Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	71	1			T48	1		T30	1		T22	2
class_index[0x1]	58	1			T21	1		T13	1		T32	1
class_index[0x2]	67	1			T3	1		T32	1		T30	1
class_index[0x3]	63	1			T21	1		T13	1		T32	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T13	2		T32	2		T30	1
intr_timeout_cnt[1]	55	1			T3	1		T48	1		T30	1
intr_timeout_cnt[2]	20	1			T30	1		T22	1		T50	1
intr_timeout_cnt[3]	17	1			T21	1		T22	4		T65	1
intr_timeout_cnt[4]	14	1			T22	3		T50	1		T57	1
intr_timeout_cnt[5]	11	1			T30	1		T22	1		T239	1
intr_timeout_cnt[6]	13	1			T21	1		T22	1		T70	1
intr_timeout_cnt[7]	12	1			T22	1		T50	1		T84	3
intr_timeout_cnt[8]	7	1			T50	1		T240	1		T241	1
intr_timeout_cnt[9]	10	1			T32	1		T241	1		T242	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2] , class_index[0x3]]	[intr_timeout_cnt[8]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	35	1			T30	1		T22	1		T81	1
class_index[0x0]	intr_timeout_cnt[1]	9	1			T48	1		T56	1		T243	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T22	1		T244	1		T245	2
class_index[0x0]	intr_timeout_cnt[3]	5	1			T66	1		T241	1		T246	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T50	1		T97	1		T247	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T241	1		T101	1		T44	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T70	1		T248	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T242	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T240	1		T249	1		T224	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T250	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T13	1		T32	1		T81	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T22	1		T252	2		T253	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T30	1		T81	1		T55	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T22	1		T65	1		T55	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T22	3		T254	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T239	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	5	1			T21	1		T85	1		T86	1
class_index[0x1]	intr_timeout_cnt[7]	4	1			T22	1		T50	1		T233	1
class_index[0x1]	intr_timeout_cnt[8]	4	1			T50	1		T241	1		T255	1
class_index[0x2]	intr_timeout_cnt[0]	19	1			T22	1		T82	1		T55	1
class_index[0x2]	intr_timeout_cnt[1]	20	1			T3	1		T80	1		T86	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T81	1		T242	1		T233	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T22	3		T57	1		T256	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T44	2		T251	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	4	1			T30	1		T42	1		T255	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T22	1		T87	1		T52	2
class_index[0x2]	intr_timeout_cnt[7]	3	1			T84	3		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	4	1			T32	1		T241	1		T242	1
class_index[0x3]	intr_timeout_cnt[0]	28	1			T13	1		T32	1		T22	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T30	1		T55	1		T57	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T50	1		T55	1		T243	2
class_index[0x3]	intr_timeout_cnt[3]	2	1			T21	1		T235	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T57	1		T239	1		T209	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T22	1		T241	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T244	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	4	1			T257	1		T258	1		T259	1
class_index[0x3]	intr_timeout_cnt[9]	4	1			T250	1		T260	2		T261	1