Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	348822	1			T1	35		T2	35		T3	31
all_values[1]	348822	1			T1	35		T2	35		T3	31
all_values[2]	348822	1			T1	35		T2	35		T3	31
all_values[3]	348822	1			T1	35		T2	35		T3	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692649

1

T1

57

T3

56

T16

32

auto[1]

702639

1

T1

83

T2

140

T3

68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

832234

1

T1

72

T2

123

T3

64

auto[1]

563054

1

T1

68

T2

17

T3

60

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99469	1			T1	9		T3	10		T16	4
all_values[0]	auto[0]	auto[1]	73730	1			T1	8		T3	10		T16	4
all_values[0]	auto[1]	auto[0]	101587	1			T1	9		T2	25		T3	6
all_values[0]	auto[1]	auto[1]	74036	1			T1	9		T2	10		T3	5
all_values[1]	auto[0]	auto[0]	103592	1			T1	2		T3	4		T16	3
all_values[1]	auto[0]	auto[1]	70185	1			T1	2		T3	4		T16	2
all_values[1]	auto[1]	auto[0]	105037	1			T1	16		T2	35		T3	12
all_values[1]	auto[1]	auto[1]	70008	1			T1	15		T3	11		T16	8
all_values[2]	auto[0]	auto[0]	103460	1			T1	8		T3	9		T16	5
all_values[2]	auto[0]	auto[1]	69322	1			T1	7		T3	9		T16	4
all_values[2]	auto[1]	auto[0]	105905	1			T1	10		T2	28		T3	7
all_values[2]	auto[1]	auto[1]	70135	1			T1	10		T2	7		T3	6
all_values[3]	auto[0]	auto[0]	105387	1			T1	11		T3	5		T16	5
all_values[3]	auto[0]	auto[1]	67504	1			T1	10		T3	5		T16	5
all_values[3]	auto[1]	auto[0]	107797	1			T1	7		T2	35		T3	11
all_values[3]	auto[1]	auto[1]	68134	1			T1	7		T3	10		T16	5