Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	348822	1			T1	35		T2	35		T3	31
all_pins[1]	348822	1			T1	35		T2	35		T3	31
all_pins[2]	348822	1			T1	35		T2	35		T3	31
all_pins[3]	348822	1			T1	35		T2	35		T3	31

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1112975	1			T1	99		T2	123		T3	92
values[0x1]	282313	1			T1	41		T2	17		T3	32
transitions[0x0=>0x1]	187196	1			T1	19		T2	16		T3	18
transitions[0x1=>0x0]	187450	1			T1	20		T2	17		T3	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274786	1			T1	26		T2	25		T3	26
all_pins[0]	values[0x1]	74036	1			T1	9		T2	10		T3	5
all_pins[0]	transitions[0x0=>0x1]	73323	1			T1	8		T2	9		T3	4
all_pins[0]	transitions[0x1=>0x0]	67675	1			T1	7		T3	10		T16	5
all_pins[1]	values[0x0]	278814	1			T1	20		T2	35		T3	20
all_pins[1]	values[0x1]	70008	1			T1	15		T3	11		T16	8
all_pins[1]	transitions[0x0=>0x1]	38160	1			T1	8		T3	7		T16	4
all_pins[1]	transitions[0x1=>0x0]	42188	1			T1	2		T2	10		T3	1
all_pins[2]	values[0x0]	278687	1			T1	25		T2	28		T3	25
all_pins[2]	values[0x1]	70135	1			T1	10		T2	7		T3	6
all_pins[2]	transitions[0x0=>0x1]	38690	1			T1	1		T2	7		T3	1
all_pins[2]	transitions[0x1=>0x0]	38563	1			T1	6		T3	6		T16	3
all_pins[3]	values[0x0]	280688	1			T1	28		T2	35		T3	21
all_pins[3]	values[0x1]	68134	1			T1	7		T3	10		T16	5
all_pins[3]	transitions[0x0=>0x1]	37023	1			T1	2		T3	6		T16	2
all_pins[3]	transitions[0x1=>0x0]	39024	1			T1	5		T2	7		T3	2