Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T152	7		T153	7		T219	4
all_values[1]	281	1			T152	7		T153	7		T219	4
all_values[2]	281	1			T152	7		T153	7		T219	4
all_values[3]	281	1			T152	7		T153	7		T219	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T152

15

T153

13

T219

7

auto[1]

520

1

T152

13

T153

15

T219

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

421

1

T152

13

T153

10

T219

8

auto[1]

703

1

T152

15

T153

18

T219

8

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662

1

T152

18

T153

18

T219

10

auto[1]

462

1

T152

10

T153

10

T219

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

60

1

T152

3

T153

1

T219

1

all_values[0]

auto[0]

auto[0]

auto[1]

22

1

T153

1

T336

1

T337

1

all_values[0]

auto[0]

auto[1]

auto[0]

58

1

T152

1

T153

2

T219

2

all_values[0]

auto[0]

auto[1]

auto[1]

32

1

T152

1

T153

1

T338

1

all_values[0]

auto[1]

auto[0]

auto[1]

51

1

T153

1

T339

2

T340

1

all_values[0]

auto[1]

auto[1]

auto[1]

58

1

T152

2

T153

1

T219

1

all_values[1]

auto[0]

auto[0]

auto[0]

69

1

T152

3

T219

2

T341

2

all_values[1]

auto[0]

auto[0]

auto[1]

36

1

T153

2

T338

1

T341

1

all_values[1]

auto[0]

auto[1]

auto[0]

39

1

T219

1

T338

1

T342

3

all_values[1]

auto[0]

auto[1]

auto[1]

26

1

T152

1

T153

2

T342

2

all_values[1]

auto[1]

auto[0]

auto[1]

64

1

T152

2

T153

2

T219

1

all_values[1]

auto[1]

auto[1]

auto[1]

47

1

T152

1

T153

1

T338

1

all_values[2]

auto[0]

auto[0]

auto[0]

51

1

T153

1

T342

2

T339

1

all_values[2]

auto[0]

auto[0]

auto[1]

36

1

T152

1

T153

1

T219

1

all_values[2]

auto[0]

auto[1]

auto[0]

40

1

T152

1

T219

1

T341

1

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T152

2

T153

1

T338

2

all_values[2]

auto[1]

auto[0]

auto[1]

73

1

T152

1

T153

1

T338

2

all_values[2]

auto[1]

auto[1]

auto[1]

54

1

T152

2

T153

3

T219

2

all_values[3]

auto[0]

auto[0]

auto[0]

50

1

T152

4

T153

2

T338

1

all_values[3]

auto[0]

auto[0]

auto[1]

33

1

T219

1

T343

2

T344

1

all_values[3]

auto[0]

auto[1]

auto[0]

54

1

T152

1

T153

4

T219

1

all_values[3]

auto[0]

auto[1]

auto[1]

29

1

T343

1

T339

1

T345

1

all_values[3]

auto[1]

auto[0]

auto[1]

59

1

T152

1

T153

1

T219

1

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T152

1

T219

1

T339

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal