Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83718	1			T7	1052		T21	284		T13	226
accum_cnt_1000	220354	1			T5	1869		T7	1162		T21	1759
accum_cnt_100	27423	1			T5	206		T7	65		T21	100
accum_cnt_50	62039	1			T1	30		T3	26		T16	22
accum_cnt_10	167556	1			T1	33		T2	27		T3	31
accum_cnt_0	424415	1			T1	41		T2	65		T3	63

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256969	1			T1	26		T2	23		T3	30
class_index[0x1]	256969	1			T1	26		T2	23		T3	30
class_index[0x2]	256969	1			T1	26		T2	23		T3	30
class_index[0x3]	256969	1			T1	26		T2	23		T3	30

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21183	1			T13	226		T14	323		T15	606
class_index[0x0]	accum_cnt_1000	65109	1			T5	846		T13	560		T14	661
class_index[0x0]	accum_cnt_100	9001	1			T5	140		T13	26		T14	37
class_index[0x0]	accum_cnt_50	16680	1			T1	4		T16	7		T5	139
class_index[0x0]	accum_cnt_10	41225	1			T1	12		T2	23		T16	4
class_index[0x0]	accum_cnt_0	92798	1			T1	10		T3	30		T16	1
class_index[0x1]	accum_cnt_2000	24142	1			T7	492		T14	247		T15	833
class_index[0x1]	accum_cnt_1000	55303	1			T5	1023		T7	659		T14	248
class_index[0x1]	accum_cnt_100	5536	1			T5	66		T7	37		T14	14
class_index[0x1]	accum_cnt_50	15864	1			T1	9		T16	6		T5	48
class_index[0x1]	accum_cnt_10	41423	1			T1	13		T3	27		T16	3
class_index[0x1]	accum_cnt_0	102985	1			T1	4		T2	23		T3	3
class_index[0x2]	accum_cnt_2000	18878	1			T21	284		T15	138		T8	189
class_index[0x2]	accum_cnt_1000	47601	1			T21	766		T15	529		T8	1165
class_index[0x2]	accum_cnt_100	6512	1			T21	23		T15	44		T8	58
class_index[0x2]	accum_cnt_50	15087	1			T3	26		T16	7		T20	15
class_index[0x2]	accum_cnt_10	38208	1			T2	4		T3	4		T16	4
class_index[0x2]	accum_cnt_0	120635	1			T1	26		T2	19		T16	1
class_index[0x3]	accum_cnt_2000	19515	1			T7	560		T14	443		T15	1096
class_index[0x3]	accum_cnt_1000	52341	1			T7	503		T21	993		T14	399
class_index[0x3]	accum_cnt_100	6374	1			T7	28		T21	77		T14	18
class_index[0x3]	accum_cnt_50	14408	1			T1	17		T16	2		T20	13
class_index[0x3]	accum_cnt_10	46700	1			T1	8		T16	6		T4	13
class_index[0x3]	accum_cnt_0	107997	1			T1	1		T2	23		T3	30