Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7965	1			T65	3		T75	79		T80	67
alert[0x1]	7188	1			T13	251		T30	48		T75	495
alert[0x2]	4869	1			T13	205		T9	1		T30	16
alert[0x3]	3906	1			T20	27		T13	2		T9	1
alert[0x4]	4912	1			T13	109		T15	8		T48	1129
alert[0x5]	4086	1			T21	34		T13	420		T15	25
alert[0x6]	2329	1			T13	10		T47	1		T78	5
alert[0x7]	7982	1			T21	195		T13	41		T15	19
alert[0x8]	5753	1			T13	14		T15	8		T48	211
alert[0x9]	6782	1			T4	1		T13	85		T15	26
alert[0xa]	9728	1			T13	38		T9	1		T47	1
alert[0xb]	3695	1			T2	1		T13	103		T47	1
alert[0xc]	13872	1			T13	24		T15	1		T48	20
alert[0xd]	9067	1			T13	14		T15	3		T30	101
alert[0xe]	7347	1			T48	126		T30	2271		T23	12
alert[0xf]	4552	1			T32	52		T30	235		T22	4
alert[0x10]	9143	1			T48	224		T30	24		T75	257
alert[0x11]	7412	1			T13	15		T9	1		T32	1
alert[0x12]	2929	1			T13	31		T9	2		T48	7
alert[0x13]	5645	1			T2	1		T21	21		T30	22
alert[0x14]	6762	1			T4	1		T13	127		T15	36
alert[0x15]	6936	1			T21	8		T13	313		T9	1
alert[0x16]	1589	1			T2	1		T13	20		T30	156
alert[0x17]	5833	1			T13	241		T48	236		T22	1
alert[0x18]	8660	1			T47	1		T48	2841		T23	8
alert[0x19]	11177	1			T4	1		T13	702		T15	41
alert[0x1a]	2892	1			T4	1		T67	1		T69	2
alert[0x1b]	9585	1			T15	15		T47	1		T78	4
alert[0x1c]	13014	1			T13	8		T15	97		T47	1
alert[0x1d]	4841	1			T13	344		T48	427		T30	378
alert[0x1e]	6333	1			T9	1		T32	3		T30	27
alert[0x1f]	5015	1			T4	1		T21	62		T13	163
alert[0x20]	7492	1			T13	1154		T15	2		T22	33
alert[0x21]	10867	1			T4	1		T15	33		T48	372
alert[0x22]	10556	1			T21	96		T13	18		T15	2
alert[0x23]	6702	1			T2	1		T9	1		T22	69
alert[0x24]	5992	1			T4	1		T65	1		T81	26
alert[0x25]	19121	1			T2	1		T21	13		T13	21
alert[0x26]	4726	1			T15	1		T9	1		T48	210
alert[0x27]	4752	1			T13	38		T15	8		T48	534
alert[0x28]	11013	1			T13	73		T8	1		T47	1
alert[0x29]	4702	1			T13	887		T15	235		T48	24
alert[0x2a]	5337	1			T21	329		T13	6		T15	52
alert[0x2b]	7327	1			T13	20		T47	1		T71	2
alert[0x2c]	17328	1			T13	21		T67	1		T69	1
alert[0x2d]	6386	1			T4	1		T13	440		T15	557
alert[0x2e]	7015	1			T21	480		T15	1		T9	1
alert[0x2f]	9446	1			T21	200		T15	3		T9	1
alert[0x30]	3823	1			T15	2		T9	1		T48	219
alert[0x31]	7151	1			T13	1		T48	70		T30	524
alert[0x32]	6405	1			T2	1		T15	360		T9	1
alert[0x33]	7113	1			T4	1		T30	267		T23	70
alert[0x34]	5205	1			T2	1		T48	63		T69	1
alert[0x35]	6184	1			T13	894		T15	2		T48	135
alert[0x36]	5924	1			T21	197		T13	141		T47	1
alert[0x37]	13584	1			T2	1		T21	279		T15	16
alert[0x38]	8255	1			T13	43		T47	1		T30	111
alert[0x39]	3707	1			T13	138		T30	3		T22	2
alert[0x3a]	3717	1			T13	95		T47	1		T32	1
alert[0x3b]	3601	1			T9	1		T32	23		T30	109
alert[0x3c]	9196	1			T2	1		T48	56		T23	67
alert[0x3d]	10115	1			T21	240		T15	214		T9	1
alert[0x3e]	4066	1			T21	14		T48	53		T23	46
alert[0x3f]	7243	1			T2	1		T30	316		T72	1
alert[0x40]	3402	1			T47	1		T48	19		T71	2

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	150418	1			T2	10		T4	5		T21	9
class_i[0x1]	84331	1			T4	1		T21	2159		T9	17
class_i[0x2]	88600	1			T4	2		T20	27		T15	1760
class_i[0x3]	135903	1			T4	1		T13	7270		T15	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

458565

1

T20

27

T21

2168

T13

7270

alert_ping_fail

687

1

T2

10

T4

9

T8

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7952	1			T65	3		T75	79		T80	67
alert_integrity_fail	alert[0x1]	7178	1			T13	251		T30	48		T75	495
alert_integrity_fail	alert[0x2]	4859	1			T13	205		T30	16		T65	3
alert_integrity_fail	alert[0x3]	3897	1			T20	27		T13	2		T48	200
alert_integrity_fail	alert[0x4]	4898	1			T13	109		T15	8		T48	1129
alert_integrity_fail	alert[0x5]	4069	1			T21	34		T13	420		T15	25
alert_integrity_fail	alert[0x6]	2319	1			T13	10		T78	5		T71	4
alert_integrity_fail	alert[0x7]	7968	1			T21	195		T13	41		T15	19
alert_integrity_fail	alert[0x8]	5741	1			T13	14		T15	8		T48	211
alert_integrity_fail	alert[0x9]	6770	1			T13	85		T15	26		T48	69
alert_integrity_fail	alert[0xa]	9711	1			T13	38		T48	212		T30	4313
alert_integrity_fail	alert[0xb]	3682	1			T13	103		T48	246		T32	3
alert_integrity_fail	alert[0xc]	13866	1			T13	24		T15	1		T48	20
alert_integrity_fail	alert[0xd]	9053	1			T13	14		T15	3		T30	101
alert_integrity_fail	alert[0xe]	7343	1			T48	126		T30	2271		T23	12
alert_integrity_fail	alert[0xf]	4546	1			T32	52		T30	235		T22	4
alert_integrity_fail	alert[0x10]	9133	1			T48	224		T30	24		T75	257
alert_integrity_fail	alert[0x11]	7406	1			T13	15		T32	1		T30	1297
alert_integrity_fail	alert[0x12]	2921	1			T13	31		T48	7		T32	2
alert_integrity_fail	alert[0x13]	5633	1			T21	21		T30	22		T23	42
alert_integrity_fail	alert[0x14]	6751	1			T13	127		T15	36		T65	1
alert_integrity_fail	alert[0x15]	6927	1			T21	8		T13	313		T30	194
alert_integrity_fail	alert[0x16]	1580	1			T13	20		T30	156		T75	7
alert_integrity_fail	alert[0x17]	5825	1			T13	241		T48	236		T22	1
alert_integrity_fail	alert[0x18]	8643	1			T48	2841		T23	8		T75	2
alert_integrity_fail	alert[0x19]	11166	1			T13	702		T15	41		T48	1104
alert_integrity_fail	alert[0x1a]	2881	1			T71	6		T50	29		T221	344
alert_integrity_fail	alert[0x1b]	9582	1			T15	15		T78	4		T75	255
alert_integrity_fail	alert[0x1c]	13005	1			T13	8		T15	97		T23	1
alert_integrity_fail	alert[0x1d]	4829	1			T13	344		T48	427		T30	378
alert_integrity_fail	alert[0x1e]	6329	1			T32	3		T30	27		T65	2
alert_integrity_fail	alert[0x1f]	5003	1			T21	62		T13	163		T22	4
alert_integrity_fail	alert[0x20]	7485	1			T13	1154		T15	2		T22	33
alert_integrity_fail	alert[0x21]	10851	1			T15	33		T48	372		T78	3
alert_integrity_fail	alert[0x22]	10544	1			T21	96		T13	18		T15	2
alert_integrity_fail	alert[0x23]	6694	1			T22	69		T75	14		T80	18
alert_integrity_fail	alert[0x24]	5979	1			T65	1		T81	26		T100	87
alert_integrity_fail	alert[0x25]	19108	1			T21	13		T13	21		T48	835
alert_integrity_fail	alert[0x26]	4713	1			T15	1		T48	210		T30	31
alert_integrity_fail	alert[0x27]	4742	1			T13	38		T15	8		T48	534
alert_integrity_fail	alert[0x28]	10992	1			T13	73		T48	442		T32	11
alert_integrity_fail	alert[0x29]	4691	1			T13	887		T15	235		T48	24
alert_integrity_fail	alert[0x2a]	5323	1			T21	329		T13	6		T15	52
alert_integrity_fail	alert[0x2b]	7318	1			T13	20		T71	2		T75	446
alert_integrity_fail	alert[0x2c]	17318	1			T13	21		T50	8		T81	7251
alert_integrity_fail	alert[0x2d]	6372	1			T13	440		T15	557		T48	8
alert_integrity_fail	alert[0x2e]	7010	1			T21	480		T15	1		T22	1
alert_integrity_fail	alert[0x2f]	9433	1			T21	200		T15	3		T75	188
alert_integrity_fail	alert[0x30]	3811	1			T15	2		T48	219		T72	22
alert_integrity_fail	alert[0x31]	7137	1			T13	1		T48	70		T30	524
alert_integrity_fail	alert[0x32]	6401	1			T15	360		T48	245		T30	65
alert_integrity_fail	alert[0x33]	7097	1			T30	267		T23	70		T75	24
alert_integrity_fail	alert[0x34]	5191	1			T48	63		T50	51		T100	33
alert_integrity_fail	alert[0x35]	6170	1			T13	894		T15	2		T48	135
alert_integrity_fail	alert[0x36]	5918	1			T21	197		T13	141		T78	1
alert_integrity_fail	alert[0x37]	13573	1			T21	279		T15	16		T48	106
alert_integrity_fail	alert[0x38]	8244	1			T13	43		T30	111		T78	11
alert_integrity_fail	alert[0x39]	3701	1			T13	138		T30	3		T22	2
alert_integrity_fail	alert[0x3a]	3707	1			T13	95		T32	1		T23	8
alert_integrity_fail	alert[0x3b]	3591	1			T32	23		T30	109		T22	45
alert_integrity_fail	alert[0x3c]	9185	1			T48	56		T23	67		T72	12
alert_integrity_fail	alert[0x3d]	10106	1			T21	240		T15	214		T48	216
alert_integrity_fail	alert[0x3e]	4057	1			T21	14		T48	53		T23	46
alert_integrity_fail	alert[0x3f]	7240	1			T30	316		T72	1		T221	172
alert_integrity_fail	alert[0x40]	3397	1			T48	19		T71	2		T75	154
alert_ping_fail	alert[0x0]	13	1			T291	4		T292	2		T293	1
alert_ping_fail	alert[0x1]	10	1			T294	1		T295	1		T293	1
alert_ping_fail	alert[0x2]	10	1			T9	1		T69	1		T105	1
alert_ping_fail	alert[0x3]	9	1			T9	1		T296	2		T295	1
alert_ping_fail	alert[0x4]	14	1			T105	2		T283	1		T297	1
alert_ping_fail	alert[0x5]	17	1			T9	1		T47	1		T69	1
alert_ping_fail	alert[0x6]	10	1			T47	1		T67	1		T297	1
alert_ping_fail	alert[0x7]	14	1			T47	1		T67	1		T222	1
alert_ping_fail	alert[0x8]	12	1			T34	1		T298	1		T299	1
alert_ping_fail	alert[0x9]	12	1			T4	1		T67	1		T299	1
alert_ping_fail	alert[0xa]	17	1			T9	1		T47	1		T300	1
alert_ping_fail	alert[0xb]	13	1			T2	1		T47	1		T69	1
alert_ping_fail	alert[0xc]	6	1			T69	1		T299	1		T301	1
alert_ping_fail	alert[0xd]	14	1			T69	1		T105	1		T302	1
alert_ping_fail	alert[0xe]	4	1			T300	1		T303	2		T304	1
alert_ping_fail	alert[0xf]	6	1			T67	1		T299	1		T305	1
alert_ping_fail	alert[0x10]	10	1			T300	1		T306	1		T292	1
alert_ping_fail	alert[0x11]	6	1			T9	1		T105	1		T299	1
alert_ping_fail	alert[0x12]	8	1			T9	2		T69	1		T307	1
alert_ping_fail	alert[0x13]	12	1			T2	1		T308	1		T309	1
alert_ping_fail	alert[0x14]	11	1			T4	1		T73	1		T294	1
alert_ping_fail	alert[0x15]	9	1			T9	1		T69	2		T297	1
alert_ping_fail	alert[0x16]	9	1			T2	1		T310	1		T205	1
alert_ping_fail	alert[0x17]	8	1			T297	1		T303	1		T311	1
alert_ping_fail	alert[0x18]	17	1			T47	1		T69	1		T296	3
alert_ping_fail	alert[0x19]	11	1			T4	1		T302	2		T306	1
alert_ping_fail	alert[0x1a]	11	1			T4	1		T67	1		T69	2
alert_ping_fail	alert[0x1b]	3	1			T47	1		T302	1		T304	1
alert_ping_fail	alert[0x1c]	9	1			T47	1		T67	1		T69	1
alert_ping_fail	alert[0x1d]	12	1			T312	1		T308	3		T306	1
alert_ping_fail	alert[0x1e]	4	1			T9	1		T306	1		T313	1
alert_ping_fail	alert[0x1f]	12	1			T4	1		T287	2		T288	1
alert_ping_fail	alert[0x20]	7	1			T105	1		T299	1		T291	1
alert_ping_fail	alert[0x21]	16	1			T4	1		T299	1		T301	1
alert_ping_fail	alert[0x22]	12	1			T9	1		T222	1		T289	1
alert_ping_fail	alert[0x23]	8	1			T2	1		T9	1		T69	1
alert_ping_fail	alert[0x24]	13	1			T4	1		T302	1		T299	1
alert_ping_fail	alert[0x25]	13	1			T2	1		T105	1		T296	1
alert_ping_fail	alert[0x26]	13	1			T9	1		T69	1		T302	1
alert_ping_fail	alert[0x27]	10	1			T67	1		T299	1		T305	1
alert_ping_fail	alert[0x28]	21	1			T8	1		T47	1		T287	1
alert_ping_fail	alert[0x29]	11	1			T297	1		T299	1		T292	1
alert_ping_fail	alert[0x2a]	14	1			T283	1		T34	1		T301	2
alert_ping_fail	alert[0x2b]	9	1			T47	1		T288	1		T34	1
alert_ping_fail	alert[0x2c]	10	1			T67	1		T69	1		T287	1
alert_ping_fail	alert[0x2d]	14	1			T4	1		T67	1		T283	1
alert_ping_fail	alert[0x2e]	5	1			T9	1		T302	1		T314	1
alert_ping_fail	alert[0x2f]	13	1			T9	1		T69	2		T297	1
alert_ping_fail	alert[0x30]	12	1			T9	1		T222	1		T300	1
alert_ping_fail	alert[0x31]	14	1			T105	1		T302	2		T299	1
alert_ping_fail	alert[0x32]	4	1			T2	1		T9	1		T294	1
alert_ping_fail	alert[0x33]	16	1			T4	1		T305	1		T292	1
alert_ping_fail	alert[0x34]	14	1			T2	1		T69	1		T299	1
alert_ping_fail	alert[0x35]	14	1			T69	1		T283	2		T306	1
alert_ping_fail	alert[0x36]	6	1			T47	1		T67	1		T297	1
alert_ping_fail	alert[0x37]	11	1			T2	1		T302	2		T305	1
alert_ping_fail	alert[0x38]	11	1			T47	1		T283	1		T306	1
alert_ping_fail	alert[0x39]	6	1			T283	1		T297	2		T315	1
alert_ping_fail	alert[0x3a]	10	1			T47	1		T67	2		T291	1
alert_ping_fail	alert[0x3b]	10	1			T9	1		T105	1		T283	1
alert_ping_fail	alert[0x3c]	11	1			T2	1		T67	1		T299	1
alert_ping_fail	alert[0x3d]	9	1			T9	1		T296	1		T306	1
alert_ping_fail	alert[0x3e]	9	1			T69	1		T316	1		T317	1
alert_ping_fail	alert[0x3f]	3	1			T2	1		T300	1		T306	1
alert_ping_fail	alert[0x40]	5	1			T47	1		T295	1		T317	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	150262	1			T21	9		T32	3		T30	11352
alert_integrity_fail	class_i[0x1]	84150	1			T21	2159		T32	84		T30	41
alert_integrity_fail	class_i[0x2]	88403	1			T20	27		T15	1760		T32	22
alert_integrity_fail	class_i[0x3]	135750	1			T13	7270		T15	7		T48	10792
alert_ping_fail	class_i[0x0]	156	1			T2	10		T4	5		T47	12
alert_ping_fail	class_i[0x1]	181	1			T4	1		T9	17		T47	1
alert_ping_fail	class_i[0x2]	197	1			T4	2		T8	1		T47	1
alert_ping_fail	class_i[0x3]	153	1			T4	1		T9	1		T67	1