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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.74 100.00 100.00 100.00 99.38 99.52


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2881247845 Mar 14 02:05:49 PM PDT 24 Mar 14 02:06:05 PM PDT 24 172278123 ps
T118 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.225506176 Mar 14 02:06:37 PM PDT 24 Mar 14 02:10:22 PM PDT 24 1735350490 ps
T773 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3676764681 Mar 14 02:07:01 PM PDT 24 Mar 14 02:07:02 PM PDT 24 6780459 ps
T774 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1266506903 Mar 14 02:06:48 PM PDT 24 Mar 14 02:06:58 PM PDT 24 243190658 ps
T775 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3980989130 Mar 14 02:06:01 PM PDT 24 Mar 14 02:16:17 PM PDT 24 74701198095 ps
T776 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2785941962 Mar 14 02:06:39 PM PDT 24 Mar 14 02:06:47 PM PDT 24 206994131 ps
T777 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2398040848 Mar 14 02:06:49 PM PDT 24 Mar 14 02:07:28 PM PDT 24 514995667 ps
T138 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3029807890 Mar 14 02:06:03 PM PDT 24 Mar 14 02:10:18 PM PDT 24 3746680760 ps
T778 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2956762904 Mar 14 02:06:04 PM PDT 24 Mar 14 02:06:35 PM PDT 24 1531212452 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3725643560 Mar 14 02:06:12 PM PDT 24 Mar 14 02:06:34 PM PDT 24 368863015 ps
T780 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3100471899 Mar 14 02:06:50 PM PDT 24 Mar 14 02:06:52 PM PDT 24 8612496 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2983051322 Mar 14 02:06:06 PM PDT 24 Mar 14 02:08:03 PM PDT 24 863662231 ps
T782 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.425080649 Mar 14 02:05:39 PM PDT 24 Mar 14 02:05:44 PM PDT 24 202679634 ps
T783 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.131533499 Mar 14 02:05:50 PM PDT 24 Mar 14 02:05:53 PM PDT 24 11759232 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1489544533 Mar 14 02:05:51 PM PDT 24 Mar 14 02:05:57 PM PDT 24 98397407 ps
T141 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2812439722 Mar 14 02:06:44 PM PDT 24 Mar 14 02:16:34 PM PDT 24 10102615622 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1525138145 Mar 14 02:06:01 PM PDT 24 Mar 14 02:10:54 PM PDT 24 4516552492 ps
T136 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2667495100 Mar 14 02:05:56 PM PDT 24 Mar 14 02:08:50 PM PDT 24 37781520166 ps
T137 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.537586002 Mar 14 02:06:25 PM PDT 24 Mar 14 02:24:48 PM PDT 24 13541868055 ps
T786 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3356007246 Mar 14 02:06:37 PM PDT 24 Mar 14 02:06:39 PM PDT 24 8025168 ps
T787 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1501394209 Mar 14 02:06:26 PM PDT 24 Mar 14 02:06:33 PM PDT 24 44554810 ps
T788 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4281406338 Mar 14 02:06:36 PM PDT 24 Mar 14 02:06:41 PM PDT 24 122030706 ps
T789 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4093245218 Mar 14 02:07:03 PM PDT 24 Mar 14 02:07:05 PM PDT 24 9936468 ps
T142 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.563379400 Mar 14 02:06:12 PM PDT 24 Mar 14 02:09:53 PM PDT 24 3107064013 ps
T790 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3558395821 Mar 14 02:07:04 PM PDT 24 Mar 14 02:07:05 PM PDT 24 11959157 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3254045019 Mar 14 02:05:38 PM PDT 24 Mar 14 02:05:53 PM PDT 24 235652161 ps
T792 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1788937272 Mar 14 02:06:37 PM PDT 24 Mar 14 02:06:49 PM PDT 24 930652397 ps
T793 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4264168991 Mar 14 02:06:13 PM PDT 24 Mar 14 02:06:15 PM PDT 24 6263729 ps
T794 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3845292538 Mar 14 02:07:00 PM PDT 24 Mar 14 02:07:02 PM PDT 24 7827999 ps
T165 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3829404933 Mar 14 02:06:13 PM PDT 24 Mar 14 02:06:17 PM PDT 24 39992437 ps
T795 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3066245089 Mar 14 02:05:49 PM PDT 24 Mar 14 02:06:00 PM PDT 24 476368247 ps
T139 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3067961353 Mar 14 02:05:56 PM PDT 24 Mar 14 02:18:31 PM PDT 24 9089063529 ps
T796 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.378178785 Mar 14 02:06:24 PM PDT 24 Mar 14 02:06:32 PM PDT 24 132869506 ps
T797 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3970730188 Mar 14 02:06:36 PM PDT 24 Mar 14 02:06:51 PM PDT 24 444899611 ps
T140 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4031527580 Mar 14 02:06:26 PM PDT 24 Mar 14 02:12:29 PM PDT 24 5053105363 ps
T798 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1893613450 Mar 14 02:06:13 PM PDT 24 Mar 14 02:06:35 PM PDT 24 652314662 ps
T170 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3591471231 Mar 14 02:06:22 PM PDT 24 Mar 14 02:07:10 PM PDT 24 1328319471 ps
T799 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1267126483 Mar 14 02:05:49 PM PDT 24 Mar 14 02:06:03 PM PDT 24 1099481289 ps
T135 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3532575699 Mar 14 02:06:36 PM PDT 24 Mar 14 02:10:14 PM PDT 24 2155817100 ps
T800 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3772070123 Mar 14 02:06:02 PM PDT 24 Mar 14 02:06:10 PM PDT 24 88552864 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1160263774 Mar 14 02:05:37 PM PDT 24 Mar 14 02:09:26 PM PDT 24 2961876642 ps
T802 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2357420655 Mar 14 02:06:24 PM PDT 24 Mar 14 02:06:41 PM PDT 24 344283212 ps
T803 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3285541965 Mar 14 02:06:59 PM PDT 24 Mar 14 02:07:01 PM PDT 24 15183981 ps
T804 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2212566567 Mar 14 02:06:01 PM PDT 24 Mar 14 02:06:04 PM PDT 24 10452631 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4238591131 Mar 14 02:05:49 PM PDT 24 Mar 14 02:06:28 PM PDT 24 1049018248 ps
T806 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2281431735 Mar 14 02:06:25 PM PDT 24 Mar 14 02:06:28 PM PDT 24 11842411 ps
T807 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1118067819 Mar 14 02:06:04 PM PDT 24 Mar 14 02:06:11 PM PDT 24 51020202 ps
T144 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3970478022 Mar 14 02:06:25 PM PDT 24 Mar 14 02:14:25 PM PDT 24 30673164352 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1162711241 Mar 14 02:05:50 PM PDT 24 Mar 14 02:08:12 PM PDT 24 1837781306 ps
T163 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1739026781 Mar 14 02:06:38 PM PDT 24 Mar 14 02:07:52 PM PDT 24 8062127164 ps
T146 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.321806241 Mar 14 02:05:38 PM PDT 24 Mar 14 02:15:38 PM PDT 24 33206637051 ps
T809 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2345463415 Mar 14 02:06:01 PM PDT 24 Mar 14 02:06:03 PM PDT 24 9797280 ps
T164 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4031628776 Mar 14 02:06:02 PM PDT 24 Mar 14 02:07:29 PM PDT 24 1276139267 ps
T145 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2594755740 Mar 14 02:06:25 PM PDT 24 Mar 14 02:09:06 PM PDT 24 8406002604 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1964156229 Mar 14 02:05:37 PM PDT 24 Mar 14 02:11:10 PM PDT 24 13370419751 ps
T811 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.377192400 Mar 14 02:06:14 PM PDT 24 Mar 14 02:06:33 PM PDT 24 335133771 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1613786433 Mar 14 02:06:17 PM PDT 24 Mar 14 02:06:26 PM PDT 24 226787338 ps
T813 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2177227221 Mar 14 02:06:58 PM PDT 24 Mar 14 02:07:01 PM PDT 24 19974470 ps
T814 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.805327006 Mar 14 02:06:58 PM PDT 24 Mar 14 02:07:01 PM PDT 24 16538967 ps
T815 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3776361378 Mar 14 02:06:48 PM PDT 24 Mar 14 02:06:52 PM PDT 24 23878250 ps
T816 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.594059760 Mar 14 02:07:05 PM PDT 24 Mar 14 02:07:06 PM PDT 24 41134379 ps
T817 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.955343758 Mar 14 02:07:03 PM PDT 24 Mar 14 02:07:04 PM PDT 24 13092921 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2248922227 Mar 14 02:05:50 PM PDT 24 Mar 14 02:05:57 PM PDT 24 227843431 ps
T819 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1481159400 Mar 14 02:06:51 PM PDT 24 Mar 14 02:07:06 PM PDT 24 1580582492 ps
T820 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2630870751 Mar 14 02:06:26 PM PDT 24 Mar 14 02:06:54 PM PDT 24 1081894788 ps
T821 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3995603272 Mar 14 02:06:06 PM PDT 24 Mar 14 02:06:26 PM PDT 24 474246857 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.19915286 Mar 14 02:05:38 PM PDT 24 Mar 14 02:05:42 PM PDT 24 103853074 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1496579444 Mar 14 02:06:15 PM PDT 24 Mar 14 02:06:19 PM PDT 24 25001433 ps
T157 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3681366917 Mar 14 02:05:37 PM PDT 24 Mar 14 02:05:40 PM PDT 24 123163734 ps
T824 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3476885716 Mar 14 02:06:59 PM PDT 24 Mar 14 02:07:01 PM PDT 24 12616424 ps
T825 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.47870462 Mar 14 02:06:12 PM PDT 24 Mar 14 02:06:41 PM PDT 24 760838137 ps
T156 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.900873118 Mar 14 02:06:13 PM PDT 24 Mar 14 02:07:35 PM PDT 24 1273587958 ps
T143 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1828881028 Mar 14 02:06:49 PM PDT 24 Mar 14 02:12:31 PM PDT 24 17172749894 ps
T147 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2320224826 Mar 14 02:05:37 PM PDT 24 Mar 14 02:09:37 PM PDT 24 6874181909 ps
T826 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1137101622 Mar 14 02:05:37 PM PDT 24 Mar 14 02:07:05 PM PDT 24 822749329 ps
T827 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2210194472 Mar 14 02:06:38 PM PDT 24 Mar 14 02:06:46 PM PDT 24 64644191 ps
T828 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3554601986 Mar 14 02:05:40 PM PDT 24 Mar 14 02:05:53 PM PDT 24 177027688 ps
T829 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.248395443 Mar 14 02:06:39 PM PDT 24 Mar 14 02:07:07 PM PDT 24 337552033 ps
T830 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.24434038 Mar 14 02:06:55 PM PDT 24 Mar 14 02:06:59 PM PDT 24 130648327 ps
T238 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4263750855 Mar 14 02:06:52 PM PDT 24 Mar 14 02:07:14 PM PDT 24 174812254 ps
T831 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2993736082 Mar 14 02:06:50 PM PDT 24 Mar 14 02:06:59 PM PDT 24 661249407 ps

Test location /workspace/coverage/default/13.alert_handler_random_classes.1181782448
Short name T1
Test name
Test status
Simulation time 3287970859 ps
CPU time 51.35 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:09:03 PM PDT 24
Peak memory 249172 kb
Host smart-160d9f40-8769-4e03-80aa-46ab71704bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11817
82448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1181782448
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2376113750
Short name T15
Test name
Test status
Simulation time 98835806521 ps
CPU time 8455.76 seconds
Started Mar 14 02:10:36 PM PDT 24
Finished Mar 14 04:31:34 PM PDT 24
Peak memory 420532 kb
Host smart-74aa7d0a-258e-4cc9-a6a9-26ceca9f6ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376113750 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2376113750
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4290662943
Short name T10
Test name
Test status
Simulation time 1333331786 ps
CPU time 21.52 seconds
Started Mar 14 02:07:39 PM PDT 24
Finished Mar 14 02:08:01 PM PDT 24
Peak memory 274132 kb
Host smart-bf9f7af5-ed52-488e-a210-018faef5b23b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4290662943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4290662943
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3487543005
Short name T30
Test name
Test status
Simulation time 132338106740 ps
CPU time 3658.04 seconds
Started Mar 14 02:09:02 PM PDT 24
Finished Mar 14 03:10:02 PM PDT 24
Peak memory 305808 kb
Host smart-c7ca5a73-0f37-4905-8853-163ab63860d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487543005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3487543005
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.742917533
Short name T155
Test name
Test status
Simulation time 2600072933 ps
CPU time 88.87 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:08:19 PM PDT 24
Peak memory 239356 kb
Host smart-24d91731-3fca-45d4-a65e-ba54553604f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=742917533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.742917533
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3531704039
Short name T5
Test name
Test status
Simulation time 31328829120 ps
CPU time 1373.18 seconds
Started Mar 14 02:08:16 PM PDT 24
Finished Mar 14 02:31:09 PM PDT 24
Peak memory 289132 kb
Host smart-e51b720a-6507-4fe6-adb3-6284906f9043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531704039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3531704039
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4244054524
Short name T91
Test name
Test status
Simulation time 187456577976 ps
CPU time 2527.8 seconds
Started Mar 14 02:07:59 PM PDT 24
Finished Mar 14 02:50:07 PM PDT 24
Peak memory 281796 kb
Host smart-a2483cdd-e0a3-4900-83aa-98cde6607340
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244054524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4244054524
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3616270156
Short name T59
Test name
Test status
Simulation time 122702999607 ps
CPU time 7486.52 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 04:12:57 PM PDT 24
Peak memory 355412 kb
Host smart-e1b3bb7d-6414-4b50-9c57-370c13a41711
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616270156 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3616270156
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.513943311
Short name T114
Test name
Test status
Simulation time 16896599881 ps
CPU time 1247.5 seconds
Started Mar 14 02:06:22 PM PDT 24
Finished Mar 14 02:27:12 PM PDT 24
Peak memory 272744 kb
Host smart-6a6ac1b6-e122-4bfc-9df9-49ab7b06fa46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513943311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.513943311
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1246483674
Short name T479
Test name
Test status
Simulation time 412804586594 ps
CPU time 3245.45 seconds
Started Mar 14 02:08:10 PM PDT 24
Finished Mar 14 03:02:16 PM PDT 24
Peak memory 302616 kb
Host smart-c5396c6a-2f4d-46ad-9a5e-dd9b450859d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246483674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1246483674
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3291660330
Short name T124
Test name
Test status
Simulation time 2008533569 ps
CPU time 229.3 seconds
Started Mar 14 02:06:22 PM PDT 24
Finished Mar 14 02:10:13 PM PDT 24
Peak memory 270204 kb
Host smart-637868f1-969d-4886-8a9d-0ea76ef72e06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3291660330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3291660330
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3125543218
Short name T34
Test name
Test status
Simulation time 110859224939 ps
CPU time 1606.71 seconds
Started Mar 14 02:07:55 PM PDT 24
Finished Mar 14 02:34:43 PM PDT 24
Peak memory 272756 kb
Host smart-f6aaf820-78fb-4171-a2c7-589d614964b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125543218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3125543218
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4239931601
Short name T113
Test name
Test status
Simulation time 21750294148 ps
CPU time 330.37 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:12:07 PM PDT 24
Peak memory 265044 kb
Host smart-67028bd2-1cf2-4dcc-9164-61cc8a6468ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4239931601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4239931601
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1865253659
Short name T48
Test name
Test status
Simulation time 1005333069436 ps
CPU time 3101.21 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 03:01:19 PM PDT 24
Peak memory 288892 kb
Host smart-f9a0aa4d-67c3-48a7-b2ac-666aa88dea6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865253659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1865253659
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2730022772
Short name T132
Test name
Test status
Simulation time 4787525681 ps
CPU time 766.24 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:19:22 PM PDT 24
Peak memory 265064 kb
Host smart-176575b0-ec71-4586-80c6-432ad0485568
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730022772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2730022772
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2384164747
Short name T67
Test name
Test status
Simulation time 9166771866 ps
CPU time 357.15 seconds
Started Mar 14 02:12:02 PM PDT 24
Finished Mar 14 02:18:00 PM PDT 24
Peak memory 249140 kb
Host smart-106e1c86-a5f8-4734-a419-5afb0d9cbdd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384164747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2384164747
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1069693876
Short name T153
Test name
Test status
Simulation time 8905250 ps
CPU time 1.57 seconds
Started Mar 14 02:07:04 PM PDT 24
Finished Mar 14 02:07:06 PM PDT 24
Peak memory 236308 kb
Host smart-5a652b0c-7684-4592-8faf-dc2f5bee01ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1069693876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1069693876
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1773934411
Short name T50
Test name
Test status
Simulation time 385905915109 ps
CPU time 5961.63 seconds
Started Mar 14 02:12:59 PM PDT 24
Finished Mar 14 03:52:22 PM PDT 24
Peak memory 338284 kb
Host smart-264ff2b9-bc3e-49c7-9dd4-9dacef8df995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773934411 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1773934411
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2169411339
Short name T290
Test name
Test status
Simulation time 98324807998 ps
CPU time 1297.63 seconds
Started Mar 14 02:09:15 PM PDT 24
Finished Mar 14 02:30:53 PM PDT 24
Peak memory 273576 kb
Host smart-c0e50d20-a06f-4088-8788-6d3db75267e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169411339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2169411339
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2699903152
Short name T123
Test name
Test status
Simulation time 9334379175 ps
CPU time 618.95 seconds
Started Mar 14 02:06:15 PM PDT 24
Finished Mar 14 02:16:34 PM PDT 24
Peak memory 265028 kb
Host smart-2420a18d-a2bf-408e-9245-99d4d164be34
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699903152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2699903152
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1658926894
Short name T9
Test name
Test status
Simulation time 12868617441 ps
CPU time 549.91 seconds
Started Mar 14 02:10:58 PM PDT 24
Finished Mar 14 02:20:09 PM PDT 24
Peak memory 248316 kb
Host smart-ecbd6b27-3593-41cb-acb5-cd8e0525702a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658926894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1658926894
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3220849568
Short name T129
Test name
Test status
Simulation time 2066499748 ps
CPU time 166.21 seconds
Started Mar 14 02:06:22 PM PDT 24
Finished Mar 14 02:09:10 PM PDT 24
Peak memory 264876 kb
Host smart-ab34f759-6b37-40b3-89b7-1636be2f6f6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3220849568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3220849568
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3453581229
Short name T22
Test name
Test status
Simulation time 54341965872 ps
CPU time 3356.87 seconds
Started Mar 14 02:10:17 PM PDT 24
Finished Mar 14 03:06:14 PM PDT 24
Peak memory 306040 kb
Host smart-ea6780d7-a35c-4892-957d-aaf8622c8e34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453581229 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3453581229
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4574514
Short name T318
Test name
Test status
Simulation time 117791001339 ps
CPU time 1359.27 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:34:03 PM PDT 24
Peak memory 289072 kb
Host smart-28547cc1-c8fe-4bb4-abec-845daea46dce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4574514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4574514
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3029807890
Short name T138
Test name
Test status
Simulation time 3746680760 ps
CPU time 254.58 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:10:18 PM PDT 24
Peak memory 273152 kb
Host smart-ebc0437e-8d6d-4e33-86c4-0f36a9c0d847
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3029807890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3029807890
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3481744287
Short name T293
Test name
Test status
Simulation time 59011797999 ps
CPU time 590.46 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:18:03 PM PDT 24
Peak memory 248404 kb
Host smart-b9be1fa0-e6ec-4bae-87a4-1747a1d7231f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481744287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3481744287
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.143247609
Short name T330
Test name
Test status
Simulation time 124526432340 ps
CPU time 3570.52 seconds
Started Mar 14 02:08:51 PM PDT 24
Finished Mar 14 03:08:22 PM PDT 24
Peak memory 289652 kb
Host smart-8e048f3f-cabd-4641-8c7b-0316a77182f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143247609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.143247609
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3828675082
Short name T115
Test name
Test status
Simulation time 12778826268 ps
CPU time 931.53 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:21:43 PM PDT 24
Peak memory 271180 kb
Host smart-ee43efe3-eb6a-44cc-86e8-6a5a122f8857
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828675082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3828675082
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3141754024
Short name T299
Test name
Test status
Simulation time 15095885348 ps
CPU time 325.81 seconds
Started Mar 14 02:08:57 PM PDT 24
Finished Mar 14 02:14:25 PM PDT 24
Peak memory 248128 kb
Host smart-86aa4fe4-210c-4551-8b5a-b5947fa0e2a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141754024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3141754024
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2436158108
Short name T322
Test name
Test status
Simulation time 27172309808 ps
CPU time 1441.01 seconds
Started Mar 14 02:09:19 PM PDT 24
Finished Mar 14 02:33:20 PM PDT 24
Peak memory 272948 kb
Host smart-e4476402-5c1d-43bf-8138-ce6e2d18630d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436158108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2436158108
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3613218845
Short name T55
Test name
Test status
Simulation time 55287350810 ps
CPU time 2940.16 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:59:16 PM PDT 24
Peak memory 290064 kb
Host smart-c92bec06-2438-4fce-bd13-141c22cf41bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613218845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3613218845
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.338557074
Short name T126
Test name
Test status
Simulation time 27163605976 ps
CPU time 1010.86 seconds
Started Mar 14 02:06:56 PM PDT 24
Finished Mar 14 02:23:47 PM PDT 24
Peak memory 265052 kb
Host smart-c48df498-ed25-4139-beab-43c678ae004d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338557074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.338557074
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.173423816
Short name T205
Test name
Test status
Simulation time 86081874747 ps
CPU time 2341.48 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:47:16 PM PDT 24
Peak memory 289664 kb
Host smart-7863ee53-0ac4-4779-8e59-8dd47642c371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173423816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.173423816
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.58063225
Short name T32
Test name
Test status
Simulation time 37898587661 ps
CPU time 1118.49 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:26:41 PM PDT 24
Peak memory 273720 kb
Host smart-0f458135-e1f4-4c19-ac1b-7a11b2b6e347
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58063225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_hand
ler_stress_all.58063225
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1828881028
Short name T143
Test name
Test status
Simulation time 17172749894 ps
CPU time 340.27 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:12:31 PM PDT 24
Peak memory 265048 kb
Host smart-59ca08a0-b852-4011-b472-9a9bbabdafc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1828881028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1828881028
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.584282982
Short name T740
Test name
Test status
Simulation time 17180463 ps
CPU time 1.29 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:05:38 PM PDT 24
Peak memory 236384 kb
Host smart-ec6809de-29b3-4182-b756-983c3242b380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=584282982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.584282982
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2467277866
Short name T86
Test name
Test status
Simulation time 13909434476 ps
CPU time 412.49 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:17:06 PM PDT 24
Peak memory 257376 kb
Host smart-a25069d1-a899-4d65-ab27-cc0917ae0838
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467277866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2467277866
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.556715085
Short name T150
Test name
Test status
Simulation time 299512615 ps
CPU time 60.05 seconds
Started Mar 14 02:06:35 PM PDT 24
Finished Mar 14 02:07:36 PM PDT 24
Peak memory 236624 kb
Host smart-1485d828-0c21-42b7-adf5-69ce9477758b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=556715085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.556715085
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.672306624
Short name T573
Test name
Test status
Simulation time 11915766256 ps
CPU time 246.2 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:12:29 PM PDT 24
Peak memory 248120 kb
Host smart-7a133698-dc08-4e23-98b9-a527f6e406d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672306624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.672306624
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1187978696
Short name T210
Test name
Test status
Simulation time 123540756295 ps
CPU time 1862.88 seconds
Started Mar 14 02:09:29 PM PDT 24
Finished Mar 14 02:40:32 PM PDT 24
Peak memory 270136 kb
Host smart-d09c8621-f49d-48ec-a487-9e8e598c5c4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187978696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1187978696
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2691811120
Short name T209
Test name
Test status
Simulation time 176254512038 ps
CPU time 1701.54 seconds
Started Mar 14 02:09:00 PM PDT 24
Finished Mar 14 02:37:22 PM PDT 24
Peak memory 281936 kb
Host smart-9aadd694-d2b7-4a5e-b78d-bcd39bd00135
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691811120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2691811120
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.2130119542
Short name T44
Test name
Test status
Simulation time 127023135526 ps
CPU time 3567.78 seconds
Started Mar 14 02:10:14 PM PDT 24
Finished Mar 14 03:09:42 PM PDT 24
Peak memory 355256 kb
Host smart-98d5fc79-f846-4f2e-8b41-eea2bca532a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130119542 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.2130119542
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2188060415
Short name T624
Test name
Test status
Simulation time 80156788345 ps
CPU time 2055.41 seconds
Started Mar 14 02:10:58 PM PDT 24
Finished Mar 14 02:45:14 PM PDT 24
Peak memory 273424 kb
Host smart-74386ee8-26fb-4137-b3a7-703b4640c938
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188060415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2188060415
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1504514936
Short name T304
Test name
Test status
Simulation time 88704557393 ps
CPU time 466.22 seconds
Started Mar 14 02:12:49 PM PDT 24
Finished Mar 14 02:20:36 PM PDT 24
Peak memory 255012 kb
Host smart-da1e57f2-5e3b-44a7-8f96-f2cd3ca19903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504514936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1504514936
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1307001414
Short name T134
Test name
Test status
Simulation time 12621586916 ps
CPU time 1060.14 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:24:17 PM PDT 24
Peak memory 265244 kb
Host smart-674f7101-fea3-4d5f-baeb-73dc7eda06e1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307001414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1307001414
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.582275657
Short name T116
Test name
Test status
Simulation time 1048129064 ps
CPU time 110.37 seconds
Started Mar 14 02:06:02 PM PDT 24
Finished Mar 14 02:07:52 PM PDT 24
Peak memory 256736 kb
Host smart-570f3c0b-5fef-4aaf-98e9-a0e8b6179ebe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=582275657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.582275657
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3324257354
Short name T192
Test name
Test status
Simulation time 190505544 ps
CPU time 4.5 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:07:26 PM PDT 24
Peak memory 249292 kb
Host smart-7c000fad-f94b-4f69-8c8b-9e0908d7b06a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3324257354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3324257354
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3939727405
Short name T189
Test name
Test status
Simulation time 72544059 ps
CPU time 3.45 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:08:05 PM PDT 24
Peak memory 249212 kb
Host smart-1ef2ebeb-36f8-4e89-936e-08d0445634e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3939727405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3939727405
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2743910486
Short name T199
Test name
Test status
Simulation time 115798431 ps
CPU time 3.38 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:08:16 PM PDT 24
Peak memory 249344 kb
Host smart-8e37e8ff-40a0-412a-9237-4223ae3d41a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2743910486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2743910486
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1265019137
Short name T197
Test name
Test status
Simulation time 82738222 ps
CPU time 3.92 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:07:57 PM PDT 24
Peak memory 249320 kb
Host smart-e3f161f7-fa8a-41b3-ad2c-a8e038cff94b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1265019137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1265019137
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.654328941
Short name T626
Test name
Test status
Simulation time 157789972287 ps
CPU time 2218.68 seconds
Started Mar 14 02:07:11 PM PDT 24
Finished Mar 14 02:44:10 PM PDT 24
Peak memory 288928 kb
Host smart-22925d3e-eca7-44ae-930c-6060373cd62c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654328941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.654328941
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1678528742
Short name T242
Test name
Test status
Simulation time 20594096560 ps
CPU time 1488.12 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:32:50 PM PDT 24
Peak memory 286696 kb
Host smart-d9f01952-8e27-4ce3-8019-b1d79d225c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678528742 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1678528742
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4099763186
Short name T316
Test name
Test status
Simulation time 9281226926 ps
CPU time 366.56 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:14:09 PM PDT 24
Peak memory 248244 kb
Host smart-754b30dc-5b1d-4e84-940a-76dd48a330b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099763186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4099763186
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.282851445
Short name T42
Test name
Test status
Simulation time 2941283708 ps
CPU time 42.45 seconds
Started Mar 14 02:08:28 PM PDT 24
Finished Mar 14 02:09:11 PM PDT 24
Peak memory 255504 kb
Host smart-91e845eb-f114-4ce2-b44f-d7176197d602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285
1445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.282851445
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3452276936
Short name T251
Test name
Test status
Simulation time 101027916921 ps
CPU time 2808.49 seconds
Started Mar 14 02:10:45 PM PDT 24
Finished Mar 14 02:57:34 PM PDT 24
Peak memory 290104 kb
Host smart-ef52cfd4-32be-47ba-a7ce-0d772c2ce1f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452276936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3452276936
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3025200647
Short name T161
Test name
Test status
Simulation time 114456687 ps
CPU time 3.19 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:05:55 PM PDT 24
Peak memory 236340 kb
Host smart-fa310e8b-1448-4341-8327-1e629bc33c61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3025200647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3025200647
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3970478022
Short name T144
Test name
Test status
Simulation time 30673164352 ps
CPU time 478.8 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:14:25 PM PDT 24
Peak memory 265076 kb
Host smart-a4949c23-1400-4bd9-99ed-f538f6e867f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970478022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3970478022
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4031628776
Short name T164
Test name
Test status
Simulation time 1276139267 ps
CPU time 85.84 seconds
Started Mar 14 02:06:02 PM PDT 24
Finished Mar 14 02:07:29 PM PDT 24
Peak memory 239204 kb
Host smart-88e39a58-eae4-4b26-b1e6-b931ee0ecdc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4031628776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4031628776
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.796005873
Short name T13
Test name
Test status
Simulation time 18961430163 ps
CPU time 895.68 seconds
Started Mar 14 02:07:20 PM PDT 24
Finished Mar 14 02:22:16 PM PDT 24
Peak memory 273740 kb
Host smart-2a813640-5a89-4f4c-968f-0480a0fa0a2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796005873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.796005873
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3532575699
Short name T135
Test name
Test status
Simulation time 2155817100 ps
CPU time 217.44 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:10:14 PM PDT 24
Peak memory 270164 kb
Host smart-264dc766-2531-4f11-bb9b-a99a2197d6ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3532575699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3532575699
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2327466714
Short name T345
Test name
Test status
Simulation time 8716923 ps
CPU time 1.76 seconds
Started Mar 14 02:05:38 PM PDT 24
Finished Mar 14 02:05:40 PM PDT 24
Peak memory 236368 kb
Host smart-ae1f123e-d770-4ac1-b4da-9ee2602fb6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2327466714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2327466714
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1563914003
Short name T315
Test name
Test status
Simulation time 2945305346 ps
CPU time 103.01 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:08:53 PM PDT 24
Peak memory 248040 kb
Host smart-113a7bfc-3fad-4e15-93e1-06ecdd3340b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563914003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1563914003
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1336609483
Short name T76
Test name
Test status
Simulation time 35907714464 ps
CPU time 659.01 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 02:19:09 PM PDT 24
Peak memory 265552 kb
Host smart-74be8976-55e8-4660-8b39-55017ffdb05b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336609483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1336609483
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4112299198
Short name T263
Test name
Test status
Simulation time 565741080 ps
CPU time 15.29 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 02:08:24 PM PDT 24
Peak memory 249048 kb
Host smart-26b6ec85-cbc7-4513-9dca-9cde0507fde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41122
99198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4112299198
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4045322977
Short name T66
Test name
Test status
Simulation time 3111810151 ps
CPU time 50.8 seconds
Started Mar 14 02:08:38 PM PDT 24
Finished Mar 14 02:09:29 PM PDT 24
Peak memory 249180 kb
Host smart-e3665706-7776-4e8e-b5c6-0fbf8594661a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40453
22977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4045322977
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3093579732
Short name T249
Test name
Test status
Simulation time 68709952 ps
CPU time 7.21 seconds
Started Mar 14 02:08:39 PM PDT 24
Finished Mar 14 02:08:47 PM PDT 24
Peak memory 249056 kb
Host smart-15ef8068-9be5-4dfb-ae28-de319c58b2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30935
79732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3093579732
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3365992590
Short name T264
Test name
Test status
Simulation time 2615779208 ps
CPU time 38.43 seconds
Started Mar 14 02:08:48 PM PDT 24
Finished Mar 14 02:09:27 PM PDT 24
Peak memory 248344 kb
Host smart-3ab31e60-95b1-4d7b-8e65-22b26f3eb9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
92590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3365992590
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2338636063
Short name T260
Test name
Test status
Simulation time 254592203134 ps
CPU time 3416.57 seconds
Started Mar 14 02:08:59 PM PDT 24
Finished Mar 14 03:05:57 PM PDT 24
Peak memory 290308 kb
Host smart-6dd80ae4-ed3c-4e66-b2b4-25ddafac985c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338636063 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2338636063
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3990066522
Short name T248
Test name
Test status
Simulation time 44149163151 ps
CPU time 2437.43 seconds
Started Mar 14 02:09:02 PM PDT 24
Finished Mar 14 02:49:40 PM PDT 24
Peak memory 300836 kb
Host smart-3c2503a0-d084-4b04-acc0-d9f5bf396831
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990066522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3990066522
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3568683526
Short name T235
Test name
Test status
Simulation time 1715146837 ps
CPU time 27.19 seconds
Started Mar 14 02:09:15 PM PDT 24
Finished Mar 14 02:09:43 PM PDT 24
Peak memory 255272 kb
Host smart-6ac00692-96fa-45fe-bcfc-f993ed91cb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35686
83526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3568683526
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1391419143
Short name T84
Test name
Test status
Simulation time 869113538 ps
CPU time 52.18 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:10:30 PM PDT 24
Peak memory 249060 kb
Host smart-15e9e69f-2125-4731-83ad-37e1357f6d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
19143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1391419143
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.591233365
Short name T108
Test name
Test status
Simulation time 6852005366 ps
CPU time 39.29 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:08:02 PM PDT 24
Peak memory 255616 kb
Host smart-366d83a7-5291-4b01-ad7e-f2c7302e9709
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591233365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.591233365
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1793311001
Short name T300
Test name
Test status
Simulation time 4341565658 ps
CPU time 150.37 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:12:47 PM PDT 24
Peak memory 248324 kb
Host smart-33996d5a-d752-4cd0-bd57-ad9fe642ea9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793311001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1793311001
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2669791963
Short name T698
Test name
Test status
Simulation time 9114834881 ps
CPU time 819.99 seconds
Started Mar 14 02:10:21 PM PDT 24
Finished Mar 14 02:24:01 PM PDT 24
Peak memory 273184 kb
Host smart-8a6ed015-2a05-4143-b1b5-630d57eed369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669791963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2669791963
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4133355786
Short name T271
Test name
Test status
Simulation time 14994579765 ps
CPU time 1155.51 seconds
Started Mar 14 02:11:10 PM PDT 24
Finished Mar 14 02:30:26 PM PDT 24
Peak memory 284884 kb
Host smart-aa93bb21-2e97-4eaa-9c3a-36af6667dded
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133355786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4133355786
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1696020106
Short name T244
Test name
Test status
Simulation time 5169763637 ps
CPU time 75.46 seconds
Started Mar 14 02:11:36 PM PDT 24
Finished Mar 14 02:12:51 PM PDT 24
Peak memory 256944 kb
Host smart-58eecd5e-2fd2-44c6-adb5-6ec3f3ae5279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16960
20106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1696020106
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1221470194
Short name T239
Test name
Test status
Simulation time 724565258 ps
CPU time 49.11 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:08:44 PM PDT 24
Peak memory 255304 kb
Host smart-409381ff-cf4c-4a0e-a117-eb7c7e11c9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12214
70194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1221470194
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2320224826
Short name T147
Test name
Test status
Simulation time 6874181909 ps
CPU time 239.79 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:09:37 PM PDT 24
Peak memory 265044 kb
Host smart-28a4b944-5023-4e4a-967f-e55d04a30b21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2320224826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2320224826
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1255023913
Short name T162
Test name
Test status
Simulation time 5514127331 ps
CPU time 39.84 seconds
Started Mar 14 02:06:55 PM PDT 24
Finished Mar 14 02:07:35 PM PDT 24
Peak memory 236804 kb
Host smart-73768f8f-fcc1-4e46-b1d5-6ae5af8f03ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1255023913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1255023913
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3494612559
Short name T154
Test name
Test status
Simulation time 209036331 ps
CPU time 3.83 seconds
Started Mar 14 02:06:26 PM PDT 24
Finished Mar 14 02:06:30 PM PDT 24
Peak memory 236360 kb
Host smart-67db3e52-b3c8-4899-bef5-e140a1eafd13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3494612559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3494612559
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3982403585
Short name T166
Test name
Test status
Simulation time 208549782 ps
CPU time 3.89 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:06:40 PM PDT 24
Peak memory 236372 kb
Host smart-ab8f1c98-98dd-4e78-a467-7f437e8f0b73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3982403585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3982403585
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3558676602
Short name T167
Test name
Test status
Simulation time 70153658 ps
CPU time 4.1 seconds
Started Mar 14 02:05:48 PM PDT 24
Finished Mar 14 02:05:53 PM PDT 24
Peak memory 236372 kb
Host smart-8971a781-7d5a-4c5d-9c9e-b41cdb9fcb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3558676602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3558676602
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.900873118
Short name T156
Test name
Test status
Simulation time 1273587958 ps
CPU time 82.56 seconds
Started Mar 14 02:06:13 PM PDT 24
Finished Mar 14 02:07:35 PM PDT 24
Peak memory 239204 kb
Host smart-20fc399e-9934-4db9-bd51-d12abc0fe7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=900873118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.900873118
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.220185454
Short name T148
Test name
Test status
Simulation time 552598572 ps
CPU time 3.51 seconds
Started Mar 14 02:05:41 PM PDT 24
Finished Mar 14 02:05:45 PM PDT 24
Peak memory 236732 kb
Host smart-61883a3f-f89d-485c-9c14-a41792ae6672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=220185454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.220185454
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1622228675
Short name T159
Test name
Test status
Simulation time 310049327 ps
CPU time 48.15 seconds
Started Mar 14 02:06:24 PM PDT 24
Finished Mar 14 02:07:14 PM PDT 24
Peak memory 240020 kb
Host smart-e6c6b853-709a-4b5a-9534-ea34f45f047c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1622228675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1622228675
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.225506176
Short name T118
Test name
Test status
Simulation time 1735350490 ps
CPU time 224.63 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:10:22 PM PDT 24
Peak memory 269868 kb
Host smart-ea1b6e6f-d3de-4333-9260-658c3584dd98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=225506176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.225506176
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3471733705
Short name T160
Test name
Test status
Simulation time 1157864890 ps
CPU time 36.19 seconds
Started Mar 14 02:06:40 PM PDT 24
Finished Mar 14 02:07:17 PM PDT 24
Peak memory 239236 kb
Host smart-f0aff19a-610b-494a-bc3a-1b2a7dd43096
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3471733705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3471733705
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3829404933
Short name T165
Test name
Test status
Simulation time 39992437 ps
CPU time 3.59 seconds
Started Mar 14 02:06:13 PM PDT 24
Finished Mar 14 02:06:17 PM PDT 24
Peak memory 236728 kb
Host smart-e293d689-3cec-40ec-aad1-745962b5b8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3829404933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3829404933
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3681366917
Short name T157
Test name
Test status
Simulation time 123163734 ps
CPU time 2.83 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:05:40 PM PDT 24
Peak memory 236348 kb
Host smart-8dd64c8c-4df9-41d0-8cd5-5532dc3bff5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3681366917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3681366917
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1739026781
Short name T163
Test name
Test status
Simulation time 8062127164 ps
CPU time 74.15 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:07:52 PM PDT 24
Peak memory 237968 kb
Host smart-3853f1bd-6569-4ff5-9581-be0868af784b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1739026781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1739026781
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3851594549
Short name T158
Test name
Test status
Simulation time 130989307 ps
CPU time 3.26 seconds
Started Mar 14 02:06:01 PM PDT 24
Finished Mar 14 02:06:05 PM PDT 24
Peak memory 236356 kb
Host smart-3a4927bb-af21-41a3-9926-65b81fac120f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3851594549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3851594549
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3591471231
Short name T170
Test name
Test status
Simulation time 1328319471 ps
CPU time 47.45 seconds
Started Mar 14 02:06:22 PM PDT 24
Finished Mar 14 02:07:10 PM PDT 24
Peak memory 239372 kb
Host smart-d8d59bb9-643c-436b-ad38-6e8b664b7aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3591471231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3591471231
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2830793117
Short name T26
Test name
Test status
Simulation time 1058955341 ps
CPU time 38.84 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:08:51 PM PDT 24
Peak memory 255448 kb
Host smart-1125d61e-604c-45fe-9d05-5c1d3b3e1dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28307
93117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2830793117
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3134437209
Short name T24
Test name
Test status
Simulation time 12112785940 ps
CPU time 39.27 seconds
Started Mar 14 02:10:58 PM PDT 24
Finished Mar 14 02:11:37 PM PDT 24
Peak memory 255972 kb
Host smart-6627feaa-77f6-42e7-ba00-5b870df679e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
37209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3134437209
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2561621344
Short name T25
Test name
Test status
Simulation time 1046886401 ps
CPU time 58.55 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:08:54 PM PDT 24
Peak memory 256112 kb
Host smart-6e0d26c4-08f0-41a6-ac32-ae7e443a5a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25616
21344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2561621344
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3733270306
Short name T755
Test name
Test status
Simulation time 3986602824 ps
CPU time 141.14 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:07:58 PM PDT 24
Peak memory 240140 kb
Host smart-0611ce0f-7d35-4653-ae01-cb9353f63c7d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3733270306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3733270306
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1137101622
Short name T826
Test name
Test status
Simulation time 822749329 ps
CPU time 87.57 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:07:05 PM PDT 24
Peak memory 235484 kb
Host smart-55e0bed7-9893-4d93-8119-bdf967449a17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1137101622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1137101622
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1098063841
Short name T733
Test name
Test status
Simulation time 102669507 ps
CPU time 5.02 seconds
Started Mar 14 02:05:41 PM PDT 24
Finished Mar 14 02:05:46 PM PDT 24
Peak memory 240012 kb
Host smart-cef27797-9b1f-4884-8177-0c8f4ce48a5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1098063841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1098063841
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.19915286
Short name T822
Test name
Test status
Simulation time 103853074 ps
CPU time 4.29 seconds
Started Mar 14 02:05:38 PM PDT 24
Finished Mar 14 02:05:42 PM PDT 24
Peak memory 240112 kb
Host smart-b9001f10-aa12-47e8-adda-dc0007ddb0b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.alert_handler_csr_mem_rw_with_rand_reset.19915286
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.986259486
Short name T723
Test name
Test status
Simulation time 558975471 ps
CPU time 9.97 seconds
Started Mar 14 02:05:38 PM PDT 24
Finished Mar 14 02:05:48 PM PDT 24
Peak memory 239988 kb
Host smart-d6890b7f-a75f-4490-b753-01719d54ad42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=986259486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.986259486
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3554601986
Short name T828
Test name
Test status
Simulation time 177027688 ps
CPU time 12.4 seconds
Started Mar 14 02:05:40 PM PDT 24
Finished Mar 14 02:05:53 PM PDT 24
Peak memory 240028 kb
Host smart-a8fa52f4-d87e-4f17-91b0-e2443345f7f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3554601986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3554601986
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1964156229
Short name T810
Test name
Test status
Simulation time 13370419751 ps
CPU time 332.74 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:11:10 PM PDT 24
Peak memory 266056 kb
Host smart-06cd5543-5f19-4f8e-85a6-d1b32b67373a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1964156229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1964156229
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2961008773
Short name T127
Test name
Test status
Simulation time 4629467545 ps
CPU time 842.44 seconds
Started Mar 14 02:05:38 PM PDT 24
Finished Mar 14 02:19:41 PM PDT 24
Peak memory 273248 kb
Host smart-81f4b95c-81b2-464b-9937-daca30c55526
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961008773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2961008773
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3254045019
Short name T791
Test name
Test status
Simulation time 235652161 ps
CPU time 15.76 seconds
Started Mar 14 02:05:38 PM PDT 24
Finished Mar 14 02:05:53 PM PDT 24
Peak memory 248172 kb
Host smart-59884f3a-fb25-4d22-bec3-bd9e62f25850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3254045019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3254045019
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.265008012
Short name T730
Test name
Test status
Simulation time 21977005211 ps
CPU time 299.57 seconds
Started Mar 14 02:05:51 PM PDT 24
Finished Mar 14 02:10:51 PM PDT 24
Peak memory 240160 kb
Host smart-222b2871-79b0-4eed-bd8f-67dd21a31cbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=265008012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.265008012
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1160263774
Short name T801
Test name
Test status
Simulation time 2961876642 ps
CPU time 228.06 seconds
Started Mar 14 02:05:37 PM PDT 24
Finished Mar 14 02:09:26 PM PDT 24
Peak memory 236452 kb
Host smart-ded0bfeb-27b9-4c56-84d8-7390b643c095
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1160263774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1160263774
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.425080649
Short name T782
Test name
Test status
Simulation time 202679634 ps
CPU time 5.28 seconds
Started Mar 14 02:05:39 PM PDT 24
Finished Mar 14 02:05:44 PM PDT 24
Peak memory 239980 kb
Host smart-c8b55e13-ee04-43a6-89e2-001da9e9762a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=425080649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.425080649
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1489544533
Short name T784
Test name
Test status
Simulation time 98397407 ps
CPU time 5.22 seconds
Started Mar 14 02:05:51 PM PDT 24
Finished Mar 14 02:05:57 PM PDT 24
Peak memory 236408 kb
Host smart-5c3171bb-e1dc-4326-a71e-c266cf58fa2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489544533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1489544533
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1482162219
Short name T758
Test name
Test status
Simulation time 120504886 ps
CPU time 5.46 seconds
Started Mar 14 02:05:41 PM PDT 24
Finished Mar 14 02:05:47 PM PDT 24
Peak memory 236284 kb
Host smart-f885a61b-d3be-48d7-9389-876732c2a944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1482162219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1482162219
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.4166681366
Short name T754
Test name
Test status
Simulation time 700996928 ps
CPU time 23.72 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:06:15 PM PDT 24
Peak memory 244552 kb
Host smart-5845497c-2aed-481e-a1d9-f414ed6f8d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4166681366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.4166681366
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.321806241
Short name T146
Test name
Test status
Simulation time 33206637051 ps
CPU time 600.4 seconds
Started Mar 14 02:05:38 PM PDT 24
Finished Mar 14 02:15:38 PM PDT 24
Peak memory 265008 kb
Host smart-f1e2a181-c744-4c91-bf6f-a91e840f7c2b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321806241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.321806241
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1295186508
Short name T229
Test name
Test status
Simulation time 588891957 ps
CPU time 19.38 seconds
Started Mar 14 02:05:41 PM PDT 24
Finished Mar 14 02:06:01 PM PDT 24
Peak memory 253520 kb
Host smart-fcfca28c-dbc8-4c34-89c0-8dce20035fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1295186508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1295186508
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.502782432
Short name T226
Test name
Test status
Simulation time 277500912 ps
CPU time 5.6 seconds
Started Mar 14 02:06:23 PM PDT 24
Finished Mar 14 02:06:32 PM PDT 24
Peak memory 240068 kb
Host smart-47d2a5ed-e9ac-41bf-802b-a3a6e01af606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502782432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.502782432
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.502598262
Short name T184
Test name
Test status
Simulation time 37195959 ps
CPU time 5.62 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:32 PM PDT 24
Peak memory 236328 kb
Host smart-f38531fc-bcbe-4d61-b59c-d358ce99db02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=502598262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.502598262
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.577702935
Short name T735
Test name
Test status
Simulation time 59357078 ps
CPU time 1.46 seconds
Started Mar 14 02:06:24 PM PDT 24
Finished Mar 14 02:06:28 PM PDT 24
Peak memory 236324 kb
Host smart-9cb36d7c-80a5-48e7-b067-172eed353998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=577702935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.577702935
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2630870751
Short name T820
Test name
Test status
Simulation time 1081894788 ps
CPU time 27.31 seconds
Started Mar 14 02:06:26 PM PDT 24
Finished Mar 14 02:06:54 PM PDT 24
Peak memory 244552 kb
Host smart-9c8efcb2-0982-4213-aa7b-ee0ec732ffb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2630870751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2630870751
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2594755740
Short name T145
Test name
Test status
Simulation time 8406002604 ps
CPU time 158.96 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:09:06 PM PDT 24
Peak memory 264156 kb
Host smart-f89bbdab-2cbd-41b7-b5bb-6c36a39a272f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2594755740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2594755740
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1501394209
Short name T787
Test name
Test status
Simulation time 44554810 ps
CPU time 6.24 seconds
Started Mar 14 02:06:26 PM PDT 24
Finished Mar 14 02:06:33 PM PDT 24
Peak memory 247360 kb
Host smart-acfa4588-3a43-4176-95ec-502da7a1996b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1501394209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1501394209
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2492467862
Short name T149
Test name
Test status
Simulation time 30804296 ps
CPU time 2.99 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:30 PM PDT 24
Peak memory 236356 kb
Host smart-133f9bd6-a4eb-4cb4-85aa-a838f645408d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2492467862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2492467862
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.258459441
Short name T759
Test name
Test status
Simulation time 247166631 ps
CPU time 7.65 seconds
Started Mar 14 02:06:23 PM PDT 24
Finished Mar 14 02:06:34 PM PDT 24
Peak memory 238496 kb
Host smart-a69674fe-a081-4ab5-b107-848428c2375d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258459441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.258459441
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.149328733
Short name T228
Test name
Test status
Simulation time 141507069 ps
CPU time 9.86 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:36 PM PDT 24
Peak memory 236300 kb
Host smart-f6677b4b-55d6-41ca-98b0-19b45c418466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=149328733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.149328733
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3003412396
Short name T765
Test name
Test status
Simulation time 9615616 ps
CPU time 1.57 seconds
Started Mar 14 02:06:26 PM PDT 24
Finished Mar 14 02:06:28 PM PDT 24
Peak memory 236352 kb
Host smart-a0d0c266-7e45-4923-8b1d-38ce101e45d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3003412396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3003412396
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4270833798
Short name T764
Test name
Test status
Simulation time 609026462 ps
CPU time 18.91 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:45 PM PDT 24
Peak memory 240008 kb
Host smart-414d9961-bcb7-4c41-882c-faaa426adc60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270833798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4270833798
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2802154134
Short name T112
Test name
Test status
Simulation time 5653301427 ps
CPU time 425.17 seconds
Started Mar 14 02:06:26 PM PDT 24
Finished Mar 14 02:13:32 PM PDT 24
Peak memory 265136 kb
Host smart-a398e778-fc38-43cd-99d0-4b650afc2f23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2802154134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2802154134
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3907124956
Short name T122
Test name
Test status
Simulation time 13827087586 ps
CPU time 532.21 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:15:19 PM PDT 24
Peak memory 264964 kb
Host smart-6acb48e5-222c-4773-aba4-94f5d69b92b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907124956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3907124956
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1223240705
Short name T717
Test name
Test status
Simulation time 311132473 ps
CPU time 25.67 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 246660 kb
Host smart-6c7d279b-af47-4e4d-ad6d-ccb156c24064
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1223240705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1223240705
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3916052895
Short name T748
Test name
Test status
Simulation time 26513652 ps
CPU time 5.33 seconds
Started Mar 14 02:06:27 PM PDT 24
Finished Mar 14 02:06:32 PM PDT 24
Peak memory 240100 kb
Host smart-96e13bd2-70e2-4d69-8ff6-76c6e4357caf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916052895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3916052895
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.378178785
Short name T796
Test name
Test status
Simulation time 132869506 ps
CPU time 4.98 seconds
Started Mar 14 02:06:24 PM PDT 24
Finished Mar 14 02:06:32 PM PDT 24
Peak memory 239888 kb
Host smart-d97f218e-81ac-4d0b-9823-4759c788367d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=378178785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.378178785
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2281431735
Short name T806
Test name
Test status
Simulation time 11842411 ps
CPU time 1.37 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:28 PM PDT 24
Peak memory 235468 kb
Host smart-be93c532-1231-44a0-97ff-a5970dc42e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2281431735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2281431735
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2357420655
Short name T802
Test name
Test status
Simulation time 344283212 ps
CPU time 15.28 seconds
Started Mar 14 02:06:24 PM PDT 24
Finished Mar 14 02:06:41 PM PDT 24
Peak memory 244520 kb
Host smart-e0c9bfcd-1b6d-4653-8815-d58c3fe2649f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2357420655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2357420655
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4031527580
Short name T140
Test name
Test status
Simulation time 5053105363 ps
CPU time 362.08 seconds
Started Mar 14 02:06:26 PM PDT 24
Finished Mar 14 02:12:29 PM PDT 24
Peak memory 270708 kb
Host smart-9b696add-04c1-4b10-ab53-52bce8a2d071
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4031527580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4031527580
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.537586002
Short name T137
Test name
Test status
Simulation time 13541868055 ps
CPU time 1101.71 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:24:48 PM PDT 24
Peak memory 265112 kb
Host smart-d536e904-73dd-4ae8-9a21-75aec61f834c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537586002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.537586002
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2515166055
Short name T716
Test name
Test status
Simulation time 164210037 ps
CPU time 6.49 seconds
Started Mar 14 02:06:25 PM PDT 24
Finished Mar 14 02:06:33 PM PDT 24
Peak memory 247264 kb
Host smart-a96d30c5-4880-4018-a947-670cc20b1de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2515166055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2515166055
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2210194472
Short name T827
Test name
Test status
Simulation time 64644191 ps
CPU time 8.46 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:06:46 PM PDT 24
Peak memory 251900 kb
Host smart-a849d471-5c97-4923-bc11-e0cf1d80138a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210194472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2210194472
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.104108698
Short name T731
Test name
Test status
Simulation time 120312935 ps
CPU time 9.8 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:06:48 PM PDT 24
Peak memory 239764 kb
Host smart-3319beb8-ed88-4f02-b18c-78c9bdfa37d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=104108698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.104108698
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3356007246
Short name T786
Test name
Test status
Simulation time 8025168 ps
CPU time 1.51 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:06:39 PM PDT 24
Peak memory 235480 kb
Host smart-c7107ccc-2004-47bf-b583-204b452f54e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3356007246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3356007246
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.274232775
Short name T746
Test name
Test status
Simulation time 511216155 ps
CPU time 35.68 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:07:12 PM PDT 24
Peak memory 243692 kb
Host smart-c3a55324-2505-4450-8348-934f192eed39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=274232775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.274232775
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3142380388
Short name T130
Test name
Test status
Simulation time 11862022728 ps
CPU time 201.71 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:10:00 PM PDT 24
Peak memory 266432 kb
Host smart-b91abe97-b2d3-48c7-9750-11a9e3a03cb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3142380388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3142380388
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.248395443
Short name T829
Test name
Test status
Simulation time 337552033 ps
CPU time 27.73 seconds
Started Mar 14 02:06:39 PM PDT 24
Finished Mar 14 02:07:07 PM PDT 24
Peak memory 247284 kb
Host smart-00aaad4a-aaa6-4e6c-bc82-ae72d435ce2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=248395443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.248395443
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1790654181
Short name T762
Test name
Test status
Simulation time 128325357 ps
CPU time 4.47 seconds
Started Mar 14 02:06:40 PM PDT 24
Finished Mar 14 02:06:44 PM PDT 24
Peak memory 240096 kb
Host smart-d6e030ab-c217-4b61-9e1e-2a49a3e57f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790654181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1790654181
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3669011032
Short name T181
Test name
Test status
Simulation time 61545002 ps
CPU time 5.31 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:06:44 PM PDT 24
Peak memory 235460 kb
Host smart-9e31e4de-5a04-4854-81a8-673d2656b811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3669011032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3669011032
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.34858879
Short name T741
Test name
Test status
Simulation time 20231583 ps
CPU time 1.36 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:06:38 PM PDT 24
Peak memory 236348 kb
Host smart-240c938b-2600-4815-8997-a3c9d58d9b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34858879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.34858879
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3970730188
Short name T797
Test name
Test status
Simulation time 444899611 ps
CPU time 15.31 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:06:51 PM PDT 24
Peak memory 244520 kb
Host smart-bdae66cf-ba4c-47c4-bc6a-43de6b9044fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3970730188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3970730188
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2812439722
Short name T141
Test name
Test status
Simulation time 10102615622 ps
CPU time 589.86 seconds
Started Mar 14 02:06:44 PM PDT 24
Finished Mar 14 02:16:34 PM PDT 24
Peak memory 269272 kb
Host smart-fa595f62-0b3c-47cb-bdbd-b4331ae51425
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812439722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2812439722
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1459798313
Short name T767
Test name
Test status
Simulation time 300681390 ps
CPU time 11.17 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:06:48 PM PDT 24
Peak memory 248084 kb
Host smart-3730c152-d5b0-4e0e-8c88-9dfbbabc4111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1459798313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1459798313
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1736996378
Short name T726
Test name
Test status
Simulation time 149515001 ps
CPU time 13.48 seconds
Started Mar 14 02:06:39 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 250340 kb
Host smart-87dae447-69f9-48a8-8691-38aacc2e15bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736996378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1736996378
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2058024845
Short name T739
Test name
Test status
Simulation time 236225551 ps
CPU time 5.73 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:06:41 PM PDT 24
Peak memory 236352 kb
Host smart-b698e654-11f8-4c62-aa32-7e0db6ecc840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2058024845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2058024845
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3935824289
Short name T721
Test name
Test status
Simulation time 25629983 ps
CPU time 1.41 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:06:39 PM PDT 24
Peak memory 236384 kb
Host smart-697d4c2b-b5b3-4491-af29-9c4f436517b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3935824289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3935824289
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2118505324
Short name T178
Test name
Test status
Simulation time 359128284 ps
CPU time 14.1 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 248216 kb
Host smart-6b523b24-2d5b-4ef2-960d-b2d43f3969a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2118505324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2118505324
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2497688181
Short name T131
Test name
Test status
Simulation time 2230656375 ps
CPU time 310.19 seconds
Started Mar 14 02:06:44 PM PDT 24
Finished Mar 14 02:11:54 PM PDT 24
Peak memory 265152 kb
Host smart-bef3d61c-a137-43c1-86d7-63bf6cfa61fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497688181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2497688181
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2604783075
Short name T725
Test name
Test status
Simulation time 303062427 ps
CPU time 10.24 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:06:48 PM PDT 24
Peak memory 248244 kb
Host smart-2035b3d2-2d51-4f48-9b8c-10fa194baa05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604783075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2604783075
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4281406338
Short name T788
Test name
Test status
Simulation time 122030706 ps
CPU time 5.07 seconds
Started Mar 14 02:06:36 PM PDT 24
Finished Mar 14 02:06:41 PM PDT 24
Peak memory 240092 kb
Host smart-506e1b6b-aae2-4e86-8514-b8fa42cb6b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281406338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4281406338
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2785941962
Short name T776
Test name
Test status
Simulation time 206994131 ps
CPU time 7.95 seconds
Started Mar 14 02:06:39 PM PDT 24
Finished Mar 14 02:06:47 PM PDT 24
Peak memory 235476 kb
Host smart-f92a2fdb-4de9-4f0f-ba4b-98332561fd1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2785941962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2785941962
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2770377994
Short name T337
Test name
Test status
Simulation time 28135137 ps
CPU time 1.43 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:06:39 PM PDT 24
Peak memory 236352 kb
Host smart-b46e7334-71e3-40b4-b372-fc21d04bde52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2770377994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2770377994
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3973139898
Short name T749
Test name
Test status
Simulation time 1462945803 ps
CPU time 28.56 seconds
Started Mar 14 02:06:38 PM PDT 24
Finished Mar 14 02:07:07 PM PDT 24
Peak memory 248236 kb
Host smart-5a88d16b-8634-4541-84b7-2ae80635140f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3973139898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3973139898
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1788937272
Short name T792
Test name
Test status
Simulation time 930652397 ps
CPU time 12.14 seconds
Started Mar 14 02:06:37 PM PDT 24
Finished Mar 14 02:06:49 PM PDT 24
Peak memory 248260 kb
Host smart-ce68b7e8-d23f-4f03-9658-662ccd94a9be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1788937272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1788937272
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1481159400
Short name T819
Test name
Test status
Simulation time 1580582492 ps
CPU time 14.66 seconds
Started Mar 14 02:06:51 PM PDT 24
Finished Mar 14 02:07:06 PM PDT 24
Peak memory 248332 kb
Host smart-c5074145-5421-4bd6-8e8f-2209dd299b9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481159400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1481159400
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3198459800
Short name T766
Test name
Test status
Simulation time 1189544524 ps
CPU time 8.55 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:06:57 PM PDT 24
Peak memory 235312 kb
Host smart-a3ef5f44-15ce-4150-8873-565f84823b87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3198459800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3198459800
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.692970493
Short name T760
Test name
Test status
Simulation time 6682616 ps
CPU time 1.45 seconds
Started Mar 14 02:06:47 PM PDT 24
Finished Mar 14 02:06:49 PM PDT 24
Peak memory 236256 kb
Host smart-f9dfc28e-a2d8-459f-bbf7-15ef6c688317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=692970493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.692970493
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.446876238
Short name T736
Test name
Test status
Simulation time 175408102 ps
CPU time 29.89 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:07:20 PM PDT 24
Peak memory 240024 kb
Host smart-5dd53926-f619-4fd5-a0ed-f0749fa34827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=446876238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.446876238
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.47562212
Short name T121
Test name
Test status
Simulation time 3831066141 ps
CPU time 288.72 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:11:39 PM PDT 24
Peak memory 265064 kb
Host smart-6d5290b5-bd05-47ab-8fbb-5085ad2d3bf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=47562212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.47562212
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3555918752
Short name T119
Test name
Test status
Simulation time 47919964697 ps
CPU time 1086.49 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:24:55 PM PDT 24
Peak memory 265020 kb
Host smart-7bea0a85-31c3-4b68-a682-4c81c073ee43
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555918752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3555918752
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.24434038
Short name T830
Test name
Test status
Simulation time 130648327 ps
CPU time 4.45 seconds
Started Mar 14 02:06:55 PM PDT 24
Finished Mar 14 02:06:59 PM PDT 24
Peak memory 248004 kb
Host smart-4f6537a3-8cca-4b56-9844-fb6bc3a0503f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=24434038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.24434038
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3119201464
Short name T734
Test name
Test status
Simulation time 164918489 ps
CPU time 12.46 seconds
Started Mar 14 02:06:51 PM PDT 24
Finished Mar 14 02:07:03 PM PDT 24
Peak memory 250448 kb
Host smart-56c6bcdd-ece4-4ec6-91b6-50b30cadaf75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119201464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3119201464
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3776361378
Short name T815
Test name
Test status
Simulation time 23878250 ps
CPU time 3.72 seconds
Started Mar 14 02:06:48 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 236328 kb
Host smart-64b279ba-9f22-4a13-b867-bbb2b5f1e880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3776361378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3776361378
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2169858169
Short name T771
Test name
Test status
Simulation time 21487880 ps
CPU time 1.36 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 236344 kb
Host smart-6f8e8384-9b13-4df9-bcb4-10e388f23c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2169858169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2169858169
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1964620765
Short name T179
Test name
Test status
Simulation time 514057263 ps
CPU time 11.9 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 243676 kb
Host smart-be93f26f-07d9-4c26-a3c6-1db2721cb19c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1964620765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1964620765
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3085242250
Short name T133
Test name
Test status
Simulation time 6073905107 ps
CPU time 495.19 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:15:04 PM PDT 24
Peak memory 265040 kb
Host smart-3e62f360-1f26-459f-9419-969479eb78bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085242250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3085242250
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2993736082
Short name T831
Test name
Test status
Simulation time 661249407 ps
CPU time 9.03 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:06:59 PM PDT 24
Peak memory 247556 kb
Host smart-9557ed69-9cd4-475f-8f8c-df5894e1ab15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2993736082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2993736082
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4263750855
Short name T238
Test name
Test status
Simulation time 174812254 ps
CPU time 22.31 seconds
Started Mar 14 02:06:52 PM PDT 24
Finished Mar 14 02:07:14 PM PDT 24
Peak memory 236528 kb
Host smart-6ff9efd3-639e-4ca6-8412-65c021529d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4263750855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4263750855
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1266506903
Short name T774
Test name
Test status
Simulation time 243190658 ps
CPU time 9.92 seconds
Started Mar 14 02:06:48 PM PDT 24
Finished Mar 14 02:06:58 PM PDT 24
Peak memory 238192 kb
Host smart-5350f405-31e3-4bb8-bf76-c9d036658a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266506903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1266506903
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3086511468
Short name T737
Test name
Test status
Simulation time 62541716 ps
CPU time 6.23 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:06:56 PM PDT 24
Peak memory 236288 kb
Host smart-7f195f25-7fe7-4c14-9e4d-34cc2e47509a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3086511468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3086511468
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3100471899
Short name T780
Test name
Test status
Simulation time 8612496 ps
CPU time 1.31 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 236368 kb
Host smart-6e181978-559f-4560-878d-d525e7994f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3100471899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3100471899
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2398040848
Short name T777
Test name
Test status
Simulation time 514995667 ps
CPU time 39.38 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:07:28 PM PDT 24
Peak memory 248236 kb
Host smart-66e54c56-3dec-4bf0-b484-5740ef7a6c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2398040848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2398040848
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3606574673
Short name T128
Test name
Test status
Simulation time 16351949455 ps
CPU time 316.19 seconds
Started Mar 14 02:06:50 PM PDT 24
Finished Mar 14 02:12:06 PM PDT 24
Peak memory 273048 kb
Host smart-b3b82218-2734-47c4-96ab-b75ca59cdca2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3606574673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3606574673
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2862482352
Short name T728
Test name
Test status
Simulation time 209774730 ps
CPU time 7.52 seconds
Started Mar 14 02:06:51 PM PDT 24
Finished Mar 14 02:06:58 PM PDT 24
Peak memory 248088 kb
Host smart-202796e3-5a5c-4c32-9398-1802bf7a9fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2862482352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2862482352
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3811398755
Short name T180
Test name
Test status
Simulation time 18351039975 ps
CPU time 332.61 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:11:22 PM PDT 24
Peak memory 240164 kb
Host smart-69442745-c806-464e-9e8e-0eee54b5c0d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3811398755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3811398755
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2817163290
Short name T729
Test name
Test status
Simulation time 85589095911 ps
CPU time 270.55 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:10:20 PM PDT 24
Peak memory 236296 kb
Host smart-ab8624b5-93e6-4239-be8d-e1cd005c6fef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2817163290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2817163290
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.714036255
Short name T151
Test name
Test status
Simulation time 169615172 ps
CPU time 5.9 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:05:57 PM PDT 24
Peak memory 240048 kb
Host smart-7022c093-8e57-4000-9aa5-3f5bb6298ab1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=714036255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.714036255
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2881247845
Short name T772
Test name
Test status
Simulation time 172278123 ps
CPU time 13.89 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:06:05 PM PDT 24
Peak memory 250460 kb
Host smart-bc97583b-63dd-4377-a139-532e9a9632cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881247845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2881247845
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3789568841
Short name T722
Test name
Test status
Simulation time 92918815 ps
CPU time 4.22 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:05:56 PM PDT 24
Peak memory 235460 kb
Host smart-06b5fbf4-fc08-486f-9ef9-f379c6c3f763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3789568841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3789568841
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1561979446
Short name T761
Test name
Test status
Simulation time 11000727 ps
CPU time 1.61 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:05:53 PM PDT 24
Peak memory 236320 kb
Host smart-e6de2fd6-7bc7-4686-98f2-476fd37d6c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561979446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1561979446
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4238591131
Short name T805
Test name
Test status
Simulation time 1049018248 ps
CPU time 37.86 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:06:28 PM PDT 24
Peak memory 248188 kb
Host smart-4b968518-b1f3-42dd-90f4-3294150918d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4238591131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.4238591131
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1162711241
Short name T808
Test name
Test status
Simulation time 1837781306 ps
CPU time 140.2 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:08:12 PM PDT 24
Peak memory 256712 kb
Host smart-f883693e-13c0-48af-aa60-3ddec05c371c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1162711241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1162711241
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2881395240
Short name T120
Test name
Test status
Simulation time 8567393313 ps
CPU time 648.2 seconds
Started Mar 14 02:05:56 PM PDT 24
Finished Mar 14 02:16:44 PM PDT 24
Peak memory 265040 kb
Host smart-8587e2c5-a7e8-4781-884e-d138e46e4be8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881395240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2881395240
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.834055430
Short name T718
Test name
Test status
Simulation time 144285154 ps
CPU time 10.24 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:06:02 PM PDT 24
Peak memory 248256 kb
Host smart-59993f36-c520-4fe9-947c-bae217f2066a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=834055430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.834055430
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.426507716
Short name T770
Test name
Test status
Simulation time 8258253 ps
CPU time 1.53 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 236328 kb
Host smart-fbd1afc8-4f28-48cf-b43e-c42365b8b0b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=426507716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.426507716
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.395419317
Short name T343
Test name
Test status
Simulation time 7470315 ps
CPU time 1.43 seconds
Started Mar 14 02:06:52 PM PDT 24
Finished Mar 14 02:06:53 PM PDT 24
Peak memory 236384 kb
Host smart-c2e0ad94-914d-46b5-9235-dc43b1efcf20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=395419317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.395419317
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3534576129
Short name T756
Test name
Test status
Simulation time 8205810 ps
CPU time 1.35 seconds
Started Mar 14 02:06:52 PM PDT 24
Finished Mar 14 02:06:53 PM PDT 24
Peak memory 236384 kb
Host smart-cc5a80e3-6815-42c0-8252-814ed4d23cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3534576129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3534576129
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2562777411
Short name T768
Test name
Test status
Simulation time 8482317 ps
CPU time 1.45 seconds
Started Mar 14 02:06:49 PM PDT 24
Finished Mar 14 02:06:52 PM PDT 24
Peak memory 234768 kb
Host smart-de6437d7-f546-49d0-b908-23b8b7919eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562777411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2562777411
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3109614277
Short name T757
Test name
Test status
Simulation time 11782453 ps
CPU time 1.28 seconds
Started Mar 14 02:06:51 PM PDT 24
Finished Mar 14 02:06:53 PM PDT 24
Peak memory 236380 kb
Host smart-70e02cdd-c76e-404c-a2e0-9af98bbcd18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3109614277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3109614277
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3676764681
Short name T773
Test name
Test status
Simulation time 6780459 ps
CPU time 1.53 seconds
Started Mar 14 02:07:01 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 236332 kb
Host smart-f6d08955-b8d4-4eab-b4c2-898faabcf0a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3676764681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3676764681
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1033579064
Short name T338
Test name
Test status
Simulation time 11598942 ps
CPU time 1.71 seconds
Started Mar 14 02:06:59 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 236356 kb
Host smart-133495f0-7a2f-4312-9968-44de4c416a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1033579064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1033579064
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3285541965
Short name T803
Test name
Test status
Simulation time 15183981 ps
CPU time 1.38 seconds
Started Mar 14 02:06:59 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 235496 kb
Host smart-8fe4629a-16c3-4bb8-aecf-81e4db7ce369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3285541965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3285541965
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1034983606
Short name T750
Test name
Test status
Simulation time 25794157 ps
CPU time 1.51 seconds
Started Mar 14 02:06:59 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 235412 kb
Host smart-f34caf1e-3fae-463f-a497-c86fb825c706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1034983606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1034983606
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2463031336
Short name T342
Test name
Test status
Simulation time 28276197 ps
CPU time 1.55 seconds
Started Mar 14 02:07:03 PM PDT 24
Finished Mar 14 02:07:04 PM PDT 24
Peak memory 236368 kb
Host smart-d41e2099-20be-4be6-8634-99c867fdc26a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2463031336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2463031336
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.584823359
Short name T183
Test name
Test status
Simulation time 2169186895 ps
CPU time 68.25 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:07:12 PM PDT 24
Peak memory 240040 kb
Host smart-2272dc38-bdeb-4532-81d6-95736fceac60
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=584823359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.584823359
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2182634751
Short name T230
Test name
Test status
Simulation time 4265431615 ps
CPU time 288.09 seconds
Started Mar 14 02:05:51 PM PDT 24
Finished Mar 14 02:10:40 PM PDT 24
Peak memory 240160 kb
Host smart-367b1501-aa23-41b2-ba68-1b1348c2d55c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2182634751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2182634751
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3066245089
Short name T795
Test name
Test status
Simulation time 476368247 ps
CPU time 8.96 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:06:00 PM PDT 24
Peak memory 240028 kb
Host smart-7d284a3e-0740-485a-90a5-83f4191bebdf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3066245089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3066245089
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2552160517
Short name T185
Test name
Test status
Simulation time 195786161 ps
CPU time 8.58 seconds
Started Mar 14 02:06:02 PM PDT 24
Finished Mar 14 02:06:11 PM PDT 24
Peak memory 248288 kb
Host smart-7ec588c7-37f9-451b-b1ea-a9993d157b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552160517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2552160517
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2248922227
Short name T818
Test name
Test status
Simulation time 227843431 ps
CPU time 5.47 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:05:57 PM PDT 24
Peak memory 238256 kb
Host smart-a0b5fc71-80ea-44fb-b2b8-e911f94f71ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2248922227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2248922227
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.131533499
Short name T783
Test name
Test status
Simulation time 11759232 ps
CPU time 1.31 seconds
Started Mar 14 02:05:50 PM PDT 24
Finished Mar 14 02:05:53 PM PDT 24
Peak memory 236376 kb
Host smart-b3d647fe-da28-4a3b-853c-9ce9520875e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=131533499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.131533499
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3753771941
Short name T743
Test name
Test status
Simulation time 697957047 ps
CPU time 26.31 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:06:30 PM PDT 24
Peak memory 244532 kb
Host smart-4e58f6e5-3c68-4ac0-8d5f-cf9738a2a633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3753771941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3753771941
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2667495100
Short name T136
Test name
Test status
Simulation time 37781520166 ps
CPU time 173.71 seconds
Started Mar 14 02:05:56 PM PDT 24
Finished Mar 14 02:08:50 PM PDT 24
Peak memory 265044 kb
Host smart-468eb1fc-d74b-4217-a690-6e96fb165a80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2667495100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2667495100
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3067961353
Short name T139
Test name
Test status
Simulation time 9089063529 ps
CPU time 754.83 seconds
Started Mar 14 02:05:56 PM PDT 24
Finished Mar 14 02:18:31 PM PDT 24
Peak memory 265048 kb
Host smart-6a16d7d7-271f-44d4-bc91-6c6723f13c5e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067961353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3067961353
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1267126483
Short name T799
Test name
Test status
Simulation time 1099481289 ps
CPU time 13.35 seconds
Started Mar 14 02:05:49 PM PDT 24
Finished Mar 14 02:06:03 PM PDT 24
Peak memory 248292 kb
Host smart-14806fd7-d556-4aca-ab48-da4dd15e6b23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1267126483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1267126483
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.890352493
Short name T727
Test name
Test status
Simulation time 24644622 ps
CPU time 1.48 seconds
Started Mar 14 02:06:59 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 235448 kb
Host smart-c1a1d953-3d5f-4658-98f9-6e7cb083b190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=890352493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.890352493
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.162950590
Short name T751
Test name
Test status
Simulation time 17118980 ps
CPU time 1.32 seconds
Started Mar 14 02:07:04 PM PDT 24
Finished Mar 14 02:07:05 PM PDT 24
Peak memory 236348 kb
Host smart-c166f984-f3e8-455f-951e-6e3c1d54fcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=162950590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.162950590
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3468910428
Short name T336
Test name
Test status
Simulation time 16433522 ps
CPU time 1.44 seconds
Started Mar 14 02:06:58 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 236348 kb
Host smart-f24ecaf7-1868-4f43-865c-0af0d91e4983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3468910428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3468910428
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4093245218
Short name T789
Test name
Test status
Simulation time 9936468 ps
CPU time 1.53 seconds
Started Mar 14 02:07:03 PM PDT 24
Finished Mar 14 02:07:05 PM PDT 24
Peak memory 235464 kb
Host smart-925ab86d-2073-4da3-8571-a74a49dc6371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093245218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4093245218
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.805327006
Short name T814
Test name
Test status
Simulation time 16538967 ps
CPU time 1.55 seconds
Started Mar 14 02:06:58 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 236600 kb
Host smart-9edd403d-3c3d-4fb3-b564-a60f57ddf045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=805327006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.805327006
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3326846230
Short name T341
Test name
Test status
Simulation time 28408970 ps
CPU time 1.3 seconds
Started Mar 14 02:07:05 PM PDT 24
Finished Mar 14 02:07:06 PM PDT 24
Peak memory 234420 kb
Host smart-3af9b719-df7d-42ff-9511-3721e04cbcc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3326846230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3326846230
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.955343758
Short name T817
Test name
Test status
Simulation time 13092921 ps
CPU time 1.3 seconds
Started Mar 14 02:07:03 PM PDT 24
Finished Mar 14 02:07:04 PM PDT 24
Peak memory 236352 kb
Host smart-3f1ad0be-782c-4541-8089-67f4032ef19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=955343758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.955343758
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3476885716
Short name T824
Test name
Test status
Simulation time 12616424 ps
CPU time 1.45 seconds
Started Mar 14 02:06:59 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 235448 kb
Host smart-90194989-351b-400a-8909-7a0b8f419747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3476885716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3476885716
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3895333292
Short name T744
Test name
Test status
Simulation time 22084613 ps
CPU time 1.44 seconds
Started Mar 14 02:07:00 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 236344 kb
Host smart-e1d22ad7-cb0b-4156-885d-ff157a564b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3895333292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3895333292
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1525138145
Short name T785
Test name
Test status
Simulation time 4516552492 ps
CPU time 293.14 seconds
Started Mar 14 02:06:01 PM PDT 24
Finished Mar 14 02:10:54 PM PDT 24
Peak memory 240164 kb
Host smart-d662ac0e-91ea-45bb-a7cd-5763527ed705
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1525138145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1525138145
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2983051322
Short name T781
Test name
Test status
Simulation time 863662231 ps
CPU time 116.15 seconds
Started Mar 14 02:06:06 PM PDT 24
Finished Mar 14 02:08:03 PM PDT 24
Peak memory 234676 kb
Host smart-acc5922d-facd-494a-92ca-1ad64f5ce5d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2983051322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2983051322
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1052240141
Short name T732
Test name
Test status
Simulation time 25722590 ps
CPU time 3.83 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:06:07 PM PDT 24
Peak memory 239984 kb
Host smart-0beb6a37-d236-4657-bcb4-712589308523
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1052240141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1052240141
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3772070123
Short name T800
Test name
Test status
Simulation time 88552864 ps
CPU time 6.92 seconds
Started Mar 14 02:06:02 PM PDT 24
Finished Mar 14 02:06:10 PM PDT 24
Peak memory 239308 kb
Host smart-80a7733f-a8d2-46b8-9b20-f99b5facdc4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772070123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3772070123
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2800822879
Short name T168
Test name
Test status
Simulation time 192110901 ps
CPU time 4.86 seconds
Started Mar 14 02:06:00 PM PDT 24
Finished Mar 14 02:06:05 PM PDT 24
Peak memory 236236 kb
Host smart-83ef79bc-3916-445a-965a-a0a4d3e7aba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2800822879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2800822879
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2345463415
Short name T809
Test name
Test status
Simulation time 9797280 ps
CPU time 1.27 seconds
Started Mar 14 02:06:01 PM PDT 24
Finished Mar 14 02:06:03 PM PDT 24
Peak memory 235456 kb
Host smart-f771d2a1-567b-48e5-9b62-acbac484c9f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2345463415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2345463415
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.4152339194
Short name T182
Test name
Test status
Simulation time 2036975869 ps
CPU time 38.4 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:06:42 PM PDT 24
Peak memory 244544 kb
Host smart-9f819850-7377-4b8b-bdaf-87c83bcdb9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4152339194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.4152339194
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1951556075
Short name T125
Test name
Test status
Simulation time 16312595876 ps
CPU time 1149.6 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:25:13 PM PDT 24
Peak memory 265048 kb
Host smart-bf750f72-1fe1-4feb-a8d5-557827b2c2a1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951556075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1951556075
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2538221767
Short name T715
Test name
Test status
Simulation time 260975088 ps
CPU time 13.66 seconds
Started Mar 14 02:06:00 PM PDT 24
Finished Mar 14 02:06:14 PM PDT 24
Peak memory 247832 kb
Host smart-b3c45049-81c2-4f41-b493-961b917b173a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2538221767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2538221767
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3845292538
Short name T794
Test name
Test status
Simulation time 7827999 ps
CPU time 1.35 seconds
Started Mar 14 02:07:00 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 235496 kb
Host smart-4a715d61-950e-46f0-a3e2-831a70bb0d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845292538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3845292538
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1444296089
Short name T747
Test name
Test status
Simulation time 6862902 ps
CPU time 1.43 seconds
Started Mar 14 02:07:00 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 235488 kb
Host smart-87f7e4f9-ea3a-4591-a8e4-ed7af2d17ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1444296089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1444296089
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2377754326
Short name T219
Test name
Test status
Simulation time 6268090 ps
CPU time 1.47 seconds
Started Mar 14 02:07:03 PM PDT 24
Finished Mar 14 02:07:04 PM PDT 24
Peak memory 235496 kb
Host smart-0f26e2b4-d901-45eb-9827-8bc3d7387e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2377754326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2377754326
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.594059760
Short name T816
Test name
Test status
Simulation time 41134379 ps
CPU time 1.3 seconds
Started Mar 14 02:07:05 PM PDT 24
Finished Mar 14 02:07:06 PM PDT 24
Peak memory 235304 kb
Host smart-b299de4e-d5d3-40ad-a0a7-e249cc85d2fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=594059760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.594059760
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2177227221
Short name T813
Test name
Test status
Simulation time 19974470 ps
CPU time 1.37 seconds
Started Mar 14 02:06:58 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 235492 kb
Host smart-d24e45ec-d9aa-4123-aaf1-35b7b81e1fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2177227221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2177227221
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1270935061
Short name T152
Test name
Test status
Simulation time 15070995 ps
CPU time 1.36 seconds
Started Mar 14 02:07:00 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 236368 kb
Host smart-e2d2986f-6d58-4271-be19-14264238791a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1270935061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1270935061
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.838577233
Short name T340
Test name
Test status
Simulation time 11856748 ps
CPU time 1.68 seconds
Started Mar 14 02:07:01 PM PDT 24
Finished Mar 14 02:07:03 PM PDT 24
Peak memory 234484 kb
Host smart-16a36f11-1b8f-4f44-9452-f1be482d9e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=838577233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.838577233
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3930476343
Short name T753
Test name
Test status
Simulation time 17079474 ps
CPU time 1.31 seconds
Started Mar 14 02:07:00 PM PDT 24
Finished Mar 14 02:07:02 PM PDT 24
Peak memory 235464 kb
Host smart-e57644cf-bcf3-4d81-b45b-3a73a73c0380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3930476343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3930476343
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.410088792
Short name T339
Test name
Test status
Simulation time 10721296 ps
CPU time 1.66 seconds
Started Mar 14 02:06:59 PM PDT 24
Finished Mar 14 02:07:01 PM PDT 24
Peak memory 235504 kb
Host smart-d5e7d6b2-f1e9-4d00-ac95-d321eb9d85f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410088792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.410088792
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3558395821
Short name T790
Test name
Test status
Simulation time 11959157 ps
CPU time 1.25 seconds
Started Mar 14 02:07:04 PM PDT 24
Finished Mar 14 02:07:05 PM PDT 24
Peak memory 235460 kb
Host smart-961d7e22-d30c-44a2-afc5-e9f046f36249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3558395821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3558395821
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2499527308
Short name T347
Test name
Test status
Simulation time 37052485 ps
CPU time 5.71 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:06:10 PM PDT 24
Peak memory 255448 kb
Host smart-cad4806c-9c8c-461c-a95f-db640aa15148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499527308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2499527308
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1118067819
Short name T807
Test name
Test status
Simulation time 51020202 ps
CPU time 4.86 seconds
Started Mar 14 02:06:04 PM PDT 24
Finished Mar 14 02:06:11 PM PDT 24
Peak memory 238324 kb
Host smart-d936f232-37f7-4f42-9bb7-cf6a19b49db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1118067819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1118067819
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2212566567
Short name T804
Test name
Test status
Simulation time 10452631 ps
CPU time 1.8 seconds
Started Mar 14 02:06:01 PM PDT 24
Finished Mar 14 02:06:04 PM PDT 24
Peak memory 235448 kb
Host smart-f8e31dc0-d9ff-48aa-be03-1b9a413c3235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2212566567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2212566567
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.901846221
Short name T724
Test name
Test status
Simulation time 2800245813 ps
CPU time 55.26 seconds
Started Mar 14 02:06:02 PM PDT 24
Finished Mar 14 02:06:57 PM PDT 24
Peak memory 240056 kb
Host smart-930a6538-bb93-4daf-be96-4b93e15b96ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=901846221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.901846221
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.423192329
Short name T111
Test name
Test status
Simulation time 7468580681 ps
CPU time 165.87 seconds
Started Mar 14 02:06:03 PM PDT 24
Finished Mar 14 02:08:49 PM PDT 24
Peak memory 264424 kb
Host smart-3bc81a62-0f92-49a5-b1a3-d5095599f1b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=423192329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.423192329
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3034088731
Short name T117
Test name
Test status
Simulation time 45831067477 ps
CPU time 884.94 seconds
Started Mar 14 02:06:02 PM PDT 24
Finished Mar 14 02:20:47 PM PDT 24
Peak memory 271672 kb
Host smart-45c68a11-8ab8-4695-935d-ba5ed483499b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034088731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3034088731
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2956762904
Short name T778
Test name
Test status
Simulation time 1531212452 ps
CPU time 30.77 seconds
Started Mar 14 02:06:04 PM PDT 24
Finished Mar 14 02:06:35 PM PDT 24
Peak memory 248352 kb
Host smart-06588183-bffb-45fd-9d33-cc5d67e0f7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2956762904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2956762904
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1079101593
Short name T719
Test name
Test status
Simulation time 309725480 ps
CPU time 6.56 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:06:18 PM PDT 24
Peak memory 241496 kb
Host smart-5e192285-1ed5-4daf-9603-130545182f9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079101593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1079101593
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1613786433
Short name T812
Test name
Test status
Simulation time 226787338 ps
CPU time 8.92 seconds
Started Mar 14 02:06:17 PM PDT 24
Finished Mar 14 02:06:26 PM PDT 24
Peak memory 236340 kb
Host smart-58ff39d0-f0e8-4617-a266-3fd54127b8ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1613786433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1613786433
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1255669768
Short name T752
Test name
Test status
Simulation time 7867114 ps
CPU time 1.49 seconds
Started Mar 14 02:06:14 PM PDT 24
Finished Mar 14 02:06:16 PM PDT 24
Peak memory 235496 kb
Host smart-147974c0-63e0-41c8-a3eb-4f7943a28609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1255669768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1255669768
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1348855561
Short name T720
Test name
Test status
Simulation time 536153251 ps
CPU time 40.86 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:06:53 PM PDT 24
Peak memory 243624 kb
Host smart-7bdf82bd-dd0b-4d7c-834d-b36a6bb957f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1348855561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1348855561
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3980989130
Short name T775
Test name
Test status
Simulation time 74701198095 ps
CPU time 615.51 seconds
Started Mar 14 02:06:01 PM PDT 24
Finished Mar 14 02:16:17 PM PDT 24
Peak memory 265036 kb
Host smart-2304c784-5779-4ef3-874c-de2fc172e057
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980989130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3980989130
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3995603272
Short name T821
Test name
Test status
Simulation time 474246857 ps
CPU time 19.05 seconds
Started Mar 14 02:06:06 PM PDT 24
Finished Mar 14 02:06:26 PM PDT 24
Peak memory 252300 kb
Host smart-06c80a75-e761-4b4e-bc04-5110aeba211b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3995603272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3995603272
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1147798305
Short name T169
Test name
Test status
Simulation time 37469469 ps
CPU time 6.3 seconds
Started Mar 14 02:06:22 PM PDT 24
Finished Mar 14 02:06:30 PM PDT 24
Peak memory 255584 kb
Host smart-001fb822-4f80-4bee-8229-10f53f78ff80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147798305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1147798305
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2396174127
Short name T738
Test name
Test status
Simulation time 130879863 ps
CPU time 9.72 seconds
Started Mar 14 02:06:14 PM PDT 24
Finished Mar 14 02:06:24 PM PDT 24
Peak memory 236332 kb
Host smart-7f4b29ad-f16a-4b64-97da-42d6b0922199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2396174127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2396174127
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4264168991
Short name T793
Test name
Test status
Simulation time 6263729 ps
CPU time 1.43 seconds
Started Mar 14 02:06:13 PM PDT 24
Finished Mar 14 02:06:15 PM PDT 24
Peak memory 234448 kb
Host smart-beb7768a-beca-4ec6-a421-0b9618268e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4264168991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4264168991
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1893613450
Short name T798
Test name
Test status
Simulation time 652314662 ps
CPU time 21.98 seconds
Started Mar 14 02:06:13 PM PDT 24
Finished Mar 14 02:06:35 PM PDT 24
Peak memory 248252 kb
Host smart-c3730c8c-565b-4f45-b37e-0b5cc1ff4aeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1893613450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1893613450
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.47870462
Short name T825
Test name
Test status
Simulation time 760838137 ps
CPU time 28.88 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:06:41 PM PDT 24
Peak memory 248336 kb
Host smart-1dadd088-c88c-4c19-88ae-ea508e68b19c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=47870462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.47870462
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1496579444
Short name T823
Test name
Test status
Simulation time 25001433 ps
CPU time 3.55 seconds
Started Mar 14 02:06:15 PM PDT 24
Finished Mar 14 02:06:19 PM PDT 24
Peak memory 236540 kb
Host smart-7cfd43cc-0ca6-4427-8ac9-34dc440279d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496579444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1496579444
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.456538264
Short name T177
Test name
Test status
Simulation time 66512146 ps
CPU time 3.54 seconds
Started Mar 14 02:06:14 PM PDT 24
Finished Mar 14 02:06:18 PM PDT 24
Peak memory 236344 kb
Host smart-c8d16124-9f98-4919-98f2-50e931808ce4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=456538264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.456538264
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2490095298
Short name T344
Test name
Test status
Simulation time 7904082 ps
CPU time 1.44 seconds
Started Mar 14 02:06:14 PM PDT 24
Finished Mar 14 02:06:15 PM PDT 24
Peak memory 234468 kb
Host smart-9baecd0a-97ff-44fa-8bba-deb6fec194c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2490095298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2490095298
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.377192400
Short name T811
Test name
Test status
Simulation time 335133771 ps
CPU time 18.56 seconds
Started Mar 14 02:06:14 PM PDT 24
Finished Mar 14 02:06:33 PM PDT 24
Peak memory 248228 kb
Host smart-7cf3f34d-7947-4271-85e7-03106c8a8b9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=377192400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.377192400
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.563379400
Short name T142
Test name
Test status
Simulation time 3107064013 ps
CPU time 220.21 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:09:53 PM PDT 24
Peak memory 265048 kb
Host smart-a4c2fa6d-9ef9-4c57-80d5-f5d59dc2556a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=563379400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.563379400
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.844881961
Short name T227
Test name
Test status
Simulation time 878829435 ps
CPU time 15.09 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:06:27 PM PDT 24
Peak memory 247764 kb
Host smart-8655d778-d194-4323-b53a-1e62eef0b828
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844881961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.844881961
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1406396083
Short name T348
Test name
Test status
Simulation time 266019926 ps
CPU time 9.78 seconds
Started Mar 14 02:06:24 PM PDT 24
Finished Mar 14 02:06:36 PM PDT 24
Peak memory 256132 kb
Host smart-afc20b14-35d9-4e7b-8bea-7c0ace43d784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406396083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1406396083
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3806592124
Short name T742
Test name
Test status
Simulation time 314693918 ps
CPU time 6.11 seconds
Started Mar 14 02:06:22 PM PDT 24
Finished Mar 14 02:06:30 PM PDT 24
Peak memory 238340 kb
Host smart-318d57e5-d1fd-4c76-91e9-16282ffbdbfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3806592124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3806592124
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2864881093
Short name T763
Test name
Test status
Simulation time 11886005 ps
CPU time 1.4 seconds
Started Mar 14 02:06:17 PM PDT 24
Finished Mar 14 02:06:19 PM PDT 24
Peak memory 236360 kb
Host smart-28c6f68c-b926-4a75-a091-5b36113010d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2864881093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2864881093
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4031231792
Short name T745
Test name
Test status
Simulation time 1470982071 ps
CPU time 25.2 seconds
Started Mar 14 02:06:13 PM PDT 24
Finished Mar 14 02:06:39 PM PDT 24
Peak memory 240020 kb
Host smart-55b2709a-06f5-479e-865a-ccd61643932c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4031231792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4031231792
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3725643560
Short name T779
Test name
Test status
Simulation time 368863015 ps
CPU time 22.15 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:06:34 PM PDT 24
Peak memory 248592 kb
Host smart-2e8cf9ce-19d3-41e3-abb8-bb4c0c543311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3725643560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3725643560
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1556987690
Short name T769
Test name
Test status
Simulation time 2410278241 ps
CPU time 45.12 seconds
Started Mar 14 02:06:12 PM PDT 24
Finished Mar 14 02:06:58 PM PDT 24
Peak memory 239248 kb
Host smart-7919a6d8-2424-4348-8e61-75a97546eff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1556987690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1556987690
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3047839742
Short name T711
Test name
Test status
Simulation time 14839949 ps
CPU time 2.99 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:07:13 PM PDT 24
Peak memory 249296 kb
Host smart-af2160ce-5619-4b23-9eda-f572a0023c4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3047839742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3047839742
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.4245567177
Short name T496
Test name
Test status
Simulation time 31921224698 ps
CPU time 2016.59 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:40:47 PM PDT 24
Peak memory 281916 kb
Host smart-1a242f10-81bf-4fb9-8236-c30310667be3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245567177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4245567177
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3481583176
Short name T213
Test name
Test status
Simulation time 1046742435 ps
CPU time 12.71 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:07:23 PM PDT 24
Peak memory 240888 kb
Host smart-5314b1a2-9ecc-484c-8b52-2f158d4709bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3481583176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3481583176
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3137429120
Short name T592
Test name
Test status
Simulation time 7606102561 ps
CPU time 140.1 seconds
Started Mar 14 02:07:09 PM PDT 24
Finished Mar 14 02:09:30 PM PDT 24
Peak memory 257060 kb
Host smart-750835a4-6f33-486f-9be0-bd350a715b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31374
29120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3137429120
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1640424861
Short name T83
Test name
Test status
Simulation time 2229629272 ps
CPU time 28.11 seconds
Started Mar 14 02:07:13 PM PDT 24
Finished Mar 14 02:07:42 PM PDT 24
Peak memory 249500 kb
Host smart-c54b5d6e-a54e-4ce1-a093-a0aa01ced57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
24861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1640424861
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1004499604
Short name T694
Test name
Test status
Simulation time 27473294632 ps
CPU time 833.35 seconds
Started Mar 14 02:07:11 PM PDT 24
Finished Mar 14 02:21:04 PM PDT 24
Peak memory 273752 kb
Host smart-8a58fbc2-dc25-4d2e-abd9-1c99a1a2489e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004499604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1004499604
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3278555598
Short name T525
Test name
Test status
Simulation time 3360513451 ps
CPU time 46.96 seconds
Started Mar 14 02:06:58 PM PDT 24
Finished Mar 14 02:07:46 PM PDT 24
Peak memory 249176 kb
Host smart-c994e321-0f75-400e-ac4e-c00e2891c6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32785
55598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3278555598
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3939975172
Short name T560
Test name
Test status
Simulation time 4927763682 ps
CPU time 50.54 seconds
Started Mar 14 02:07:11 PM PDT 24
Finished Mar 14 02:08:01 PM PDT 24
Peak memory 256856 kb
Host smart-145d8b71-08d2-47ac-a82b-7ce501ac1be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39399
75172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3939975172
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1430906000
Short name T12
Test name
Test status
Simulation time 927062201 ps
CPU time 29.69 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:07:40 PM PDT 24
Peak memory 269904 kb
Host smart-0f95f75b-5970-4a8b-a2bc-9af4e6108671
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1430906000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1430906000
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.4035451362
Short name T85
Test name
Test status
Simulation time 2287175021 ps
CPU time 78.1 seconds
Started Mar 14 02:07:13 PM PDT 24
Finished Mar 14 02:08:32 PM PDT 24
Peak memory 255908 kb
Host smart-e9896ad4-1cff-44ae-9b78-5fea5fccb3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40354
51362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.4035451362
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.402368583
Short name T278
Test name
Test status
Simulation time 81569923 ps
CPU time 8.98 seconds
Started Mar 14 02:07:05 PM PDT 24
Finished Mar 14 02:07:14 PM PDT 24
Peak memory 249060 kb
Host smart-aad7f3b7-14e2-4a42-a829-8b17e5e62d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40236
8583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.402368583
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2822057942
Short name T607
Test name
Test status
Simulation time 2181893948 ps
CPU time 195.91 seconds
Started Mar 14 02:07:09 PM PDT 24
Finished Mar 14 02:10:25 PM PDT 24
Peak memory 257320 kb
Host smart-c7567f20-0fe0-44a8-bf66-b24c96a6f618
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822057942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2822057942
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2723192232
Short name T421
Test name
Test status
Simulation time 502013437182 ps
CPU time 1465.83 seconds
Started Mar 14 02:07:09 PM PDT 24
Finished Mar 14 02:31:35 PM PDT 24
Peak memory 266548 kb
Host smart-130fe7a9-8e42-42fe-b992-ff84b41c5bb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723192232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2723192232
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1578569593
Short name T485
Test name
Test status
Simulation time 510216798 ps
CPU time 9.17 seconds
Started Mar 14 02:07:20 PM PDT 24
Finished Mar 14 02:07:29 PM PDT 24
Peak memory 240828 kb
Host smart-2a2b08d0-d9c3-4c62-8b46-b970b21b08bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1578569593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1578569593
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3086259250
Short name T578
Test name
Test status
Simulation time 601096873 ps
CPU time 61.73 seconds
Started Mar 14 02:07:13 PM PDT 24
Finished Mar 14 02:08:15 PM PDT 24
Peak memory 257108 kb
Host smart-e9955d08-15eb-4ae8-80e9-df551c85d061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30862
59250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3086259250
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.4006754362
Short name T385
Test name
Test status
Simulation time 780724937 ps
CPU time 51.55 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:08:01 PM PDT 24
Peak memory 249000 kb
Host smart-55ba72e6-0afd-4cf1-b340-a3ac67f1e944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40067
54362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.4006754362
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3597613661
Short name T328
Test name
Test status
Simulation time 286790033582 ps
CPU time 1435.31 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:31:18 PM PDT 24
Peak memory 285920 kb
Host smart-bd0b1121-3626-4508-a1d7-c117aaf2ba09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597613661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3597613661
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3298971013
Short name T443
Test name
Test status
Simulation time 20464358182 ps
CPU time 999.2 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:24:02 PM PDT 24
Peak memory 281332 kb
Host smart-026b1015-3efd-438d-9e0a-9563e40eea8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298971013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3298971013
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.218876658
Short name T618
Test name
Test status
Simulation time 160208696729 ps
CPU time 463.8 seconds
Started Mar 14 02:07:09 PM PDT 24
Finished Mar 14 02:14:53 PM PDT 24
Peak memory 248168 kb
Host smart-ff56c992-976c-4436-afcd-fc0de2cf32a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218876658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.218876658
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2482266011
Short name T487
Test name
Test status
Simulation time 5926497732 ps
CPU time 29.31 seconds
Started Mar 14 02:07:13 PM PDT 24
Finished Mar 14 02:07:43 PM PDT 24
Peak memory 255508 kb
Host smart-54dd1da1-ac47-429f-ac25-7fec623231f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
66011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2482266011
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3367153719
Short name T411
Test name
Test status
Simulation time 2401512688 ps
CPU time 39.22 seconds
Started Mar 14 02:07:10 PM PDT 24
Finished Mar 14 02:07:49 PM PDT 24
Peak memory 249544 kb
Host smart-7b177db6-ac1a-46c7-be1e-5b4152614166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671
53719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3367153719
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2048518703
Short name T36
Test name
Test status
Simulation time 832847827 ps
CPU time 27.41 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:07:50 PM PDT 24
Peak memory 273892 kb
Host smart-c8b3b2b2-c437-419e-9aeb-2d3dba220ff0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2048518703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2048518703
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1935458764
Short name T369
Test name
Test status
Simulation time 1005709910 ps
CPU time 29.23 seconds
Started Mar 14 02:07:09 PM PDT 24
Finished Mar 14 02:07:38 PM PDT 24
Peak memory 255576 kb
Host smart-1c00b6ff-69fc-43a9-833c-2369bc6b0a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
58764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1935458764
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3958508835
Short name T423
Test name
Test status
Simulation time 412559970 ps
CPU time 30.36 seconds
Started Mar 14 02:07:09 PM PDT 24
Finished Mar 14 02:07:40 PM PDT 24
Peak memory 249064 kb
Host smart-99ddb279-3b5b-4be3-a6ee-46a8a932a9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
08835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3958508835
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.740256719
Short name T408
Test name
Test status
Simulation time 157945796066 ps
CPU time 2284.25 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:46:02 PM PDT 24
Peak memory 281984 kb
Host smart-aef311a6-87da-4bc6-8ad0-534fbb7adb1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740256719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.740256719
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2474040476
Short name T467
Test name
Test status
Simulation time 117020077 ps
CPU time 6.48 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:08:04 PM PDT 24
Peak memory 240772 kb
Host smart-5a5e7e78-74d3-48de-96d7-70b5a2a970c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2474040476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2474040476
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2500497036
Short name T41
Test name
Test status
Simulation time 1681725499 ps
CPU time 32.45 seconds
Started Mar 14 02:07:55 PM PDT 24
Finished Mar 14 02:08:28 PM PDT 24
Peak memory 256168 kb
Host smart-1cd40ac5-12b0-4f97-84e2-86580c09aafc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
97036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2500497036
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1946959619
Short name T508
Test name
Test status
Simulation time 2817965694 ps
CPU time 37.63 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:08:35 PM PDT 24
Peak memory 248988 kb
Host smart-3c6771c5-aac2-4dd7-b826-d657f7223747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
59619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1946959619
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1659652485
Short name T333
Test name
Test status
Simulation time 27983365834 ps
CPU time 1637.93 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:35:16 PM PDT 24
Peak memory 266532 kb
Host smart-41e528f3-81cb-426f-be45-1ef6a5232fa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659652485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1659652485
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.127247477
Short name T465
Test name
Test status
Simulation time 106781960233 ps
CPU time 1475.67 seconds
Started Mar 14 02:07:56 PM PDT 24
Finished Mar 14 02:32:32 PM PDT 24
Peak memory 273780 kb
Host smart-a7831633-f226-4629-a78b-4541749d6f17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127247477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.127247477
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1714420274
Short name T301
Test name
Test status
Simulation time 23265961301 ps
CPU time 526.92 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:16:45 PM PDT 24
Peak memory 248208 kb
Host smart-beb2ff9a-abe0-41a4-bad2-79031f106a74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714420274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1714420274
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.363080775
Short name T171
Test name
Test status
Simulation time 174044920 ps
CPU time 12.7 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:11 PM PDT 24
Peak memory 249056 kb
Host smart-6d3db95b-3726-4da4-b85f-a00797839a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36308
0775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.363080775
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.744988196
Short name T673
Test name
Test status
Simulation time 1156040634 ps
CPU time 24.34 seconds
Started Mar 14 02:07:56 PM PDT 24
Finished Mar 14 02:08:20 PM PDT 24
Peak memory 247460 kb
Host smart-77ce4e3a-a442-4c6b-ba08-48bb597013ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74498
8196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.744988196
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3770099452
Short name T87
Test name
Test status
Simulation time 658942880 ps
CPU time 25.74 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:08:21 PM PDT 24
Peak memory 255076 kb
Host smart-716db613-07dc-4fb9-b55a-16862e7cd0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37700
99452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3770099452
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2477254342
Short name T551
Test name
Test status
Simulation time 327662991 ps
CPU time 20.93 seconds
Started Mar 14 02:07:59 PM PDT 24
Finished Mar 14 02:08:20 PM PDT 24
Peak memory 249332 kb
Host smart-8f259bf4-0041-469a-8733-963f29470de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24772
54342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2477254342
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2370144087
Short name T186
Test name
Test status
Simulation time 14130412 ps
CPU time 2.75 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:08:05 PM PDT 24
Peak memory 249316 kb
Host smart-d8a5896e-bd56-4ed0-8d65-2392d4d169bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2370144087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2370144087
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4027722177
Short name T398
Test name
Test status
Simulation time 22441129824 ps
CPU time 1190.44 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:27:53 PM PDT 24
Peak memory 281888 kb
Host smart-43cba9ac-fc04-40d5-8d44-cabbeba0f237
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027722177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4027722177
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1219136799
Short name T623
Test name
Test status
Simulation time 463945700 ps
CPU time 14.71 seconds
Started Mar 14 02:08:03 PM PDT 24
Finished Mar 14 02:08:18 PM PDT 24
Peak memory 249092 kb
Host smart-3b456c99-bd1f-4ad5-a81e-5d5007f89b5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1219136799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1219136799
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1214252889
Short name T68
Test name
Test status
Simulation time 107045915 ps
CPU time 7.23 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:08:09 PM PDT 24
Peak memory 240524 kb
Host smart-3b774a03-ef69-416b-a10f-4c9502b119e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
52889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1214252889
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1615791711
Short name T528
Test name
Test status
Simulation time 238171795 ps
CPU time 13.8 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 02:08:23 PM PDT 24
Peak memory 247668 kb
Host smart-73f29aec-a0db-4a3b-9fd5-af87f40fb3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16157
91711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1615791711
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.589470572
Short name T287
Test name
Test status
Simulation time 158523501092 ps
CPU time 2400.02 seconds
Started Mar 14 02:08:10 PM PDT 24
Finished Mar 14 02:48:11 PM PDT 24
Peak memory 288912 kb
Host smart-7713c437-d27f-4034-83a6-dc4f2617c7b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589470572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.589470572
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.4181491833
Short name T460
Test name
Test status
Simulation time 43504028370 ps
CPU time 1035.98 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 02:25:26 PM PDT 24
Peak memory 273236 kb
Host smart-f58eab5b-2918-4cf6-a921-03fe1877052b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181491833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4181491833
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2976195638
Short name T534
Test name
Test status
Simulation time 952893457 ps
CPU time 12.45 seconds
Started Mar 14 02:08:10 PM PDT 24
Finished Mar 14 02:08:23 PM PDT 24
Peak memory 255500 kb
Host smart-05195605-3e8a-409c-bdbe-d438e85cdd8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29761
95638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2976195638
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.811735763
Short name T539
Test name
Test status
Simulation time 162298005 ps
CPU time 10.92 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:08:12 PM PDT 24
Peak memory 250948 kb
Host smart-376833d2-e692-48b7-8f55-3fb89eb884a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81173
5763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.811735763
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2198285728
Short name T661
Test name
Test status
Simulation time 323118009 ps
CPU time 26.52 seconds
Started Mar 14 02:08:00 PM PDT 24
Finished Mar 14 02:08:27 PM PDT 24
Peak memory 247880 kb
Host smart-a36ae1be-8227-4b3b-8ffa-7d3ad79c03a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21982
85728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2198285728
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3114660362
Short name T688
Test name
Test status
Simulation time 621555451 ps
CPU time 22.01 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:08:24 PM PDT 24
Peak memory 254976 kb
Host smart-bf21bad0-0652-49d7-96f6-6aac6803808d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31146
60362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3114660362
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3845504560
Short name T201
Test name
Test status
Simulation time 62899531 ps
CPU time 3.83 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:08:05 PM PDT 24
Peak memory 249272 kb
Host smart-9d8d6c1d-3fa2-4047-91dd-55c341dbc3dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3845504560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3845504560
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2846965121
Short name T542
Test name
Test status
Simulation time 13898838625 ps
CPU time 786.08 seconds
Started Mar 14 02:08:10 PM PDT 24
Finished Mar 14 02:21:17 PM PDT 24
Peak memory 273772 kb
Host smart-e4132ec1-3a0c-4306-a7e3-4f51662fb9e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846965121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2846965121
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2172851403
Short name T568
Test name
Test status
Simulation time 546643670 ps
CPU time 9.45 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:08:11 PM PDT 24
Peak memory 240872 kb
Host smart-d06692f2-0c88-4978-b6e2-0fbf47d8d4bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2172851403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2172851403
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.633698657
Short name T368
Test name
Test status
Simulation time 3362060299 ps
CPU time 181.04 seconds
Started Mar 14 02:08:00 PM PDT 24
Finished Mar 14 02:11:01 PM PDT 24
Peak memory 251604 kb
Host smart-6ea9387b-d6ba-48c5-98c9-bfc202a16a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63369
8657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.633698657
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3072122334
Short name T554
Test name
Test status
Simulation time 522902650 ps
CPU time 35.38 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 02:08:45 PM PDT 24
Peak memory 249056 kb
Host smart-6f4c1d34-4abd-42e5-912d-531ecc4bd9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721
22334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3072122334
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2245960418
Short name T218
Test name
Test status
Simulation time 55351176325 ps
CPU time 1224.43 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:28:26 PM PDT 24
Peak memory 289172 kb
Host smart-15b5fcb7-3d9d-4a57-ab60-2ef22271a116
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245960418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2245960418
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2447101913
Short name T665
Test name
Test status
Simulation time 29499079849 ps
CPU time 667.65 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:19:09 PM PDT 24
Peak memory 248424 kb
Host smart-6048d5a7-b483-4b43-9fb9-8a4037788946
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447101913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2447101913
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1041146132
Short name T274
Test name
Test status
Simulation time 1178396896 ps
CPU time 14.74 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:08:16 PM PDT 24
Peak memory 249060 kb
Host smart-50ac14ca-63bd-402c-8d21-435fe977733f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10411
46132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1041146132
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.4030812381
Short name T96
Test name
Test status
Simulation time 1407056122 ps
CPU time 34.89 seconds
Started Mar 14 02:08:03 PM PDT 24
Finished Mar 14 02:08:38 PM PDT 24
Peak memory 248736 kb
Host smart-b8ee6791-5453-41ba-aa43-5867a4d3e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40308
12381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4030812381
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2457496763
Short name T259
Test name
Test status
Simulation time 1693433694 ps
CPU time 47.99 seconds
Started Mar 14 02:08:09 PM PDT 24
Finished Mar 14 02:08:58 PM PDT 24
Peak memory 249048 kb
Host smart-da8b0ad8-a7fd-44c5-b0c4-1d8301b4e6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24574
96763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2457496763
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.231955532
Short name T526
Test name
Test status
Simulation time 1192209553 ps
CPU time 34.76 seconds
Started Mar 14 02:08:08 PM PDT 24
Finished Mar 14 02:08:43 PM PDT 24
Peak memory 249124 kb
Host smart-19a753fc-22c8-4570-9b5c-fb890c63d453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23195
5532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.231955532
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1745013463
Short name T286
Test name
Test status
Simulation time 117726540357 ps
CPU time 1686.26 seconds
Started Mar 14 02:08:02 PM PDT 24
Finished Mar 14 02:36:08 PM PDT 24
Peak memory 290112 kb
Host smart-416672ba-8e9d-4a9f-8420-278e6204e55e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745013463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1745013463
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3161909860
Short name T75
Test name
Test status
Simulation time 94610485274 ps
CPU time 1610.29 seconds
Started Mar 14 02:08:15 PM PDT 24
Finished Mar 14 02:35:06 PM PDT 24
Peak memory 273072 kb
Host smart-e16cbe10-af27-4fcb-9d33-642f988fd9db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161909860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3161909860
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3679320996
Short name T533
Test name
Test status
Simulation time 3751676081 ps
CPU time 38.43 seconds
Started Mar 14 02:08:13 PM PDT 24
Finished Mar 14 02:08:52 PM PDT 24
Peak memory 249172 kb
Host smart-c6e828bd-659a-470d-92dd-933c65d49127
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3679320996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3679320996
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1247665075
Short name T690
Test name
Test status
Simulation time 3574218678 ps
CPU time 198.99 seconds
Started Mar 14 02:08:14 PM PDT 24
Finished Mar 14 02:11:33 PM PDT 24
Peak memory 256832 kb
Host smart-afc7fffb-e820-4287-a201-826ffcdcb798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12476
65075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1247665075
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2911559111
Short name T400
Test name
Test status
Simulation time 847444218 ps
CPU time 49.44 seconds
Started Mar 14 02:08:13 PM PDT 24
Finished Mar 14 02:09:03 PM PDT 24
Peak memory 255656 kb
Host smart-203b28bb-4295-4c3d-87f1-8fdaf7c6eb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29115
59111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2911559111
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1290589843
Short name T621
Test name
Test status
Simulation time 166773237323 ps
CPU time 2206.34 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:44:59 PM PDT 24
Peak memory 284816 kb
Host smart-70d63321-b932-454a-acf7-36c0eca117e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290589843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1290589843
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4273599463
Short name T654
Test name
Test status
Simulation time 176896136 ps
CPU time 22.01 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:08:34 PM PDT 24
Peak memory 247612 kb
Host smart-d72dd42c-36e5-4e2c-89c5-bd8cae60d51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
99463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4273599463
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2350661461
Short name T418
Test name
Test status
Simulation time 272160944 ps
CPU time 7.7 seconds
Started Mar 14 02:08:10 PM PDT 24
Finished Mar 14 02:08:18 PM PDT 24
Peak memory 249108 kb
Host smart-5a1a4af3-8444-445e-9cb5-392a86927a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23506
61461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2350661461
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3370565396
Short name T472
Test name
Test status
Simulation time 23136035501 ps
CPU time 1513.7 seconds
Started Mar 14 02:08:14 PM PDT 24
Finished Mar 14 02:33:28 PM PDT 24
Peak memory 273332 kb
Host smart-36e735e3-ad0f-4548-a30a-7c8a942b33f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370565396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3370565396
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3418831810
Short name T243
Test name
Test status
Simulation time 147168556212 ps
CPU time 5521.14 seconds
Started Mar 14 02:08:13 PM PDT 24
Finished Mar 14 03:40:16 PM PDT 24
Peak memory 306256 kb
Host smart-e5238cea-0582-4e4e-aa15-9d3a5faad189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418831810 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3418831810
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3043971126
Short name T88
Test name
Test status
Simulation time 53297752 ps
CPU time 2.33 seconds
Started Mar 14 02:08:17 PM PDT 24
Finished Mar 14 02:08:19 PM PDT 24
Peak memory 249208 kb
Host smart-7824c448-26d8-46ab-af01-5b38f339a837
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3043971126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3043971126
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.444878733
Short name T563
Test name
Test status
Simulation time 44437123269 ps
CPU time 2551.77 seconds
Started Mar 14 02:08:14 PM PDT 24
Finished Mar 14 02:50:46 PM PDT 24
Peak memory 289484 kb
Host smart-a8179a82-37e9-41e6-a4de-937239784dce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444878733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.444878733
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1063296671
Short name T373
Test name
Test status
Simulation time 982700746 ps
CPU time 33.65 seconds
Started Mar 14 02:08:16 PM PDT 24
Finished Mar 14 02:08:49 PM PDT 24
Peak memory 240768 kb
Host smart-9b79d350-c2ab-4960-8996-21d0414c56e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1063296671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1063296671
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1909979308
Short name T622
Test name
Test status
Simulation time 10755234595 ps
CPU time 161.74 seconds
Started Mar 14 02:08:17 PM PDT 24
Finished Mar 14 02:10:59 PM PDT 24
Peak memory 257344 kb
Host smart-850354f7-1199-47b8-8b74-b9652ada654e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
79308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1909979308
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2012673396
Short name T281
Test name
Test status
Simulation time 85510817042 ps
CPU time 725.51 seconds
Started Mar 14 02:08:13 PM PDT 24
Finished Mar 14 02:20:20 PM PDT 24
Peak memory 265568 kb
Host smart-a1445036-012f-4eb6-9dc6-42a8f0bee1a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012673396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2012673396
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2468680195
Short name T580
Test name
Test status
Simulation time 7388536069 ps
CPU time 287.57 seconds
Started Mar 14 02:08:17 PM PDT 24
Finished Mar 14 02:13:05 PM PDT 24
Peak memory 248232 kb
Host smart-39304cd7-20d5-46ee-af42-ce9b16879e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468680195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2468680195
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2603386390
Short name T523
Test name
Test status
Simulation time 284383992 ps
CPU time 17.51 seconds
Started Mar 14 02:08:14 PM PDT 24
Finished Mar 14 02:08:32 PM PDT 24
Peak memory 249088 kb
Host smart-040c05c3-d42c-4756-9ae5-c7a19e2d0dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26033
86390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2603386390
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1882100629
Short name T394
Test name
Test status
Simulation time 5593614685 ps
CPU time 54.39 seconds
Started Mar 14 02:08:12 PM PDT 24
Finished Mar 14 02:09:06 PM PDT 24
Peak memory 247912 kb
Host smart-3006ecae-8909-4c2d-9f83-f469035b3ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18821
00629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1882100629
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3833175211
Short name T652
Test name
Test status
Simulation time 522384460 ps
CPU time 31.58 seconds
Started Mar 14 02:08:15 PM PDT 24
Finished Mar 14 02:08:47 PM PDT 24
Peak memory 249064 kb
Host smart-c9649038-41a5-46d2-b9c7-c91453f3defb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38331
75211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3833175211
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2078418563
Short name T416
Test name
Test status
Simulation time 2906373376 ps
CPU time 45.25 seconds
Started Mar 14 02:08:13 PM PDT 24
Finished Mar 14 02:08:59 PM PDT 24
Peak memory 249212 kb
Host smart-e4e597a0-d113-402a-aa9e-edf075b3cf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20784
18563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2078418563
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2177578572
Short name T693
Test name
Test status
Simulation time 11520687327 ps
CPU time 671.19 seconds
Started Mar 14 02:08:15 PM PDT 24
Finished Mar 14 02:19:26 PM PDT 24
Peak memory 257364 kb
Host smart-571f083f-e0bb-4de6-a757-6a59d3bef042
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177578572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2177578572
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4105218991
Short name T190
Test name
Test status
Simulation time 33660199 ps
CPU time 3.21 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:08:27 PM PDT 24
Peak memory 249316 kb
Host smart-90a0c65e-07ab-4a3a-bb0f-d971e12728e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4105218991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4105218991
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2154758962
Short name T366
Test name
Test status
Simulation time 15052330102 ps
CPU time 847.7 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:22:32 PM PDT 24
Peak memory 273756 kb
Host smart-4436e672-fde4-47c3-8f46-d422e9097f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154758962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2154758962
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.948104198
Short name T582
Test name
Test status
Simulation time 4680577395 ps
CPU time 49.25 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:09:14 PM PDT 24
Peak memory 249196 kb
Host smart-a2eec372-3c82-437a-a221-4fa654b8a116
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=948104198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.948104198
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3990378546
Short name T439
Test name
Test status
Simulation time 39988780591 ps
CPU time 152.67 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:10:56 PM PDT 24
Peak memory 257284 kb
Host smart-9a7ff070-cb50-43e0-a6c6-65dbd71822a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
78546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3990378546
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.955848440
Short name T77
Test name
Test status
Simulation time 947143858 ps
CPU time 31.75 seconds
Started Mar 14 02:08:37 PM PDT 24
Finished Mar 14 02:09:09 PM PDT 24
Peak memory 249380 kb
Host smart-aed61afa-b50e-4e3a-861a-20ae8d4617f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95584
8440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.955848440
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2266723378
Short name T98
Test name
Test status
Simulation time 22586749004 ps
CPU time 1443.76 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:32:28 PM PDT 24
Peak memory 281916 kb
Host smart-9c149f4d-3df8-4cfd-8b06-f1bc98f1fa36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266723378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2266723378
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3023868604
Short name T425
Test name
Test status
Simulation time 8828195491 ps
CPU time 783.56 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:21:28 PM PDT 24
Peak memory 269936 kb
Host smart-46fcec95-6850-4444-89f0-3d2273835f40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023868604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3023868604
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1533755455
Short name T311
Test name
Test status
Simulation time 11379495988 ps
CPU time 115.4 seconds
Started Mar 14 02:08:27 PM PDT 24
Finished Mar 14 02:10:23 PM PDT 24
Peak memory 247204 kb
Host smart-c5ef4145-924c-48d5-82a0-2ecf5bea602b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533755455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1533755455
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2285826249
Short name T262
Test name
Test status
Simulation time 273042786 ps
CPU time 25.18 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:08:48 PM PDT 24
Peak memory 249000 kb
Host smart-2833a24a-f409-49ca-8d3c-a0a2ad733bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22858
26249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2285826249
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1293983108
Short name T434
Test name
Test status
Simulation time 891782464 ps
CPU time 28.26 seconds
Started Mar 14 02:08:22 PM PDT 24
Finished Mar 14 02:08:51 PM PDT 24
Peak memory 256172 kb
Host smart-b8e2d2ce-7883-49de-8f0f-208632699a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12939
83108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1293983108
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3653915939
Short name T681
Test name
Test status
Simulation time 697977083 ps
CPU time 47.68 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:09:11 PM PDT 24
Peak memory 256164 kb
Host smart-02d8b6cf-5fe8-4d92-a4bf-35355d5626a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36539
15939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3653915939
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3332641741
Short name T565
Test name
Test status
Simulation time 679965908 ps
CPU time 42.54 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:09:07 PM PDT 24
Peak memory 248052 kb
Host smart-8bd191eb-66d8-4978-a721-630ed77b09a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332641741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3332641741
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.826994075
Short name T538
Test name
Test status
Simulation time 21732027790 ps
CPU time 1508.83 seconds
Started Mar 14 02:08:25 PM PDT 24
Finished Mar 14 02:33:34 PM PDT 24
Peak memory 282120 kb
Host smart-c3075026-fcc7-48a1-895d-3ad62e5a1141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826994075 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.826994075
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2786421262
Short name T200
Test name
Test status
Simulation time 70244016 ps
CPU time 3.54 seconds
Started Mar 14 02:08:26 PM PDT 24
Finished Mar 14 02:08:29 PM PDT 24
Peak memory 249312 kb
Host smart-d0fa1b9f-cc86-4f90-8c42-4af51e53f0a7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2786421262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2786421262
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.799080847
Short name T449
Test name
Test status
Simulation time 46858669880 ps
CPU time 1393.8 seconds
Started Mar 14 02:08:25 PM PDT 24
Finished Mar 14 02:31:39 PM PDT 24
Peak memory 273684 kb
Host smart-e82afec2-1018-47b3-b89b-7b21bf4ede0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799080847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.799080847
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.421941027
Short name T6
Test name
Test status
Simulation time 1098147884 ps
CPU time 16.22 seconds
Started Mar 14 02:08:26 PM PDT 24
Finished Mar 14 02:08:43 PM PDT 24
Peak memory 240936 kb
Host smart-8e1d0cc9-5b0d-4989-82de-31ff44fea83a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=421941027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.421941027
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.6445429
Short name T350
Test name
Test status
Simulation time 623845519 ps
CPU time 43.56 seconds
Started Mar 14 02:08:26 PM PDT 24
Finished Mar 14 02:09:10 PM PDT 24
Peak memory 256792 kb
Host smart-0b087129-048a-4710-ac16-06b533c52a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64454
29 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.6445429
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2372250709
Short name T510
Test name
Test status
Simulation time 2031507517 ps
CPU time 22.48 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:08:46 PM PDT 24
Peak memory 255800 kb
Host smart-8d70eea6-34ad-44a3-8760-731307ec5620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23722
50709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2372250709
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3725316324
Short name T73
Test name
Test status
Simulation time 37680750984 ps
CPU time 745.73 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:20:49 PM PDT 24
Peak memory 272916 kb
Host smart-e07f9891-f3f5-4f1e-b41a-8be24fe4c66f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725316324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3725316324
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2036142696
Short name T677
Test name
Test status
Simulation time 47547858115 ps
CPU time 1451.26 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:32:35 PM PDT 24
Peak memory 273068 kb
Host smart-532ea97a-fc14-4688-a61b-a7fa1ce57e35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036142696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2036142696
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2179783445
Short name T284
Test name
Test status
Simulation time 585937029 ps
CPU time 38.65 seconds
Started Mar 14 02:08:25 PM PDT 24
Finished Mar 14 02:09:04 PM PDT 24
Peak memory 256100 kb
Host smart-80dea8a9-0a9e-46cf-aafa-0ac7f5f142c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21797
83445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2179783445
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1585329603
Short name T543
Test name
Test status
Simulation time 1445486308 ps
CPU time 37.62 seconds
Started Mar 14 02:08:25 PM PDT 24
Finished Mar 14 02:09:03 PM PDT 24
Peak memory 248100 kb
Host smart-d080d961-55a4-4b51-8319-60458cfd13c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15853
29603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1585329603
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1677861755
Short name T707
Test name
Test status
Simulation time 490648174 ps
CPU time 25.2 seconds
Started Mar 14 02:08:23 PM PDT 24
Finished Mar 14 02:08:48 PM PDT 24
Peak memory 249032 kb
Host smart-8acc2810-3d16-48b1-8b52-27e53ec80dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
61755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1677861755
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1972150746
Short name T454
Test name
Test status
Simulation time 5021549688 ps
CPU time 26.63 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:08:50 PM PDT 24
Peak memory 249136 kb
Host smart-47efa834-cdeb-4cad-a3d8-691e73211348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19721
50746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1972150746
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.769544507
Short name T488
Test name
Test status
Simulation time 44594861679 ps
CPU time 2389.62 seconds
Started Mar 14 02:08:27 PM PDT 24
Finished Mar 14 02:48:17 PM PDT 24
Peak memory 281972 kb
Host smart-9109e973-b656-4518-a5e9-719e1592987a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769544507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.769544507
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.572172962
Short name T17
Test name
Test status
Simulation time 33096181 ps
CPU time 3.37 seconds
Started Mar 14 02:08:37 PM PDT 24
Finished Mar 14 02:08:40 PM PDT 24
Peak memory 249248 kb
Host smart-a629884d-257c-40e8-b44d-c71ae7750112
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=572172962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.572172962
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.433015075
Short name T581
Test name
Test status
Simulation time 4941798559 ps
CPU time 514.68 seconds
Started Mar 14 02:08:37 PM PDT 24
Finished Mar 14 02:17:12 PM PDT 24
Peak memory 265528 kb
Host smart-c097ec54-84b0-4e6f-99f7-3ff959599b17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433015075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.433015075
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.82177913
Short name T223
Test name
Test status
Simulation time 1942009118 ps
CPU time 46.24 seconds
Started Mar 14 02:08:37 PM PDT 24
Finished Mar 14 02:09:23 PM PDT 24
Peak memory 249080 kb
Host smart-da3bfb52-ab95-4313-b0b4-f85ba0658ba8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=82177913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.82177913
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.56394568
Short name T576
Test name
Test status
Simulation time 5580213761 ps
CPU time 101.36 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:10:17 PM PDT 24
Peak memory 257368 kb
Host smart-4b677885-a1ec-4d8c-abf7-9d68407d2474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56394
568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.56394568
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.207214369
Short name T486
Test name
Test status
Simulation time 977973142 ps
CPU time 58.84 seconds
Started Mar 14 02:08:39 PM PDT 24
Finished Mar 14 02:09:38 PM PDT 24
Peak memory 255780 kb
Host smart-8aac8f4e-6ee0-41f2-b970-0db519f9a0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
4369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.207214369
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2891590890
Short name T588
Test name
Test status
Simulation time 15899965758 ps
CPU time 1406.26 seconds
Started Mar 14 02:08:37 PM PDT 24
Finished Mar 14 02:32:03 PM PDT 24
Peak memory 289268 kb
Host smart-7f91ee73-3f44-4d28-a8eb-7d4ae83cc6e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891590890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2891590890
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3127642663
Short name T106
Test name
Test status
Simulation time 7244468514 ps
CPU time 860.56 seconds
Started Mar 14 02:08:37 PM PDT 24
Finished Mar 14 02:22:57 PM PDT 24
Peak memory 273240 kb
Host smart-00c30324-1ea4-474c-8421-f66cd314e881
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127642663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3127642663
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4181910901
Short name T305
Test name
Test status
Simulation time 11759323194 ps
CPU time 443.98 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:16:00 PM PDT 24
Peak memory 248096 kb
Host smart-e6fc241b-7cd2-426a-9c2d-17cbaf7b7ed6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181910901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4181910901
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1959606128
Short name T613
Test name
Test status
Simulation time 974491090 ps
CPU time 28.49 seconds
Started Mar 14 02:08:38 PM PDT 24
Finished Mar 14 02:09:06 PM PDT 24
Peak memory 255920 kb
Host smart-8f19535a-f25d-4bb2-801a-ee24ac5880e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19596
06128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1959606128
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3762940275
Short name T649
Test name
Test status
Simulation time 3266562891 ps
CPU time 38.32 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:09:15 PM PDT 24
Peak memory 255840 kb
Host smart-b5c837f1-2f93-4e51-a114-e7acc8482ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37629
40275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3762940275
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2691479736
Short name T456
Test name
Test status
Simulation time 294554935 ps
CPU time 18.43 seconds
Started Mar 14 02:08:24 PM PDT 24
Finished Mar 14 02:08:43 PM PDT 24
Peak memory 257520 kb
Host smart-9a82684c-fd59-4db0-96ea-cf6641786ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26914
79736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2691479736
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2093040445
Short name T499
Test name
Test status
Simulation time 41475946027 ps
CPU time 1476.63 seconds
Started Mar 14 02:08:35 PM PDT 24
Finished Mar 14 02:33:12 PM PDT 24
Peak memory 273688 kb
Host smart-7f4a1ddd-7535-4e43-b119-9c0c669e83ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093040445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2093040445
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1557749484
Short name T62
Test name
Test status
Simulation time 18712916763 ps
CPU time 1246.2 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:29:22 PM PDT 24
Peak memory 282156 kb
Host smart-a0c468c0-50c7-4811-817e-08fe5e3efa01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557749484 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1557749484
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1674347067
Short name T194
Test name
Test status
Simulation time 52311435 ps
CPU time 2.44 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:08:51 PM PDT 24
Peak memory 249332 kb
Host smart-d961a3bd-0897-4413-ad2d-4fd573a96c58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1674347067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1674347067
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.664852203
Short name T519
Test name
Test status
Simulation time 39841508579 ps
CPU time 863.5 seconds
Started Mar 14 02:08:35 PM PDT 24
Finished Mar 14 02:22:59 PM PDT 24
Peak memory 271864 kb
Host smart-b965b034-0f81-4cc3-88b6-702a6d903f4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664852203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.664852203
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3104178580
Short name T220
Test name
Test status
Simulation time 1136459342 ps
CPU time 28.66 seconds
Started Mar 14 02:08:56 PM PDT 24
Finished Mar 14 02:09:25 PM PDT 24
Peak memory 240808 kb
Host smart-1d9c7da1-f7f9-4257-b454-c0679ee55d17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3104178580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3104178580
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1757352177
Short name T355
Test name
Test status
Simulation time 5006724680 ps
CPU time 71.63 seconds
Started Mar 14 02:08:38 PM PDT 24
Finished Mar 14 02:09:50 PM PDT 24
Peak memory 257088 kb
Host smart-847f6ad2-b8b5-4bd0-94e0-6068e02bd0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17573
52177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1757352177
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2818847169
Short name T364
Test name
Test status
Simulation time 663104855 ps
CPU time 33.33 seconds
Started Mar 14 02:08:35 PM PDT 24
Finished Mar 14 02:09:09 PM PDT 24
Peak memory 256280 kb
Host smart-a02101cc-64fb-4a8a-a86c-ddf7dcc7f538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28188
47169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2818847169
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3029050754
Short name T222
Test name
Test status
Simulation time 170637565621 ps
CPU time 2341.23 seconds
Started Mar 14 02:08:38 PM PDT 24
Finished Mar 14 02:47:39 PM PDT 24
Peak memory 273608 kb
Host smart-6c4d183b-e8b7-4492-9dd2-fe9b6049e7de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029050754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3029050754
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.652517833
Short name T537
Test name
Test status
Simulation time 56927828417 ps
CPU time 1267.72 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:29:44 PM PDT 24
Peak memory 289868 kb
Host smart-449b18c7-f360-462c-918d-3005420af9d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652517833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.652517833
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.489097433
Short name T38
Test name
Test status
Simulation time 48917158166 ps
CPU time 529.39 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:17:26 PM PDT 24
Peak memory 248052 kb
Host smart-fcbaad16-00d5-48ef-90ff-9aa1c72ebe49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489097433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.489097433
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2777811416
Short name T635
Test name
Test status
Simulation time 254753792 ps
CPU time 23.01 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:08:59 PM PDT 24
Peak memory 257256 kb
Host smart-b7c18e42-1dd0-4c0c-a25f-03a6203679b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27778
11416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2777811416
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3406340682
Short name T60
Test name
Test status
Simulation time 1740623441 ps
CPU time 36.46 seconds
Started Mar 14 02:08:35 PM PDT 24
Finished Mar 14 02:09:12 PM PDT 24
Peak memory 247436 kb
Host smart-58e6ded9-a591-4706-b966-7b4c4c379f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
40682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3406340682
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1602028469
Short name T387
Test name
Test status
Simulation time 1980653622 ps
CPU time 35.44 seconds
Started Mar 14 02:08:36 PM PDT 24
Finished Mar 14 02:09:11 PM PDT 24
Peak memory 257184 kb
Host smart-5384b858-c28e-492e-b5e6-9b9b443abde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16020
28469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1602028469
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.940923550
Short name T451
Test name
Test status
Simulation time 34297411446 ps
CPU time 2205.66 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:45:35 PM PDT 24
Peak memory 289488 kb
Host smart-5bbc107e-40fb-49d0-b698-dd2d792a7293
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940923550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.940923550
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2720962217
Short name T232
Test name
Test status
Simulation time 118026099908 ps
CPU time 4858.18 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 03:29:48 PM PDT 24
Peak memory 322404 kb
Host smart-6104ef1f-b892-42e1-9794-02c12a3fca41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720962217 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2720962217
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4017185091
Short name T191
Test name
Test status
Simulation time 69775220 ps
CPU time 3.13 seconds
Started Mar 14 02:08:48 PM PDT 24
Finished Mar 14 02:08:51 PM PDT 24
Peak memory 249312 kb
Host smart-854763c4-dee4-4e44-be49-f83cd368dd7a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4017185091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4017185091
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2124195621
Short name T611
Test name
Test status
Simulation time 58464910633 ps
CPU time 1096.49 seconds
Started Mar 14 02:08:48 PM PDT 24
Finished Mar 14 02:27:05 PM PDT 24
Peak memory 271984 kb
Host smart-51bd1707-c87e-47ac-807f-43de709ed0b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124195621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2124195621
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1713575544
Short name T714
Test name
Test status
Simulation time 1803976715 ps
CPU time 22.96 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:09:12 PM PDT 24
Peak memory 249036 kb
Host smart-bdfeba30-14a2-43a1-aa70-f8ecd93392a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1713575544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1713575544
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1352598591
Short name T458
Test name
Test status
Simulation time 12977295697 ps
CPU time 274.14 seconds
Started Mar 14 02:08:47 PM PDT 24
Finished Mar 14 02:13:22 PM PDT 24
Peak memory 257148 kb
Host smart-e678b8ac-2f92-4e0d-a82c-c73ecd5932e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13525
98591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1352598591
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1034852084
Short name T370
Test name
Test status
Simulation time 1123553589 ps
CPU time 36.76 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:09:26 PM PDT 24
Peak memory 254932 kb
Host smart-0460b9c1-a522-40d7-b9dc-e90eb8e0baba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10348
52084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1034852084
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3851058484
Short name T332
Test name
Test status
Simulation time 38413678521 ps
CPU time 1985 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:41:54 PM PDT 24
Peak memory 273400 kb
Host smart-c3ecfec2-ce2d-4203-9db5-79c0e01b96ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851058484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3851058484
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2201095599
Short name T641
Test name
Test status
Simulation time 48365199259 ps
CPU time 1320.4 seconds
Started Mar 14 02:08:50 PM PDT 24
Finished Mar 14 02:30:51 PM PDT 24
Peak memory 289192 kb
Host smart-26db3451-ed9c-449e-9ac5-7765e371bfb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201095599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2201095599
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1538435431
Short name T612
Test name
Test status
Simulation time 6220560351 ps
CPU time 253.74 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:13:03 PM PDT 24
Peak memory 247276 kb
Host smart-c698bdb6-85f9-414a-b230-7d787eac1eda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538435431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1538435431
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.272664077
Short name T371
Test name
Test status
Simulation time 2976982324 ps
CPU time 47.51 seconds
Started Mar 14 02:08:48 PM PDT 24
Finished Mar 14 02:09:36 PM PDT 24
Peak memory 255684 kb
Host smart-fcd2da53-bddd-4591-9af9-a8ff96fb961d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27266
4077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.272664077
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1434084240
Short name T256
Test name
Test status
Simulation time 288821994 ps
CPU time 28.42 seconds
Started Mar 14 02:08:48 PM PDT 24
Finished Mar 14 02:09:16 PM PDT 24
Peak memory 249368 kb
Host smart-79a2dca4-2d4a-4c1f-a3a2-7537077cabd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
84240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1434084240
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.408367294
Short name T74
Test name
Test status
Simulation time 321408459 ps
CPU time 25.91 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:09:15 PM PDT 24
Peak memory 256408 kb
Host smart-94a9d6b2-c505-4622-9008-6ae528dde40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40836
7294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.408367294
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3455492322
Short name T446
Test name
Test status
Simulation time 48382861459 ps
CPU time 1240.59 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:29:30 PM PDT 24
Peak memory 289316 kb
Host smart-39881228-0015-4447-9464-24f270acc626
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455492322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3455492322
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2867542931
Short name T57
Test name
Test status
Simulation time 268722136930 ps
CPU time 4026.36 seconds
Started Mar 14 02:08:47 PM PDT 24
Finished Mar 14 03:15:54 PM PDT 24
Peak memory 315860 kb
Host smart-dd8a30dd-4913-4855-9e3d-5774de8e1330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867542931 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2867542931
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1587398704
Short name T187
Test name
Test status
Simulation time 15666486 ps
CPU time 2.69 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:07:25 PM PDT 24
Peak memory 249276 kb
Host smart-6ab870a6-314b-42db-8028-535152d97e88
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1587398704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1587398704
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1959105341
Short name T666
Test name
Test status
Simulation time 22233577608 ps
CPU time 1223.45 seconds
Started Mar 14 02:07:19 PM PDT 24
Finished Mar 14 02:27:43 PM PDT 24
Peak memory 267888 kb
Host smart-b67afafe-f6ba-4b9c-b59c-c27eb314b1e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959105341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1959105341
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1575854438
Short name T610
Test name
Test status
Simulation time 3659733769 ps
CPU time 30.33 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:07:55 PM PDT 24
Peak memory 249092 kb
Host smart-93e447c5-6352-4241-a4b4-c727c8aba5e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1575854438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1575854438
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3926314286
Short name T527
Test name
Test status
Simulation time 3171405155 ps
CPU time 99.01 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:09:01 PM PDT 24
Peak memory 249088 kb
Host smart-62751e97-ca77-4422-bfb5-bb3558dbc460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39263
14286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3926314286
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3953710390
Short name T415
Test name
Test status
Simulation time 8212161427 ps
CPU time 24.32 seconds
Started Mar 14 02:07:24 PM PDT 24
Finished Mar 14 02:07:48 PM PDT 24
Peak memory 255820 kb
Host smart-2c01039a-5b39-409b-9e77-edb8900435be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
10390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3953710390
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1742664491
Short name T45
Test name
Test status
Simulation time 347496662331 ps
CPU time 1299.4 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:29:00 PM PDT 24
Peak memory 267620 kb
Host smart-8640c4ad-7457-4f37-958e-e40b9b298bae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742664491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1742664491
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2658111377
Short name T272
Test name
Test status
Simulation time 87645063981 ps
CPU time 1575.13 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:33:36 PM PDT 24
Peak memory 290072 kb
Host smart-0cca46b3-f4d4-46f0-8f88-6ce3da630785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658111377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2658111377
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2740857863
Short name T4
Test name
Test status
Simulation time 5523003471 ps
CPU time 239.96 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:11:22 PM PDT 24
Peak memory 247200 kb
Host smart-96ad1365-9abf-491f-9609-430b583b043b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740857863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2740857863
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.914227375
Short name T594
Test name
Test status
Simulation time 1012625036 ps
CPU time 42.63 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:08:04 PM PDT 24
Peak memory 249076 kb
Host smart-5e713dae-d8f2-4e79-8501-3e02ef61fc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91422
7375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.914227375
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3541930708
Short name T555
Test name
Test status
Simulation time 6256865303 ps
CPU time 43.54 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:08:06 PM PDT 24
Peak memory 256972 kb
Host smart-afe57c30-40ea-4b11-a326-8f1233e2b4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35419
30708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3541930708
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3511663901
Short name T37
Test name
Test status
Simulation time 1179791877 ps
CPU time 12.85 seconds
Started Mar 14 02:07:19 PM PDT 24
Finished Mar 14 02:07:33 PM PDT 24
Peak memory 265624 kb
Host smart-21ab0328-edd4-4349-8573-9bc7f9bb92d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3511663901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3511663901
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3009520881
Short name T520
Test name
Test status
Simulation time 2879172883 ps
CPU time 45.53 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:08:07 PM PDT 24
Peak memory 255712 kb
Host smart-e31b5d31-2eb8-4d8b-9554-f7d7dbf5be8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30095
20881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3009520881
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4116793503
Short name T579
Test name
Test status
Simulation time 413289498 ps
CPU time 24.91 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:07:50 PM PDT 24
Peak memory 256200 kb
Host smart-71760259-4b37-41bc-8921-a1f8589bbc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41167
93503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4116793503
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2086864272
Short name T56
Test name
Test status
Simulation time 4464649199 ps
CPU time 251.89 seconds
Started Mar 14 02:07:20 PM PDT 24
Finished Mar 14 02:11:32 PM PDT 24
Peak memory 257300 kb
Host smart-0495ed65-4da9-4161-a125-d8b9a20be7c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086864272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2086864272
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1330404199
Short name T23
Test name
Test status
Simulation time 34958221954 ps
CPU time 1160.46 seconds
Started Mar 14 02:07:20 PM PDT 24
Finished Mar 14 02:26:41 PM PDT 24
Peak memory 282344 kb
Host smart-896ada70-fd32-4794-8762-d243a29f74ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330404199 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1330404199
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3038294816
Short name T335
Test name
Test status
Simulation time 43559831487 ps
CPU time 2421.38 seconds
Started Mar 14 02:08:56 PM PDT 24
Finished Mar 14 02:49:18 PM PDT 24
Peak memory 289960 kb
Host smart-f25e175b-55fe-48ec-ac3c-1a566618d3f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038294816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3038294816
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3650197823
Short name T671
Test name
Test status
Simulation time 3156124036 ps
CPU time 123.03 seconds
Started Mar 14 02:08:49 PM PDT 24
Finished Mar 14 02:10:52 PM PDT 24
Peak memory 256880 kb
Host smart-c4e5170b-0646-40ec-b366-d2a90e921b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36501
97823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3650197823
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.727891026
Short name T552
Test name
Test status
Simulation time 339873606 ps
CPU time 24.74 seconds
Started Mar 14 02:08:48 PM PDT 24
Finished Mar 14 02:09:13 PM PDT 24
Peak memory 249096 kb
Host smart-e94e2d65-7c8c-476a-a56e-a5e501bdd976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72789
1026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.727891026
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3332800993
Short name T405
Test name
Test status
Simulation time 41989630946 ps
CPU time 2302.67 seconds
Started Mar 14 02:08:51 PM PDT 24
Finished Mar 14 02:47:14 PM PDT 24
Peak memory 281920 kb
Host smart-f1e82d5f-f5f0-4cd6-8030-0220d7c8778c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332800993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3332800993
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2723386846
Short name T602
Test name
Test status
Simulation time 7744009632 ps
CPU time 295.73 seconds
Started Mar 14 02:08:56 PM PDT 24
Finished Mar 14 02:13:52 PM PDT 24
Peak memory 248024 kb
Host smart-286ace59-eefb-4e83-9b5c-7a4a93397b12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723386846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2723386846
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1683747170
Short name T489
Test name
Test status
Simulation time 229369513 ps
CPU time 9.5 seconds
Started Mar 14 02:08:50 PM PDT 24
Finished Mar 14 02:09:00 PM PDT 24
Peak memory 249120 kb
Host smart-23704242-3ac1-4f24-b3e4-380a0403afac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
47170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1683747170
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.284956646
Short name T61
Test name
Test status
Simulation time 288673011 ps
CPU time 20.81 seconds
Started Mar 14 02:08:55 PM PDT 24
Finished Mar 14 02:09:17 PM PDT 24
Peak memory 253956 kb
Host smart-97be5f7f-5202-4279-9aa0-3802b22402c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
6646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.284956646
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.347839574
Short name T656
Test name
Test status
Simulation time 102193771 ps
CPU time 13.65 seconds
Started Mar 14 02:08:55 PM PDT 24
Finished Mar 14 02:09:09 PM PDT 24
Peak memory 247524 kb
Host smart-877c7a7e-67b4-49f3-98cf-1c9c19c30fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34783
9574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.347839574
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1251791117
Short name T406
Test name
Test status
Simulation time 2792720584 ps
CPU time 61.86 seconds
Started Mar 14 02:08:47 PM PDT 24
Finished Mar 14 02:09:49 PM PDT 24
Peak memory 256512 kb
Host smart-cd5153fe-e131-498e-bfd5-cbd15d37803b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12517
91117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1251791117
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3585196097
Short name T435
Test name
Test status
Simulation time 5868951850 ps
CPU time 838.31 seconds
Started Mar 14 02:09:00 PM PDT 24
Finished Mar 14 02:22:58 PM PDT 24
Peak memory 269676 kb
Host smart-567f5938-6791-43da-9ab7-b08f5165f752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585196097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3585196097
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.340095651
Short name T689
Test name
Test status
Simulation time 2161232400 ps
CPU time 116.95 seconds
Started Mar 14 02:09:03 PM PDT 24
Finished Mar 14 02:11:01 PM PDT 24
Peak memory 256816 kb
Host smart-1343f3f8-c008-4f63-8197-62f99a633639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
5651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.340095651
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4078112432
Short name T378
Test name
Test status
Simulation time 518405043 ps
CPU time 26.93 seconds
Started Mar 14 02:08:59 PM PDT 24
Finished Mar 14 02:09:27 PM PDT 24
Peak memory 249308 kb
Host smart-e6b792b5-a714-47d9-ad61-f0ffad0218ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40781
12432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4078112432
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2882319239
Short name T321
Test name
Test status
Simulation time 14146306433 ps
CPU time 553.07 seconds
Started Mar 14 02:09:02 PM PDT 24
Finished Mar 14 02:18:16 PM PDT 24
Peak memory 265508 kb
Host smart-94c53056-3328-419f-b293-b66d970246ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882319239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2882319239
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.247793709
Short name T695
Test name
Test status
Simulation time 123360582807 ps
CPU time 2829 seconds
Started Mar 14 02:09:02 PM PDT 24
Finished Mar 14 02:56:13 PM PDT 24
Peak memory 281972 kb
Host smart-4830a82b-dc55-4ebd-8eeb-13f9ee63a690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247793709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.247793709
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3364012325
Short name T708
Test name
Test status
Simulation time 12428674576 ps
CPU time 135.6 seconds
Started Mar 14 02:08:59 PM PDT 24
Finished Mar 14 02:11:15 PM PDT 24
Peak memory 248532 kb
Host smart-f70bea77-78b9-48f1-93a1-140f7cfa100c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364012325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3364012325
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.703957338
Short name T631
Test name
Test status
Simulation time 298106083 ps
CPU time 18.28 seconds
Started Mar 14 02:09:04 PM PDT 24
Finished Mar 14 02:09:23 PM PDT 24
Peak memory 255540 kb
Host smart-1a0a24a3-46a3-4ac9-adab-1af4dd2df00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70395
7338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.703957338
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3907169857
Short name T428
Test name
Test status
Simulation time 861089484 ps
CPU time 58.43 seconds
Started Mar 14 02:08:59 PM PDT 24
Finished Mar 14 02:09:58 PM PDT 24
Peak memory 255148 kb
Host smart-aa3bcf3f-a70e-46e9-bf05-e78bd4e5c32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
69857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3907169857
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.873365006
Short name T557
Test name
Test status
Simulation time 922204452 ps
CPU time 26.04 seconds
Started Mar 14 02:09:03 PM PDT 24
Finished Mar 14 02:09:29 PM PDT 24
Peak memory 255272 kb
Host smart-92ac8927-4a8f-4156-9ac3-f7855b4cdbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87336
5006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.873365006
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1830676759
Short name T457
Test name
Test status
Simulation time 182791441 ps
CPU time 6.42 seconds
Started Mar 14 02:09:01 PM PDT 24
Finished Mar 14 02:09:07 PM PDT 24
Peak memory 249064 kb
Host smart-3ea9c611-ddd7-453c-8ce7-4c95dd410c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18306
76759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1830676759
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1622066080
Short name T268
Test name
Test status
Simulation time 131155543021 ps
CPU time 3167.91 seconds
Started Mar 14 02:09:01 PM PDT 24
Finished Mar 14 03:01:49 PM PDT 24
Peak memory 322764 kb
Host smart-5b442ba1-0e3d-465e-8d36-70317eec1dde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622066080 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1622066080
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3031711894
Short name T660
Test name
Test status
Simulation time 16636217930 ps
CPU time 1130.98 seconds
Started Mar 14 02:09:02 PM PDT 24
Finished Mar 14 02:27:55 PM PDT 24
Peak memory 285140 kb
Host smart-50fb43c9-715e-462c-a96d-cc5d7634b9a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031711894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3031711894
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.853274485
Short name T393
Test name
Test status
Simulation time 12993363371 ps
CPU time 218.35 seconds
Started Mar 14 02:09:00 PM PDT 24
Finished Mar 14 02:12:39 PM PDT 24
Peak memory 257148 kb
Host smart-51bc5222-999c-484e-be3e-9b45da67caa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85327
4485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.853274485
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3100547815
Short name T215
Test name
Test status
Simulation time 1255475976 ps
CPU time 43.68 seconds
Started Mar 14 02:09:01 PM PDT 24
Finished Mar 14 02:09:45 PM PDT 24
Peak memory 249120 kb
Host smart-f7a8c955-8427-4f1e-b156-f05ca5c2ee18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31005
47815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3100547815
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.560363943
Short name T325
Test name
Test status
Simulation time 20585132170 ps
CPU time 1342.97 seconds
Started Mar 14 02:09:04 PM PDT 24
Finished Mar 14 02:31:28 PM PDT 24
Peak memory 266612 kb
Host smart-b3ae7ae0-d900-42ae-8eff-8f9078a3e0e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560363943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.560363943
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3101970393
Short name T685
Test name
Test status
Simulation time 15983256667 ps
CPU time 1465.76 seconds
Started Mar 14 02:09:03 PM PDT 24
Finished Mar 14 02:33:30 PM PDT 24
Peak memory 288944 kb
Host smart-a963f5a9-302c-46cf-b7f5-70978f9ccde6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101970393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3101970393
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3923449584
Short name T480
Test name
Test status
Simulation time 862902328 ps
CPU time 36.44 seconds
Started Mar 14 02:09:03 PM PDT 24
Finished Mar 14 02:09:40 PM PDT 24
Peak memory 255888 kb
Host smart-13fea60f-2139-4811-92f7-79e73dcdd383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
49584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3923449584
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.288578834
Short name T643
Test name
Test status
Simulation time 488378703 ps
CPU time 18.56 seconds
Started Mar 14 02:09:00 PM PDT 24
Finished Mar 14 02:09:18 PM PDT 24
Peak memory 247648 kb
Host smart-6a71181b-2036-4864-a4c7-e9dc5e3ea86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28857
8834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.288578834
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2892799238
Short name T658
Test name
Test status
Simulation time 308414015 ps
CPU time 30.86 seconds
Started Mar 14 02:09:00 PM PDT 24
Finished Mar 14 02:09:31 PM PDT 24
Peak memory 247468 kb
Host smart-2c92686e-4907-4bd2-a4a8-6c3bfbb786ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927
99238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2892799238
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2898751659
Short name T414
Test name
Test status
Simulation time 1054202175 ps
CPU time 71.73 seconds
Started Mar 14 02:09:00 PM PDT 24
Finished Mar 14 02:10:12 PM PDT 24
Peak memory 249060 kb
Host smart-14ef8698-9a2f-4a2f-a5e0-2b7fbe5aadcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28987
51659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2898751659
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3424892876
Short name T270
Test name
Test status
Simulation time 209096581110 ps
CPU time 2929.48 seconds
Started Mar 14 02:09:21 PM PDT 24
Finished Mar 14 02:58:11 PM PDT 24
Peak memory 290000 kb
Host smart-4041b6fe-d1a8-46df-bd1c-88cfbd443f8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424892876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3424892876
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3064401723
Short name T395
Test name
Test status
Simulation time 8169354931 ps
CPU time 283.8 seconds
Started Mar 14 02:09:14 PM PDT 24
Finished Mar 14 02:13:58 PM PDT 24
Peak memory 251180 kb
Host smart-fed96f85-9ee0-457e-be72-24d1e6482434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30644
01723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3064401723
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.563125403
Short name T429
Test name
Test status
Simulation time 2474821779 ps
CPU time 41.07 seconds
Started Mar 14 02:09:18 PM PDT 24
Finished Mar 14 02:09:59 PM PDT 24
Peak memory 255944 kb
Host smart-a03462b6-23fc-45de-9f3a-ede8b5eadd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56312
5403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.563125403
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1433100668
Short name T282
Test name
Test status
Simulation time 197703539226 ps
CPU time 2938.03 seconds
Started Mar 14 02:09:16 PM PDT 24
Finished Mar 14 02:58:14 PM PDT 24
Peak memory 281972 kb
Host smart-dd05047e-a7ac-4fd1-99bb-485e5c7c807c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433100668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1433100668
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.611607798
Short name T69
Test name
Test status
Simulation time 11710283449 ps
CPU time 445.33 seconds
Started Mar 14 02:09:19 PM PDT 24
Finished Mar 14 02:16:44 PM PDT 24
Peak memory 248420 kb
Host smart-6a95c180-ae77-4224-b665-b4a60967773a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611607798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.611607798
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3813391575
Short name T447
Test name
Test status
Simulation time 1911636957 ps
CPU time 53.05 seconds
Started Mar 14 02:09:22 PM PDT 24
Finished Mar 14 02:10:15 PM PDT 24
Peak memory 249156 kb
Host smart-f774dcfb-a460-47ca-a3f2-aa9f64f00db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38133
91575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3813391575
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2424935479
Short name T107
Test name
Test status
Simulation time 4101432445 ps
CPU time 59.97 seconds
Started Mar 14 02:09:15 PM PDT 24
Finished Mar 14 02:10:15 PM PDT 24
Peak memory 249176 kb
Host smart-c9ea889a-b251-4b3a-8622-39740bfbe0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24249
35479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2424935479
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.5112837
Short name T20
Test name
Test status
Simulation time 3247323099 ps
CPU time 28.57 seconds
Started Mar 14 02:09:15 PM PDT 24
Finished Mar 14 02:09:43 PM PDT 24
Peak memory 248200 kb
Host smart-774c1022-30b2-402c-96d9-0c4afbfc734a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51128
37 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.5112837
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2247970226
Short name T633
Test name
Test status
Simulation time 6928183304 ps
CPU time 76.92 seconds
Started Mar 14 02:09:21 PM PDT 24
Finished Mar 14 02:10:38 PM PDT 24
Peak memory 249180 kb
Host smart-2faa0a7d-5026-4f1f-9113-6d69b38f7859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22479
70226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2247970226
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.596879104
Short name T81
Test name
Test status
Simulation time 246604857062 ps
CPU time 3448.27 seconds
Started Mar 14 02:09:21 PM PDT 24
Finished Mar 14 03:06:50 PM PDT 24
Peak memory 289648 kb
Host smart-e1678b27-24b8-49ce-b567-c3a90a2b28a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596879104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.596879104
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.332900515
Short name T255
Test name
Test status
Simulation time 136185698671 ps
CPU time 1622.23 seconds
Started Mar 14 02:09:14 PM PDT 24
Finished Mar 14 02:36:17 PM PDT 24
Peak memory 305812 kb
Host smart-41cb26a5-d9bd-42f0-9cf7-a8974258eeaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332900515 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.332900515
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2486068284
Short name T63
Test name
Test status
Simulation time 26549691460 ps
CPU time 1029.7 seconds
Started Mar 14 02:09:18 PM PDT 24
Finished Mar 14 02:26:28 PM PDT 24
Peak memory 286272 kb
Host smart-f3fbd98b-e839-41b0-af39-ba3e48c20604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486068284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2486068284
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3229563956
Short name T651
Test name
Test status
Simulation time 2152524175 ps
CPU time 46.94 seconds
Started Mar 14 02:09:18 PM PDT 24
Finished Mar 14 02:10:05 PM PDT 24
Peak memory 248976 kb
Host smart-0cd41019-3bdb-41d3-bcc7-08b9bc73c665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32295
63956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3229563956
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1194419686
Short name T562
Test name
Test status
Simulation time 239505237 ps
CPU time 9.23 seconds
Started Mar 14 02:09:21 PM PDT 24
Finished Mar 14 02:09:31 PM PDT 24
Peak memory 253308 kb
Host smart-35f6292e-6725-4db1-8bbc-1b2ea94e219f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11944
19686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1194419686
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4069663708
Short name T470
Test name
Test status
Simulation time 539505000098 ps
CPU time 1596.32 seconds
Started Mar 14 02:09:29 PM PDT 24
Finished Mar 14 02:36:05 PM PDT 24
Peak memory 267612 kb
Host smart-af40f497-8a59-47e0-8ec5-8810b507d0fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069663708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4069663708
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2938374007
Short name T292
Test name
Test status
Simulation time 9889159908 ps
CPU time 397.42 seconds
Started Mar 14 02:09:21 PM PDT 24
Finished Mar 14 02:15:59 PM PDT 24
Peak memory 248096 kb
Host smart-5884e266-bf1c-4c79-91ab-08f3f1a7552b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938374007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2938374007
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3449924521
Short name T392
Test name
Test status
Simulation time 326119934 ps
CPU time 18.06 seconds
Started Mar 14 02:09:19 PM PDT 24
Finished Mar 14 02:09:37 PM PDT 24
Peak memory 249092 kb
Host smart-3888bf1c-585b-4261-b5d5-d9e70ea21251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34499
24521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3449924521
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2657675778
Short name T640
Test name
Test status
Simulation time 5887856916 ps
CPU time 32.7 seconds
Started Mar 14 02:09:14 PM PDT 24
Finished Mar 14 02:09:47 PM PDT 24
Peak memory 248760 kb
Host smart-73e90de2-7e16-4f0a-8994-d1a7ba066f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26576
75778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2657675778
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3615343225
Short name T464
Test name
Test status
Simulation time 1419803004 ps
CPU time 29.03 seconds
Started Mar 14 02:09:16 PM PDT 24
Finished Mar 14 02:09:46 PM PDT 24
Peak memory 249084 kb
Host smart-80c72c5b-d0fe-40a1-b148-2d9a7c1dac52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36153
43225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3615343225
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3099390662
Short name T279
Test name
Test status
Simulation time 79021825210 ps
CPU time 1329.11 seconds
Started Mar 14 02:09:28 PM PDT 24
Finished Mar 14 02:31:37 PM PDT 24
Peak memory 290072 kb
Host smart-ef007e54-280c-4e96-a042-60497bf597bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099390662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3099390662
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3359233683
Short name T541
Test name
Test status
Simulation time 27732977807 ps
CPU time 1241.15 seconds
Started Mar 14 02:09:28 PM PDT 24
Finished Mar 14 02:30:10 PM PDT 24
Peak memory 281700 kb
Host smart-26a5bc38-dfc5-4f7b-8e9a-bd952e2d5b39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359233683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3359233683
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.812194967
Short name T513
Test name
Test status
Simulation time 6239003685 ps
CPU time 107.68 seconds
Started Mar 14 02:09:29 PM PDT 24
Finished Mar 14 02:11:17 PM PDT 24
Peak memory 256972 kb
Host smart-c794f1c8-33b8-4ae1-b0eb-0acda62f6ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81219
4967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.812194967
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2851329884
Short name T536
Test name
Test status
Simulation time 667714251 ps
CPU time 36.75 seconds
Started Mar 14 02:09:30 PM PDT 24
Finished Mar 14 02:10:07 PM PDT 24
Peak memory 249084 kb
Host smart-33b7b496-f880-40c9-9947-660edf4c1704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28513
29884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2851329884
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.77949191
Short name T469
Test name
Test status
Simulation time 609961413988 ps
CPU time 2472.34 seconds
Started Mar 14 02:09:30 PM PDT 24
Finished Mar 14 02:50:43 PM PDT 24
Peak memory 290100 kb
Host smart-b314e69b-fb94-44bb-86f0-abccb33989f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77949191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.77949191
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1441154750
Short name T296
Test name
Test status
Simulation time 12804843915 ps
CPU time 441.05 seconds
Started Mar 14 02:09:28 PM PDT 24
Finished Mar 14 02:16:49 PM PDT 24
Peak memory 248344 kb
Host smart-cdf45a67-97fb-49a7-9380-66a3b37a7fa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441154750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1441154750
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2221143948
Short name T482
Test name
Test status
Simulation time 38198082 ps
CPU time 4.08 seconds
Started Mar 14 02:09:29 PM PDT 24
Finished Mar 14 02:09:34 PM PDT 24
Peak memory 240872 kb
Host smart-b0eea8fc-0729-4621-a094-797eff32809d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22211
43948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2221143948
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.696332547
Short name T461
Test name
Test status
Simulation time 941288462 ps
CPU time 58.02 seconds
Started Mar 14 02:09:28 PM PDT 24
Finished Mar 14 02:10:27 PM PDT 24
Peak memory 256144 kb
Host smart-0c5b6499-fa06-4ff2-96fa-6a0f9a283b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69633
2547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.696332547
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.792116879
Short name T93
Test name
Test status
Simulation time 2134247355 ps
CPU time 42.5 seconds
Started Mar 14 02:09:30 PM PDT 24
Finished Mar 14 02:10:13 PM PDT 24
Peak memory 255612 kb
Host smart-910f72a1-b3b8-4d11-8cf8-4fd0935271b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79211
6879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.792116879
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.969762884
Short name T466
Test name
Test status
Simulation time 48812649 ps
CPU time 7.7 seconds
Started Mar 14 02:09:28 PM PDT 24
Finished Mar 14 02:09:36 PM PDT 24
Peak memory 249156 kb
Host smart-82c5f31f-36ca-466e-84bd-8bb6d9dad429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96976
2884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.969762884
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2225214369
Short name T100
Test name
Test status
Simulation time 31094753564 ps
CPU time 807.67 seconds
Started Mar 14 02:09:31 PM PDT 24
Finished Mar 14 02:22:59 PM PDT 24
Peak memory 271932 kb
Host smart-f73755bb-5d25-46c4-a982-e978ca43430e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225214369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2225214369
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2484179584
Short name T225
Test name
Test status
Simulation time 19208313614 ps
CPU time 1109.87 seconds
Started Mar 14 02:09:29 PM PDT 24
Finished Mar 14 02:27:59 PM PDT 24
Peak memory 266688 kb
Host smart-a6453e37-8e57-4db9-b6f6-751774738c21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484179584 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2484179584
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2331379474
Short name T650
Test name
Test status
Simulation time 49077927471 ps
CPU time 1346.2 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:32:04 PM PDT 24
Peak memory 289496 kb
Host smart-0580c176-d518-4041-967b-a4c793c545e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331379474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2331379474
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2552137692
Short name T702
Test name
Test status
Simulation time 3612248448 ps
CPU time 66.14 seconds
Started Mar 14 02:09:35 PM PDT 24
Finished Mar 14 02:10:42 PM PDT 24
Peak memory 256864 kb
Host smart-b25ee09e-0922-40f0-8624-8ca481d6f716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25521
37692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2552137692
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.502261676
Short name T422
Test name
Test status
Simulation time 824450198 ps
CPU time 58.29 seconds
Started Mar 14 02:09:36 PM PDT 24
Finished Mar 14 02:10:35 PM PDT 24
Peak memory 255188 kb
Host smart-76ddc964-e7d9-429f-9fd1-cf9a2ddfa321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50226
1676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.502261676
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1776154939
Short name T326
Test name
Test status
Simulation time 38170229525 ps
CPU time 2061.73 seconds
Started Mar 14 02:09:34 PM PDT 24
Finished Mar 14 02:43:56 PM PDT 24
Peak memory 281972 kb
Host smart-e87dfda7-cafc-4ddd-b7ea-aa97590267c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776154939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1776154939
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1103180441
Short name T687
Test name
Test status
Simulation time 45199383328 ps
CPU time 831.83 seconds
Started Mar 14 02:09:38 PM PDT 24
Finished Mar 14 02:23:31 PM PDT 24
Peak memory 268788 kb
Host smart-24dac53b-69b8-4a54-b3d2-6eb82db783e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103180441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1103180441
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3278843322
Short name T645
Test name
Test status
Simulation time 16004933278 ps
CPU time 166.41 seconds
Started Mar 14 02:09:34 PM PDT 24
Finished Mar 14 02:12:21 PM PDT 24
Peak memory 254376 kb
Host smart-3a0e52b1-ea49-4c26-9476-0819d463d406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278843322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3278843322
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.804939139
Short name T211
Test name
Test status
Simulation time 1407136406 ps
CPU time 23.93 seconds
Started Mar 14 02:09:27 PM PDT 24
Finished Mar 14 02:09:51 PM PDT 24
Peak memory 256220 kb
Host smart-9928f555-571a-4d4f-99dc-8bb6c70c4fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80493
9139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.804939139
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1793644392
Short name T49
Test name
Test status
Simulation time 796731845 ps
CPU time 41.72 seconds
Started Mar 14 02:09:28 PM PDT 24
Finished Mar 14 02:10:10 PM PDT 24
Peak memory 256816 kb
Host smart-85c2a1bb-87ab-4fdf-8811-ce6cadc91325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
44392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1793644392
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.4247685811
Short name T550
Test name
Test status
Simulation time 461274429 ps
CPU time 29.33 seconds
Started Mar 14 02:09:34 PM PDT 24
Finished Mar 14 02:10:04 PM PDT 24
Peak memory 256080 kb
Host smart-4d96281e-fc10-4b15-805c-841fe8f747af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42476
85811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.4247685811
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3313067935
Short name T431
Test name
Test status
Simulation time 3876124407 ps
CPU time 29.85 seconds
Started Mar 14 02:09:29 PM PDT 24
Finished Mar 14 02:09:59 PM PDT 24
Peak memory 257380 kb
Host smart-0a4763f2-2d7e-4238-b0f9-fb623ddbd3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33130
67935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3313067935
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1701962160
Short name T80
Test name
Test status
Simulation time 178166158100 ps
CPU time 5623.22 seconds
Started Mar 14 02:09:36 PM PDT 24
Finished Mar 14 03:43:21 PM PDT 24
Peak memory 306352 kb
Host smart-b487c7b8-6541-4b26-98ef-7f2f5941206b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701962160 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1701962160
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1788967740
Short name T712
Test name
Test status
Simulation time 55358145606 ps
CPU time 2686.06 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:54:25 PM PDT 24
Peak memory 290088 kb
Host smart-d2f71b43-e0ac-4a74-97d2-d44d2fe536c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788967740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1788967740
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2461530219
Short name T699
Test name
Test status
Simulation time 4265398035 ps
CPU time 131.96 seconds
Started Mar 14 02:09:35 PM PDT 24
Finished Mar 14 02:11:47 PM PDT 24
Peak memory 257136 kb
Host smart-80e2d0be-7e0b-4166-94ac-a5f16b97a882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24615
30219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2461530219
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1878460207
Short name T452
Test name
Test status
Simulation time 110879534 ps
CPU time 8.16 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:09:47 PM PDT 24
Peak memory 249024 kb
Host smart-e6cbb659-60f3-4848-b4fe-5dc7ce977824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18784
60207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1878460207
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4096733319
Short name T308
Test name
Test status
Simulation time 173105084188 ps
CPU time 2586.46 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:52:44 PM PDT 24
Peak memory 282624 kb
Host smart-a4067dbc-08fa-42a1-97bf-c94686808fc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096733319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4096733319
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3810850028
Short name T680
Test name
Test status
Simulation time 48018310410 ps
CPU time 2775.06 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:55:54 PM PDT 24
Peak memory 286500 kb
Host smart-a13c5a6a-1d0b-42e5-8a24-79795e66dc7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810850028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3810850028
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1077065353
Short name T524
Test name
Test status
Simulation time 20704625957 ps
CPU time 417.76 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:16:37 PM PDT 24
Peak memory 247968 kb
Host smart-6f6bedd6-e030-4f18-99cd-76a086f10e7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077065353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1077065353
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3943240950
Short name T544
Test name
Test status
Simulation time 1704803465 ps
CPU time 21.55 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:09:58 PM PDT 24
Peak memory 249020 kb
Host smart-3bdfa40d-483d-4f4f-860b-59d5376d6ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39432
40950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3943240950
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2207333450
Short name T625
Test name
Test status
Simulation time 1311274325 ps
CPU time 35.29 seconds
Started Mar 14 02:09:34 PM PDT 24
Finished Mar 14 02:10:10 PM PDT 24
Peak memory 247768 kb
Host smart-c9daf357-a335-4258-90bd-716a79f9bf51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22073
33450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2207333450
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.741388722
Short name T383
Test name
Test status
Simulation time 947306901 ps
CPU time 61.81 seconds
Started Mar 14 02:09:35 PM PDT 24
Finished Mar 14 02:10:37 PM PDT 24
Peak memory 249096 kb
Host smart-b46aaea5-d734-4e0f-a954-edf2e5a8f1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74138
8722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.741388722
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1577990503
Short name T254
Test name
Test status
Simulation time 68301721853 ps
CPU time 1365.61 seconds
Started Mar 14 02:09:38 PM PDT 24
Finished Mar 14 02:32:26 PM PDT 24
Peak memory 290116 kb
Host smart-9a44c420-7638-4b5f-ad40-3631a34b438f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577990503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1577990503
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1452899448
Short name T710
Test name
Test status
Simulation time 242134469713 ps
CPU time 5154.95 seconds
Started Mar 14 02:09:34 PM PDT 24
Finished Mar 14 03:35:30 PM PDT 24
Peak memory 353268 kb
Host smart-b0144f90-9816-455f-8dab-2bd0c3563149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452899448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1452899448
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2506404398
Short name T500
Test name
Test status
Simulation time 11324230770 ps
CPU time 1244.48 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:30:45 PM PDT 24
Peak memory 289224 kb
Host smart-b1e2fb88-f290-4b2e-bb59-8ce34cd5e0e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506404398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2506404398
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.978619155
Short name T516
Test name
Test status
Simulation time 1119506926 ps
CPU time 75.68 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:11:16 PM PDT 24
Peak memory 256768 kb
Host smart-eb6230bd-c178-4c6e-b4d0-e59fb5db1217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97861
9155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.978619155
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1609100783
Short name T653
Test name
Test status
Simulation time 531702078 ps
CPU time 12.11 seconds
Started Mar 14 02:09:36 PM PDT 24
Finished Mar 14 02:09:49 PM PDT 24
Peak memory 255344 kb
Host smart-45d89743-5833-4087-8d35-458796da17cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16091
00783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1609100783
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.925403202
Short name T323
Test name
Test status
Simulation time 26086441548 ps
CPU time 692.34 seconds
Started Mar 14 02:10:02 PM PDT 24
Finished Mar 14 02:21:35 PM PDT 24
Peak memory 271456 kb
Host smart-6925f4bc-1cb0-4573-8136-e9c9643e73cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925403202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.925403202
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3269813499
Short name T39
Test name
Test status
Simulation time 158189882022 ps
CPU time 2203.13 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:46:44 PM PDT 24
Peak memory 282944 kb
Host smart-8bf6a7a2-4049-4557-a1b0-4c088caff745
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269813499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3269813499
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3417947532
Short name T549
Test name
Test status
Simulation time 19271237727 ps
CPU time 221.7 seconds
Started Mar 14 02:10:03 PM PDT 24
Finished Mar 14 02:13:44 PM PDT 24
Peak memory 255444 kb
Host smart-02f7be06-bb41-45cf-ba6d-088d7a4446d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417947532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3417947532
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2686747238
Short name T18
Test name
Test status
Simulation time 188519739 ps
CPU time 12.37 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:09:51 PM PDT 24
Peak memory 252756 kb
Host smart-ae6227fd-912a-4a9b-96fa-2ad85ccfecd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26867
47238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2686747238
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3176400931
Short name T616
Test name
Test status
Simulation time 1200244547 ps
CPU time 53.76 seconds
Started Mar 14 02:09:37 PM PDT 24
Finished Mar 14 02:10:32 PM PDT 24
Peak memory 255484 kb
Host smart-9969aa68-c217-4a71-9849-f44bfc12df81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
00931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3176400931
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.950156061
Short name T662
Test name
Test status
Simulation time 708060166 ps
CPU time 45.84 seconds
Started Mar 14 02:10:02 PM PDT 24
Finished Mar 14 02:10:48 PM PDT 24
Peak memory 256200 kb
Host smart-27e19f43-d663-463c-821a-e22b2de3fd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95015
6061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.950156061
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1522291276
Short name T657
Test name
Test status
Simulation time 116557491 ps
CPU time 10 seconds
Started Mar 14 02:09:34 PM PDT 24
Finished Mar 14 02:09:44 PM PDT 24
Peak memory 251160 kb
Host smart-123202ab-59a9-44cc-bc75-dde8876a6e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15222
91276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1522291276
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.342551755
Short name T375
Test name
Test status
Simulation time 2215803916 ps
CPU time 18.24 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:10:20 PM PDT 24
Peak memory 253764 kb
Host smart-ca1e05d9-be37-40d0-8972-088b06249ebe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342551755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.342551755
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.905474513
Short name T692
Test name
Test status
Simulation time 48337374328 ps
CPU time 1330.21 seconds
Started Mar 14 02:10:00 PM PDT 24
Finished Mar 14 02:32:10 PM PDT 24
Peak memory 267640 kb
Host smart-da4e718a-9d54-443e-97c8-bf8e842eaeed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905474513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.905474513
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.254957458
Short name T584
Test name
Test status
Simulation time 2493797285 ps
CPU time 53.9 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:10:55 PM PDT 24
Peak memory 257092 kb
Host smart-16fe2414-f88a-4250-bc3a-da6caaf6b361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25495
7458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.254957458
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3116579579
Short name T669
Test name
Test status
Simulation time 94917338 ps
CPU time 13.56 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:10:15 PM PDT 24
Peak memory 254796 kb
Host smart-76dc04be-32b2-41f2-89ab-6957c5241d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
79579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3116579579
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2222898656
Short name T324
Test name
Test status
Simulation time 51307538959 ps
CPU time 1321.97 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:32:03 PM PDT 24
Peak memory 265584 kb
Host smart-fb6fff92-0619-45ba-8d48-131e50758107
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222898656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2222898656
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.4255459012
Short name T705
Test name
Test status
Simulation time 864472184463 ps
CPU time 2520.98 seconds
Started Mar 14 02:10:02 PM PDT 24
Finished Mar 14 02:52:04 PM PDT 24
Peak memory 286436 kb
Host smart-a0b5550b-de72-4e84-ba60-9fba68f82d40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255459012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4255459012
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.181847038
Short name T105
Test name
Test status
Simulation time 39048534368 ps
CPU time 220.24 seconds
Started Mar 14 02:10:03 PM PDT 24
Finished Mar 14 02:13:43 PM PDT 24
Peak memory 248256 kb
Host smart-7552a278-8a5c-4bfb-a247-63b459ccb49e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181847038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.181847038
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2936542710
Short name T691
Test name
Test status
Simulation time 2080008290 ps
CPU time 61.9 seconds
Started Mar 14 02:10:03 PM PDT 24
Finished Mar 14 02:11:05 PM PDT 24
Peak memory 256236 kb
Host smart-ddbdb203-e785-43fe-9aa5-04131b50eff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29365
42710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2936542710
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1686855698
Short name T380
Test name
Test status
Simulation time 942714056 ps
CPU time 21.62 seconds
Started Mar 14 02:10:02 PM PDT 24
Finished Mar 14 02:10:24 PM PDT 24
Peak memory 254540 kb
Host smart-911b3965-e36b-4d54-a4cb-b3bf6660ea10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16868
55698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1686855698
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3408986051
Short name T476
Test name
Test status
Simulation time 464919189 ps
CPU time 25.66 seconds
Started Mar 14 02:10:01 PM PDT 24
Finished Mar 14 02:10:27 PM PDT 24
Peak memory 255980 kb
Host smart-72784012-2f72-44f8-b829-a79bc51a3b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
86051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3408986051
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1347886195
Short name T515
Test name
Test status
Simulation time 407540262 ps
CPU time 25.93 seconds
Started Mar 14 02:10:02 PM PDT 24
Finished Mar 14 02:10:28 PM PDT 24
Peak memory 249000 kb
Host smart-6f47c450-4298-4d7f-b246-2659c986690a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13478
86195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1347886195
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3056534463
Short name T247
Test name
Test status
Simulation time 188849122805 ps
CPU time 2305.73 seconds
Started Mar 14 02:10:02 PM PDT 24
Finished Mar 14 02:48:28 PM PDT 24
Peak memory 289320 kb
Host smart-246d16f1-506e-4f6f-a9bf-10400df40a24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056534463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3056534463
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1200617365
Short name T198
Test name
Test status
Simulation time 27312073 ps
CPU time 3.43 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:07:29 PM PDT 24
Peak memory 249244 kb
Host smart-47cbda8f-bb07-4b2f-9d68-89ea6af4aa34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1200617365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1200617365
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3955077144
Short name T632
Test name
Test status
Simulation time 147995756688 ps
CPU time 2892.83 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:55:38 PM PDT 24
Peak memory 287704 kb
Host smart-84176374-7e7f-4a0e-a38b-28ec9f2473a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955077144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3955077144
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1498185885
Short name T346
Test name
Test status
Simulation time 3033332440 ps
CPU time 30.85 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:07:55 PM PDT 24
Peak memory 240864 kb
Host smart-697b14de-af49-4d62-a400-19ae901c27f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1498185885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1498185885
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1701920199
Short name T514
Test name
Test status
Simulation time 4213550245 ps
CPU time 145.86 seconds
Started Mar 14 02:07:20 PM PDT 24
Finished Mar 14 02:09:46 PM PDT 24
Peak memory 257048 kb
Host smart-63e94a4e-8110-4b44-9d70-82617ff88f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
20199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1701920199
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1653519440
Short name T567
Test name
Test status
Simulation time 3016995904 ps
CPU time 53.8 seconds
Started Mar 14 02:07:18 PM PDT 24
Finished Mar 14 02:08:13 PM PDT 24
Peak memory 255868 kb
Host smart-96c34ee2-06e1-4e71-b34e-bdc25d9476f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16535
19440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1653519440
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.976691347
Short name T701
Test name
Test status
Simulation time 36991551266 ps
CPU time 1980.82 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:40:22 PM PDT 24
Peak memory 272908 kb
Host smart-5c65e7c4-0645-42c6-8eed-758930609cdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976691347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.976691347
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2504932354
Short name T360
Test name
Test status
Simulation time 55452798206 ps
CPU time 1967.09 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:40:08 PM PDT 24
Peak memory 273332 kb
Host smart-1468f04c-eac7-469e-aa14-c4a61fb70d1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504932354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2504932354
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2834850977
Short name T608
Test name
Test status
Simulation time 4961925997 ps
CPU time 211.84 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:10:54 PM PDT 24
Peak memory 253864 kb
Host smart-bdb5b7e5-69e0-4aa9-af45-186f38f7e936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834850977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2834850977
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4244267228
Short name T597
Test name
Test status
Simulation time 1520357514 ps
CPU time 29.93 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:07:52 PM PDT 24
Peak memory 249104 kb
Host smart-2c254dc9-2450-4155-82e5-47e688a3c5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42442
67228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4244267228
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2492451815
Short name T58
Test name
Test status
Simulation time 2755624608 ps
CPU time 21.45 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:07:47 PM PDT 24
Peak memory 254112 kb
Host smart-ee6a4869-82f6-4199-93d7-35cd120c2b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24924
51815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2492451815
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.359847585
Short name T11
Test name
Test status
Simulation time 356109353 ps
CPU time 10.29 seconds
Started Mar 14 02:07:22 PM PDT 24
Finished Mar 14 02:07:33 PM PDT 24
Peak memory 273836 kb
Host smart-06bbd16e-853f-4b8b-a526-752f3f89f8f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=359847585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.359847585
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3560406979
Short name T493
Test name
Test status
Simulation time 106645649 ps
CPU time 9.26 seconds
Started Mar 14 02:07:21 PM PDT 24
Finished Mar 14 02:07:30 PM PDT 24
Peak memory 252996 kb
Host smart-251802ea-414b-4009-bbdd-1f17db952408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35604
06979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3560406979
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2320583140
Short name T419
Test name
Test status
Simulation time 59066900 ps
CPU time 5.79 seconds
Started Mar 14 02:07:20 PM PDT 24
Finished Mar 14 02:07:26 PM PDT 24
Peak memory 240892 kb
Host smart-f065bd6e-cbf1-4ceb-b226-2a57ddb86afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
83140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2320583140
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.162750903
Short name T547
Test name
Test status
Simulation time 18659518726 ps
CPU time 1280.15 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:31:34 PM PDT 24
Peak memory 273756 kb
Host smart-a0546308-d42a-435c-8109-4ff1aded4f28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162750903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.162750903
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.624392269
Short name T231
Test name
Test status
Simulation time 2375685750 ps
CPU time 107.64 seconds
Started Mar 14 02:10:17 PM PDT 24
Finished Mar 14 02:12:05 PM PDT 24
Peak memory 256976 kb
Host smart-58b30b72-1d54-4ffb-9ea0-78d63dfff551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62439
2269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.624392269
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.485951278
Short name T561
Test name
Test status
Simulation time 427048303 ps
CPU time 26.61 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:10:40 PM PDT 24
Peak memory 249364 kb
Host smart-ba756e39-8cc0-4b74-b57b-32b47155a04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48595
1278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.485951278
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1769116428
Short name T331
Test name
Test status
Simulation time 41333953922 ps
CPU time 1043.72 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:27:37 PM PDT 24
Peak memory 268660 kb
Host smart-dce7fbc9-deed-4ac0-b6d3-b41723a41325
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769116428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1769116428
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.4037619567
Short name T556
Test name
Test status
Simulation time 21254828366 ps
CPU time 1172.15 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:29:48 PM PDT 24
Peak memory 269660 kb
Host smart-cd3ef8f9-01b5-4664-88ac-ac9495fd4e47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037619567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4037619567
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2307311543
Short name T302
Test name
Test status
Simulation time 41418043179 ps
CPU time 460.72 seconds
Started Mar 14 02:10:17 PM PDT 24
Finished Mar 14 02:17:57 PM PDT 24
Peak memory 248116 kb
Host smart-52697c25-74be-4354-bf59-ef6e7360982f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307311543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2307311543
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.91078451
Short name T505
Test name
Test status
Simulation time 551685498 ps
CPU time 34.16 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:10:51 PM PDT 24
Peak memory 256256 kb
Host smart-e24080b8-5f3b-46c7-8486-80ee15fc8ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91078
451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.91078451
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2730424601
Short name T53
Test name
Test status
Simulation time 709942708 ps
CPU time 18.77 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:10:35 PM PDT 24
Peak memory 254496 kb
Host smart-0049d147-e5f1-49a5-91d6-ff73e87a032e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27304
24601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2730424601
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3453633545
Short name T674
Test name
Test status
Simulation time 2395997341 ps
CPU time 38.2 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:10:51 PM PDT 24
Peak memory 249160 kb
Host smart-f08a15db-2d08-4531-b2b9-0b531096f3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34536
33545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3453633545
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4124064615
Short name T212
Test name
Test status
Simulation time 69776657 ps
CPU time 3.61 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:10:17 PM PDT 24
Peak memory 240880 kb
Host smart-d4744d23-28bb-4ce0-b710-d814acc176b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41240
64615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4124064615
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1320909918
Short name T97
Test name
Test status
Simulation time 37781490543 ps
CPU time 1678.52 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:38:12 PM PDT 24
Peak memory 289216 kb
Host smart-42bdcf6f-4440-42ba-bfbf-8b010dc69bc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320909918 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1320909918
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.651344652
Short name T94
Test name
Test status
Simulation time 71574627933 ps
CPU time 1369.92 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:33:06 PM PDT 24
Peak memory 289528 kb
Host smart-1b73199f-8da5-42a4-b100-9562eb3405c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651344652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.651344652
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3640579752
Short name T441
Test name
Test status
Simulation time 2624402780 ps
CPU time 116.26 seconds
Started Mar 14 02:10:05 PM PDT 24
Finished Mar 14 02:12:01 PM PDT 24
Peak memory 250212 kb
Host smart-30b167b1-d7e4-47c9-9588-8602f7e525be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405
79752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3640579752
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1701475840
Short name T377
Test name
Test status
Simulation time 166899202 ps
CPU time 2.95 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:10:16 PM PDT 24
Peak memory 239220 kb
Host smart-f88c5a08-3ec2-4771-9379-c7fc839bc1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17014
75840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1701475840
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.4293576993
Short name T521
Test name
Test status
Simulation time 15892024076 ps
CPU time 1348.13 seconds
Started Mar 14 02:10:14 PM PDT 24
Finished Mar 14 02:32:42 PM PDT 24
Peak memory 289968 kb
Host smart-88020fd1-451c-4802-88de-6da9fc3b303d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293576993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.4293576993
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.511776034
Short name T507
Test name
Test status
Simulation time 14487846836 ps
CPU time 640.3 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:20:55 PM PDT 24
Peak memory 269600 kb
Host smart-acc9f02f-9aa5-488a-88fd-7e4e29f429e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511776034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.511776034
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3100749594
Short name T353
Test name
Test status
Simulation time 182755388 ps
CPU time 22.8 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:10:38 PM PDT 24
Peak memory 255848 kb
Host smart-e90af9d4-9ba6-4eac-a8cb-493e198ef388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31007
49594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3100749594
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2230299528
Short name T637
Test name
Test status
Simulation time 125869382 ps
CPU time 14.82 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:10:31 PM PDT 24
Peak memory 249552 kb
Host smart-dfbef5a2-7142-4306-a18b-a0debbee318c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22302
99528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2230299528
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2505234419
Short name T240
Test name
Test status
Simulation time 345261948 ps
CPU time 9.41 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:10:25 PM PDT 24
Peak memory 247452 kb
Host smart-b38bd4bb-b885-4e84-98bc-cec117c0dde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25052
34419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2505234419
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1017112513
Short name T670
Test name
Test status
Simulation time 10285198660 ps
CPU time 68.08 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:11:24 PM PDT 24
Peak memory 249416 kb
Host smart-4f26075d-63e7-4a13-bcd6-31d37107ff0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10171
12513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1017112513
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1654979280
Short name T174
Test name
Test status
Simulation time 49563778691 ps
CPU time 2511.58 seconds
Started Mar 14 02:10:23 PM PDT 24
Finished Mar 14 02:52:15 PM PDT 24
Peak memory 289584 kb
Host smart-95876ebd-6686-44ec-ab34-21f4bb6c853f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654979280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1654979280
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2146111047
Short name T413
Test name
Test status
Simulation time 11407522123 ps
CPU time 166.52 seconds
Started Mar 14 02:10:16 PM PDT 24
Finished Mar 14 02:13:02 PM PDT 24
Peak memory 257364 kb
Host smart-b62906e5-57fc-4497-b01f-ec73838c668d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21461
11047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2146111047
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1416847245
Short name T3
Test name
Test status
Simulation time 1172263143 ps
CPU time 25.7 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:10:41 PM PDT 24
Peak memory 249068 kb
Host smart-e1152b05-acce-4cc7-9d7f-57de80ba41af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14168
47245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1416847245
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2645886795
Short name T704
Test name
Test status
Simulation time 21774992549 ps
CPU time 1524.29 seconds
Started Mar 14 02:10:21 PM PDT 24
Finished Mar 14 02:35:45 PM PDT 24
Peak memory 289136 kb
Host smart-0d035c44-c753-4fc7-904d-738edcddeedc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645886795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2645886795
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1404502378
Short name T603
Test name
Test status
Simulation time 6056344531 ps
CPU time 263.62 seconds
Started Mar 14 02:10:19 PM PDT 24
Finished Mar 14 02:14:43 PM PDT 24
Peak memory 247364 kb
Host smart-2f45208e-1d35-4a0d-99c6-becf6593ab14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404502378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1404502378
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1484322457
Short name T484
Test name
Test status
Simulation time 285138734 ps
CPU time 5.19 seconds
Started Mar 14 02:10:14 PM PDT 24
Finished Mar 14 02:10:20 PM PDT 24
Peak memory 250872 kb
Host smart-7eb19e3f-6811-4667-811a-c0f58c5c12fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14843
22457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1484322457
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4255077838
Short name T495
Test name
Test status
Simulation time 74322352 ps
CPU time 5.49 seconds
Started Mar 14 02:10:15 PM PDT 24
Finished Mar 14 02:10:21 PM PDT 24
Peak memory 240792 kb
Host smart-9a201d7a-f59d-4264-91e3-2ab81116ac05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550
77838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4255077838
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.721797901
Short name T511
Test name
Test status
Simulation time 121709761 ps
CPU time 7.92 seconds
Started Mar 14 02:10:19 PM PDT 24
Finished Mar 14 02:10:27 PM PDT 24
Peak memory 247544 kb
Host smart-cf5aa3bf-7ac7-4c89-aba8-c443720058a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72179
7901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.721797901
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2694829844
Short name T596
Test name
Test status
Simulation time 42297510 ps
CPU time 3.81 seconds
Started Mar 14 02:10:13 PM PDT 24
Finished Mar 14 02:10:17 PM PDT 24
Peak memory 240808 kb
Host smart-b9092f74-2a30-400b-8d9f-49bb96c8fc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
29844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2694829844
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1839768154
Short name T246
Test name
Test status
Simulation time 45654589712 ps
CPU time 1332.48 seconds
Started Mar 14 02:10:22 PM PDT 24
Finished Mar 14 02:32:35 PM PDT 24
Peak memory 290088 kb
Host smart-a0f2a30c-784e-4e46-9e79-012ba5fd38ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839768154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1839768154
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2809084225
Short name T28
Test name
Test status
Simulation time 214594055847 ps
CPU time 2233.45 seconds
Started Mar 14 02:10:20 PM PDT 24
Finished Mar 14 02:47:34 PM PDT 24
Peak memory 273080 kb
Host smart-5e8fc413-176f-4a30-b11d-1e5a5daed835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809084225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2809084225
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1324753358
Short name T686
Test name
Test status
Simulation time 4050969315 ps
CPU time 72.44 seconds
Started Mar 14 02:10:23 PM PDT 24
Finished Mar 14 02:11:35 PM PDT 24
Peak memory 249060 kb
Host smart-e157edd9-b057-4ab7-90c3-d3a0b0ffe484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
53358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1324753358
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1899886504
Short name T79
Test name
Test status
Simulation time 3012152021 ps
CPU time 50.31 seconds
Started Mar 14 02:10:25 PM PDT 24
Finished Mar 14 02:11:15 PM PDT 24
Peak memory 256416 kb
Host smart-d31c60b0-80e8-4e7a-aca9-48592b0d6994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18998
86504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1899886504
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2695728932
Short name T589
Test name
Test status
Simulation time 89797766554 ps
CPU time 925.52 seconds
Started Mar 14 02:10:19 PM PDT 24
Finished Mar 14 02:25:45 PM PDT 24
Peak memory 270584 kb
Host smart-735ff4d8-f2f2-4d4e-b2a0-4773c9a040d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695728932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2695728932
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.933178718
Short name T668
Test name
Test status
Simulation time 8986769696 ps
CPU time 725.69 seconds
Started Mar 14 02:10:25 PM PDT 24
Finished Mar 14 02:22:30 PM PDT 24
Peak memory 273748 kb
Host smart-88824875-465d-46d3-9034-80cd6dd22391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933178718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.933178718
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3626211236
Short name T313
Test name
Test status
Simulation time 11838222679 ps
CPU time 457.51 seconds
Started Mar 14 02:10:21 PM PDT 24
Finished Mar 14 02:17:59 PM PDT 24
Peak memory 248536 kb
Host smart-8e5669c9-c728-49f8-8fad-3f0564fe2425
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626211236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3626211236
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1800241604
Short name T595
Test name
Test status
Simulation time 464180328 ps
CPU time 34.42 seconds
Started Mar 14 02:10:25 PM PDT 24
Finished Mar 14 02:10:59 PM PDT 24
Peak memory 249080 kb
Host smart-0af6befa-8f3b-4283-bfab-9aceebb3a3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
41604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1800241604
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2264351536
Short name T604
Test name
Test status
Simulation time 811500815 ps
CPU time 47.08 seconds
Started Mar 14 02:10:22 PM PDT 24
Finished Mar 14 02:11:09 PM PDT 24
Peak memory 255816 kb
Host smart-551e8106-cf3d-441c-93b0-e73970cf6c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
51536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2264351536
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2526260710
Short name T491
Test name
Test status
Simulation time 133866748 ps
CPU time 10.53 seconds
Started Mar 14 02:10:22 PM PDT 24
Finished Mar 14 02:10:32 PM PDT 24
Peak memory 251120 kb
Host smart-7bfa36aa-5fee-4a91-9919-679a044ab0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25262
60710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2526260710
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3722185862
Short name T19
Test name
Test status
Simulation time 370998225 ps
CPU time 15.06 seconds
Started Mar 14 02:10:21 PM PDT 24
Finished Mar 14 02:10:36 PM PDT 24
Peak memory 249012 kb
Host smart-2e59faa4-872d-42e6-9481-d32c0d200d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37221
85862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3722185862
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1573727216
Short name T253
Test name
Test status
Simulation time 40998236666 ps
CPU time 2257.34 seconds
Started Mar 14 02:10:22 PM PDT 24
Finished Mar 14 02:47:59 PM PDT 24
Peak memory 289668 kb
Host smart-1dbce347-093f-42a1-bd77-f195db51df46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573727216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1573727216
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2842181420
Short name T277
Test name
Test status
Simulation time 22828412548 ps
CPU time 1407.87 seconds
Started Mar 14 02:10:37 PM PDT 24
Finished Mar 14 02:34:05 PM PDT 24
Peak memory 273356 kb
Host smart-7f8577ea-a95a-48a8-adb3-64a713bbc04a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842181420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2842181420
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3663033075
Short name T571
Test name
Test status
Simulation time 389275781 ps
CPU time 25.69 seconds
Started Mar 14 02:10:34 PM PDT 24
Finished Mar 14 02:10:59 PM PDT 24
Peak memory 256144 kb
Host smart-024c4ac4-51e6-494d-9f80-2f2b96fbae29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36630
33075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3663033075
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.4067703697
Short name T437
Test name
Test status
Simulation time 3336238694 ps
CPU time 56.45 seconds
Started Mar 14 02:10:34 PM PDT 24
Finished Mar 14 02:11:30 PM PDT 24
Peak memory 257356 kb
Host smart-2d7cfea6-c06b-4a43-8d38-baeed5eae868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40677
03697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4067703697
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3837207033
Short name T319
Test name
Test status
Simulation time 183009889171 ps
CPU time 2572.35 seconds
Started Mar 14 02:10:33 PM PDT 24
Finished Mar 14 02:53:25 PM PDT 24
Peak memory 283632 kb
Host smart-d9fb3a77-a368-46e8-bf53-838a48711ddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837207033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3837207033
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3934588809
Short name T403
Test name
Test status
Simulation time 101387539193 ps
CPU time 1252.94 seconds
Started Mar 14 02:10:33 PM PDT 24
Finished Mar 14 02:31:27 PM PDT 24
Peak memory 273104 kb
Host smart-a136ed20-5efb-4fb9-aeb3-bfc7e3def099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934588809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3934588809
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1833795294
Short name T713
Test name
Test status
Simulation time 126943820742 ps
CPU time 245.83 seconds
Started Mar 14 02:10:32 PM PDT 24
Finished Mar 14 02:14:38 PM PDT 24
Peak memory 248180 kb
Host smart-3e40f26d-16da-4bcf-873b-da4f85c9140f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833795294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1833795294
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3717581562
Short name T620
Test name
Test status
Simulation time 349927592 ps
CPU time 19.25 seconds
Started Mar 14 02:10:35 PM PDT 24
Finished Mar 14 02:10:55 PM PDT 24
Peak memory 249092 kb
Host smart-a4cc1288-5c40-4e59-b6b5-a42b0d1e680f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37175
81562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3717581562
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2408925341
Short name T43
Test name
Test status
Simulation time 2730358639 ps
CPU time 72.93 seconds
Started Mar 14 02:10:36 PM PDT 24
Finished Mar 14 02:11:49 PM PDT 24
Peak memory 257040 kb
Host smart-02e5f818-777c-474a-b5d8-3c9550fe9ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24089
25341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2408925341
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.282993264
Short name T606
Test name
Test status
Simulation time 461693629 ps
CPU time 18.83 seconds
Started Mar 14 02:10:37 PM PDT 24
Finished Mar 14 02:10:56 PM PDT 24
Peak memory 247300 kb
Host smart-08fbb760-ecb8-40c6-ae06-c1d4963d2c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28299
3264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.282993264
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2120448886
Short name T697
Test name
Test status
Simulation time 645101299 ps
CPU time 6.95 seconds
Started Mar 14 02:10:36 PM PDT 24
Finished Mar 14 02:10:43 PM PDT 24
Peak memory 249088 kb
Host smart-24be5cef-dd43-438e-9743-9a775db8d202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
48886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2120448886
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1320089203
Short name T570
Test name
Test status
Simulation time 1334534922 ps
CPU time 77.77 seconds
Started Mar 14 02:10:32 PM PDT 24
Finished Mar 14 02:11:50 PM PDT 24
Peak memory 255900 kb
Host smart-2e727ff5-3ed2-4710-a9a0-81142b6ddb32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320089203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1320089203
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1342594577
Short name T382
Test name
Test status
Simulation time 48883056663 ps
CPU time 2624.79 seconds
Started Mar 14 02:10:44 PM PDT 24
Finished Mar 14 02:54:29 PM PDT 24
Peak memory 289288 kb
Host smart-ad27bfe6-6d37-4785-a65d-7d4965122855
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342594577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1342594577
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4283447034
Short name T532
Test name
Test status
Simulation time 4380406972 ps
CPU time 287.1 seconds
Started Mar 14 02:10:44 PM PDT 24
Finished Mar 14 02:15:32 PM PDT 24
Peak memory 256512 kb
Host smart-12d848e6-7fb8-4917-b875-ab2107881616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834
47034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4283447034
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1520964702
Short name T397
Test name
Test status
Simulation time 622558389 ps
CPU time 17.71 seconds
Started Mar 14 02:10:33 PM PDT 24
Finished Mar 14 02:10:51 PM PDT 24
Peak memory 255808 kb
Host smart-065298c2-228e-4ada-8d9b-663134148c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15209
64702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1520964702
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2940201096
Short name T298
Test name
Test status
Simulation time 40922914002 ps
CPU time 1820.47 seconds
Started Mar 14 02:10:45 PM PDT 24
Finished Mar 14 02:41:06 PM PDT 24
Peak memory 289732 kb
Host smart-a01d4e8e-4756-41f0-bf42-75a17fae50af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940201096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2940201096
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3545735439
Short name T530
Test name
Test status
Simulation time 88793287862 ps
CPU time 1429.77 seconds
Started Mar 14 02:10:46 PM PDT 24
Finished Mar 14 02:34:37 PM PDT 24
Peak memory 273852 kb
Host smart-e4eabb52-e5e1-4209-8084-66287d64e36d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545735439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3545735439
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1764618588
Short name T675
Test name
Test status
Simulation time 46026648761 ps
CPU time 525.06 seconds
Started Mar 14 02:10:47 PM PDT 24
Finished Mar 14 02:19:32 PM PDT 24
Peak memory 248260 kb
Host smart-370e6681-eac5-4f5a-8183-175721952048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764618588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1764618588
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1160384281
Short name T352
Test name
Test status
Simulation time 855249242 ps
CPU time 32.59 seconds
Started Mar 14 02:10:35 PM PDT 24
Finished Mar 14 02:11:08 PM PDT 24
Peak memory 255868 kb
Host smart-d2037cc9-e45f-4ff5-a855-83dea78b858e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11603
84281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1160384281
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.50787838
Short name T559
Test name
Test status
Simulation time 186418081 ps
CPU time 22.7 seconds
Started Mar 14 02:10:32 PM PDT 24
Finished Mar 14 02:10:55 PM PDT 24
Peak memory 256228 kb
Host smart-aafc05ea-7221-40f4-b6a9-efe09f7c68e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50787
838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.50787838
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2191564363
Short name T636
Test name
Test status
Simulation time 500856491 ps
CPU time 34.3 seconds
Started Mar 14 02:10:46 PM PDT 24
Finished Mar 14 02:11:20 PM PDT 24
Peak memory 254908 kb
Host smart-40152273-4065-4c46-9b72-af00992fe034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
64363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2191564363
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2161151933
Short name T409
Test name
Test status
Simulation time 210713198 ps
CPU time 18.77 seconds
Started Mar 14 02:10:34 PM PDT 24
Finished Mar 14 02:10:53 PM PDT 24
Peak memory 256252 kb
Host smart-a52216a6-04fc-4a51-8af9-370215304eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21611
51933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2161151933
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2221156516
Short name T440
Test name
Test status
Simulation time 68159555118 ps
CPU time 1140.88 seconds
Started Mar 14 02:11:00 PM PDT 24
Finished Mar 14 02:30:01 PM PDT 24
Peak memory 265572 kb
Host smart-0287d486-f0de-4531-b677-6e5803cc8c53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221156516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2221156516
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.10019477
Short name T234
Test name
Test status
Simulation time 8387826572 ps
CPU time 275.66 seconds
Started Mar 14 02:10:45 PM PDT 24
Finished Mar 14 02:15:21 PM PDT 24
Peak memory 250208 kb
Host smart-7e2dea70-66fc-47b1-8d6b-49ed778c9830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019
477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.10019477
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1635033990
Short name T700
Test name
Test status
Simulation time 616093259 ps
CPU time 24.16 seconds
Started Mar 14 02:10:45 PM PDT 24
Finished Mar 14 02:11:10 PM PDT 24
Peak memory 255292 kb
Host smart-228d2c6c-86cf-485d-9523-e33a70b55ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16350
33990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1635033990
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.633301537
Short name T309
Test name
Test status
Simulation time 26059690118 ps
CPU time 1016.85 seconds
Started Mar 14 02:10:58 PM PDT 24
Finished Mar 14 02:27:56 PM PDT 24
Peak memory 272032 kb
Host smart-d3709374-a32c-4ae7-81f1-ad21e254c5eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633301537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.633301537
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1969495909
Short name T265
Test name
Test status
Simulation time 41164363250 ps
CPU time 984.73 seconds
Started Mar 14 02:10:57 PM PDT 24
Finished Mar 14 02:27:23 PM PDT 24
Peak memory 273176 kb
Host smart-a2fd03b5-3028-4797-962d-d79f91e96d6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969495909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1969495909
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.794271112
Short name T432
Test name
Test status
Simulation time 275099168 ps
CPU time 17.96 seconds
Started Mar 14 02:10:48 PM PDT 24
Finished Mar 14 02:11:06 PM PDT 24
Peak memory 248980 kb
Host smart-e1442184-54dd-4ea6-92b3-77af14aa56f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79427
1112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.794271112
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.385657987
Short name T575
Test name
Test status
Simulation time 1450939311 ps
CPU time 58.92 seconds
Started Mar 14 02:10:45 PM PDT 24
Finished Mar 14 02:11:44 PM PDT 24
Peak memory 248184 kb
Host smart-e7c2b68a-23ab-4591-a965-4b0d6c01e8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38565
7987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.385657987
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2246852981
Short name T250
Test name
Test status
Simulation time 854491903 ps
CPU time 32.1 seconds
Started Mar 14 02:10:48 PM PDT 24
Finished Mar 14 02:11:20 PM PDT 24
Peak memory 248980 kb
Host smart-c4fe49c6-0d34-4464-88ac-1bbaf3dab52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
52981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2246852981
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1586748108
Short name T384
Test name
Test status
Simulation time 441689537 ps
CPU time 12.23 seconds
Started Mar 14 02:10:46 PM PDT 24
Finished Mar 14 02:10:58 PM PDT 24
Peak memory 249120 kb
Host smart-ec0b247b-6eba-49d3-af4a-873d4442ba17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15867
48108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1586748108
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3540820669
Short name T475
Test name
Test status
Simulation time 167892238269 ps
CPU time 1465.81 seconds
Started Mar 14 02:11:00 PM PDT 24
Finished Mar 14 02:35:26 PM PDT 24
Peak memory 273748 kb
Host smart-1a6aae67-0351-4b4b-a438-962d992e5c8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540820669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3540820669
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2605662593
Short name T245
Test name
Test status
Simulation time 75675417472 ps
CPU time 4560.42 seconds
Started Mar 14 02:10:57 PM PDT 24
Finished Mar 14 03:26:58 PM PDT 24
Peak memory 306584 kb
Host smart-4b96c3bc-818b-4171-b9dc-d9ec4c4c9f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605662593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2605662593
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3017224588
Short name T14
Test name
Test status
Simulation time 76659463693 ps
CPU time 2367.02 seconds
Started Mar 14 02:11:01 PM PDT 24
Finished Mar 14 02:50:30 PM PDT 24
Peak memory 289712 kb
Host smart-2f227b37-1192-4dc6-848c-32e88f1ea7da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017224588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3017224588
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3944961655
Short name T471
Test name
Test status
Simulation time 548760148 ps
CPU time 29.7 seconds
Started Mar 14 02:11:00 PM PDT 24
Finished Mar 14 02:11:30 PM PDT 24
Peak memory 256308 kb
Host smart-06618ccf-64d0-46c8-8ba1-244c9d61ebb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39449
61655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3944961655
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3272142831
Short name T110
Test name
Test status
Simulation time 408094634 ps
CPU time 26.48 seconds
Started Mar 14 02:11:01 PM PDT 24
Finished Mar 14 02:11:29 PM PDT 24
Peak memory 254644 kb
Host smart-b432f256-2c64-438e-b0e7-0740617fc24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
42831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3272142831
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.681668953
Short name T548
Test name
Test status
Simulation time 131840413854 ps
CPU time 1830.39 seconds
Started Mar 14 02:10:59 PM PDT 24
Finished Mar 14 02:41:30 PM PDT 24
Peak memory 286008 kb
Host smart-a41a2a59-70f5-4953-81dd-71e20d305c54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681668953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.681668953
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.188725831
Short name T317
Test name
Test status
Simulation time 27017281827 ps
CPU time 290.79 seconds
Started Mar 14 02:10:59 PM PDT 24
Finished Mar 14 02:15:50 PM PDT 24
Peak memory 248028 kb
Host smart-55670fe0-9cde-431f-ae82-835a5e13b575
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188725831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.188725831
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1551589298
Short name T275
Test name
Test status
Simulation time 225818331 ps
CPU time 26.24 seconds
Started Mar 14 02:11:00 PM PDT 24
Finished Mar 14 02:11:26 PM PDT 24
Peak memory 247828 kb
Host smart-c46b093b-e342-47c3-a241-54b4e2d8d8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15515
89298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1551589298
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.198047903
Short name T257
Test name
Test status
Simulation time 1325958710 ps
CPU time 54.39 seconds
Started Mar 14 02:10:57 PM PDT 24
Finished Mar 14 02:11:52 PM PDT 24
Peak memory 247448 kb
Host smart-b2be56fe-a612-4719-9e8d-57d9a7aed7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19804
7903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.198047903
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.4042311951
Short name T462
Test name
Test status
Simulation time 874557195 ps
CPU time 55.64 seconds
Started Mar 14 02:10:58 PM PDT 24
Finished Mar 14 02:11:54 PM PDT 24
Peak memory 249396 kb
Host smart-8432a08f-8d7e-452a-aa0c-fe7a4de01550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40423
11951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.4042311951
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1293472471
Short name T463
Test name
Test status
Simulation time 301170355339 ps
CPU time 2515.84 seconds
Started Mar 14 02:11:12 PM PDT 24
Finished Mar 14 02:53:09 PM PDT 24
Peak memory 289420 kb
Host smart-8ecd3909-4461-422a-b393-c38805765bf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293472471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1293472471
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.51709537
Short name T518
Test name
Test status
Simulation time 1686242880 ps
CPU time 110.3 seconds
Started Mar 14 02:11:09 PM PDT 24
Finished Mar 14 02:13:00 PM PDT 24
Peak memory 256988 kb
Host smart-f39a4c93-46a5-4e95-8586-e94a1e36f16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51709
537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.51709537
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3972312455
Short name T276
Test name
Test status
Simulation time 1332188112 ps
CPU time 61.97 seconds
Started Mar 14 02:11:12 PM PDT 24
Finished Mar 14 02:12:15 PM PDT 24
Peak memory 255996 kb
Host smart-ff16a1be-286a-4023-82ed-902b6fd2611a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39723
12455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3972312455
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.903420435
Short name T8
Test name
Test status
Simulation time 89950183376 ps
CPU time 1600.28 seconds
Started Mar 14 02:11:10 PM PDT 24
Finished Mar 14 02:37:51 PM PDT 24
Peak memory 289496 kb
Host smart-15b2da34-3c71-4acf-849a-16e7aaceda73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903420435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.903420435
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2495404977
Short name T503
Test name
Test status
Simulation time 62626450801 ps
CPU time 1718.66 seconds
Started Mar 14 02:11:10 PM PDT 24
Finished Mar 14 02:39:50 PM PDT 24
Peak memory 273640 kb
Host smart-543b6914-8254-4f9e-8600-d05ce92d5ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495404977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2495404977
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3303734872
Short name T683
Test name
Test status
Simulation time 24585724962 ps
CPU time 241.08 seconds
Started Mar 14 02:11:12 PM PDT 24
Finished Mar 14 02:15:14 PM PDT 24
Peak memory 248408 kb
Host smart-3a76f7f1-0781-44f2-af54-00b0647766ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303734872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3303734872
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.865378753
Short name T379
Test name
Test status
Simulation time 76214260 ps
CPU time 8.2 seconds
Started Mar 14 02:11:15 PM PDT 24
Finished Mar 14 02:11:24 PM PDT 24
Peak memory 249060 kb
Host smart-a5c6807d-a001-438f-bc67-613b039d098c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86537
8753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.865378753
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3539854847
Short name T427
Test name
Test status
Simulation time 210195370 ps
CPU time 5.39 seconds
Started Mar 14 02:11:10 PM PDT 24
Finished Mar 14 02:11:15 PM PDT 24
Peak memory 239288 kb
Host smart-52520eb7-61ae-42fc-94dc-65a4eee9ac26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35398
54847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3539854847
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3494490281
Short name T65
Test name
Test status
Simulation time 171910320 ps
CPU time 21.76 seconds
Started Mar 14 02:11:11 PM PDT 24
Finished Mar 14 02:11:33 PM PDT 24
Peak memory 247744 kb
Host smart-5ac70afa-c2b7-4d22-848f-c4c90fa378b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34944
90281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3494490281
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.4103872890
Short name T535
Test name
Test status
Simulation time 275345373 ps
CPU time 27.76 seconds
Started Mar 14 02:11:12 PM PDT 24
Finished Mar 14 02:11:41 PM PDT 24
Peak memory 255888 kb
Host smart-8f453d42-1d85-4799-b4a5-4e41ad62acd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41038
72890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.4103872890
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4090845228
Short name T572
Test name
Test status
Simulation time 14028165999 ps
CPU time 1231.63 seconds
Started Mar 14 02:11:11 PM PDT 24
Finished Mar 14 02:31:43 PM PDT 24
Peak memory 289716 kb
Host smart-7cfe69a7-3824-4054-91d7-fc1b8244320e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090845228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4090845228
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4055873255
Short name T709
Test name
Test status
Simulation time 19129965518 ps
CPU time 1446.55 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:35:30 PM PDT 24
Peak memory 289548 kb
Host smart-ad96b70f-76aa-499e-b25a-3be55876a79e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055873255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4055873255
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.223037504
Short name T629
Test name
Test status
Simulation time 32739573360 ps
CPU time 128.17 seconds
Started Mar 14 02:11:13 PM PDT 24
Finished Mar 14 02:13:21 PM PDT 24
Peak memory 256776 kb
Host smart-c0c8a730-8c3e-43b5-b403-8aaae3741e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303
7504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.223037504
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2646958990
Short name T453
Test name
Test status
Simulation time 641583604 ps
CPU time 25.54 seconds
Started Mar 14 02:11:12 PM PDT 24
Finished Mar 14 02:11:38 PM PDT 24
Peak memory 249068 kb
Host smart-1957b211-0fb6-4d59-b4c3-3420d56c3a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
58990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2646958990
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1785185758
Short name T273
Test name
Test status
Simulation time 42203824595 ps
CPU time 1055.74 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:28:59 PM PDT 24
Peak memory 286908 kb
Host smart-0350deb9-759d-406e-bd3b-c6dbd91ca9b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785185758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1785185758
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1627080087
Short name T306
Test name
Test status
Simulation time 42127829390 ps
CPU time 419.41 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:18:23 PM PDT 24
Peak memory 248264 kb
Host smart-203fbf29-8386-4125-9722-c9a78b0628fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627080087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1627080087
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4248788752
Short name T663
Test name
Test status
Simulation time 2536158333 ps
CPU time 35.22 seconds
Started Mar 14 02:11:11 PM PDT 24
Finished Mar 14 02:11:47 PM PDT 24
Peak memory 256320 kb
Host smart-4e4a7817-3a98-4f13-81c2-e93a03cc7a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
88752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4248788752
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2562266038
Short name T16
Test name
Test status
Simulation time 448565729 ps
CPU time 26.37 seconds
Started Mar 14 02:11:11 PM PDT 24
Finished Mar 14 02:11:37 PM PDT 24
Peak memory 249276 kb
Host smart-f3490672-a6bd-44fc-a174-23003cb5e16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25622
66038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2562266038
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3122375438
Short name T404
Test name
Test status
Simulation time 5103191043 ps
CPU time 42.65 seconds
Started Mar 14 02:11:10 PM PDT 24
Finished Mar 14 02:11:53 PM PDT 24
Peak memory 247976 kb
Host smart-e13d4e1e-eeaa-467f-a82f-894d15861539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31223
75438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3122375438
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4271756013
Short name T354
Test name
Test status
Simulation time 920769418 ps
CPU time 53.06 seconds
Started Mar 14 02:11:09 PM PDT 24
Finished Mar 14 02:12:03 PM PDT 24
Peak memory 256120 kb
Host smart-3104ada2-620b-4631-9375-5936c93659b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
56013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4271756013
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.149712226
Short name T647
Test name
Test status
Simulation time 656052750 ps
CPU time 51.79 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:12:15 PM PDT 24
Peak memory 257208 kb
Host smart-2ad8b019-afc5-4e1a-8c09-9db23b9d9474
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149712226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.149712226
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.610987915
Short name T82
Test name
Test status
Simulation time 26830052973 ps
CPU time 2393.11 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:51:17 PM PDT 24
Peak memory 321252 kb
Host smart-f3025671-0beb-47b7-bb23-5f7e7b8c64a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610987915 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.610987915
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3615756119
Short name T202
Test name
Test status
Simulation time 81482731 ps
CPU time 3.28 seconds
Started Mar 14 02:07:37 PM PDT 24
Finished Mar 14 02:07:41 PM PDT 24
Peak memory 249276 kb
Host smart-12ff0ad2-514a-422e-8b79-d2a0f130ddaa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3615756119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3615756119
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.524563145
Short name T540
Test name
Test status
Simulation time 6932990780 ps
CPU time 869.06 seconds
Started Mar 14 02:07:40 PM PDT 24
Finished Mar 14 02:22:09 PM PDT 24
Peak memory 273296 kb
Host smart-f847b232-6188-4829-8c2f-613500a655fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524563145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.524563145
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1813069206
Short name T630
Test name
Test status
Simulation time 164484223 ps
CPU time 10.14 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:07:49 PM PDT 24
Peak memory 249076 kb
Host smart-0234fda5-19c1-4362-ba0c-fef23a80a520
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1813069206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1813069206
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.364794254
Short name T269
Test name
Test status
Simulation time 18163774775 ps
CPU time 168.8 seconds
Started Mar 14 02:07:41 PM PDT 24
Finished Mar 14 02:10:30 PM PDT 24
Peak memory 257024 kb
Host smart-6f2b02bf-2312-4a5c-b901-2a249e8150bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36479
4254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.364794254
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1112498337
Short name T176
Test name
Test status
Simulation time 404931900 ps
CPU time 33.72 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:08:12 PM PDT 24
Peak memory 249064 kb
Host smart-753a553a-19b5-48ed-ab40-71da4d0ff1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11124
98337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1112498337
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1670708038
Short name T288
Test name
Test status
Simulation time 13927432003 ps
CPU time 1143.56 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:26:42 PM PDT 24
Peak memory 285856 kb
Host smart-966d5254-5c48-4b1d-a122-790760acf2db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670708038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1670708038
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2400957871
Short name T35
Test name
Test status
Simulation time 35488228806 ps
CPU time 810.14 seconds
Started Mar 14 02:07:40 PM PDT 24
Finished Mar 14 02:21:10 PM PDT 24
Peak memory 273688 kb
Host smart-afefeabf-d314-401c-97e3-045796017754
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400957871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2400957871
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2820620385
Short name T297
Test name
Test status
Simulation time 20525759586 ps
CPU time 302.59 seconds
Started Mar 14 02:07:39 PM PDT 24
Finished Mar 14 02:12:42 PM PDT 24
Peak memory 248336 kb
Host smart-b87f6d03-1dd4-4768-b0ca-b63b43e7e86a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820620385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2820620385
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2755115671
Short name T481
Test name
Test status
Simulation time 4016050416 ps
CPU time 22.25 seconds
Started Mar 14 02:07:25 PM PDT 24
Finished Mar 14 02:07:47 PM PDT 24
Peak memory 255924 kb
Host smart-6fd58f19-cdc6-4bda-a135-6cf65ebbe923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27551
15671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2755115671
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3373591452
Short name T615
Test name
Test status
Simulation time 288252616 ps
CPU time 23.68 seconds
Started Mar 14 02:07:19 PM PDT 24
Finished Mar 14 02:07:43 PM PDT 24
Peak memory 247896 kb
Host smart-192bcf7f-736d-449c-a60c-7632ebce8753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33735
91452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3373591452
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.359570002
Short name T399
Test name
Test status
Simulation time 4568999068 ps
CPU time 54.15 seconds
Started Mar 14 02:07:40 PM PDT 24
Finished Mar 14 02:08:34 PM PDT 24
Peak memory 249176 kb
Host smart-144fe8f0-4e6d-4dbe-87fc-de5164327c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35957
0002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.359570002
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1043657407
Short name T363
Test name
Test status
Simulation time 243757630 ps
CPU time 9.71 seconds
Started Mar 14 02:07:24 PM PDT 24
Finished Mar 14 02:07:34 PM PDT 24
Peak memory 248972 kb
Host smart-837f9f24-0a14-414e-9655-09b7565430e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436
57407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1043657407
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3428603835
Short name T522
Test name
Test status
Simulation time 93549143510 ps
CPU time 2745.32 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:53:23 PM PDT 24
Peak memory 297952 kb
Host smart-7e18c547-a447-485a-b7bb-3fa111c1433d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428603835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3428603835
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1091911110
Short name T64
Test name
Test status
Simulation time 18027929564 ps
CPU time 1125.14 seconds
Started Mar 14 02:11:24 PM PDT 24
Finished Mar 14 02:30:09 PM PDT 24
Peak memory 272332 kb
Host smart-c3f4c701-b364-4b89-9260-f0ab95dd847a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091911110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1091911110
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.660178325
Short name T628
Test name
Test status
Simulation time 4262322599 ps
CPU time 129.27 seconds
Started Mar 14 02:11:26 PM PDT 24
Finished Mar 14 02:13:36 PM PDT 24
Peak memory 257348 kb
Host smart-0b0ee0ae-06cc-41f9-a092-38bc955e4425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66017
8325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.660178325
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.703655289
Short name T362
Test name
Test status
Simulation time 239695207 ps
CPU time 9.09 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:11:32 PM PDT 24
Peak memory 249156 kb
Host smart-3cae31ef-67af-4bf3-851c-6cc4280a1f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70365
5289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.703655289
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2070042394
Short name T327
Test name
Test status
Simulation time 312580461524 ps
CPU time 1282.67 seconds
Started Mar 14 02:11:22 PM PDT 24
Finished Mar 14 02:32:45 PM PDT 24
Peak memory 289288 kb
Host smart-b3394933-94be-42e3-9dc3-1dd9d98f5da8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070042394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2070042394
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.424803221
Short name T29
Test name
Test status
Simulation time 77803649341 ps
CPU time 920.22 seconds
Started Mar 14 02:11:25 PM PDT 24
Finished Mar 14 02:26:45 PM PDT 24
Peak memory 272012 kb
Host smart-e313fb4d-0afb-474f-85b8-71e217767942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424803221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.424803221
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2286297990
Short name T703
Test name
Test status
Simulation time 20708488851 ps
CPU time 496.79 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:19:40 PM PDT 24
Peak memory 248108 kb
Host smart-6381486e-03fe-4e13-91e3-47ae6af6a409
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286297990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2286297990
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.356376839
Short name T361
Test name
Test status
Simulation time 2277352324 ps
CPU time 22.3 seconds
Started Mar 14 02:11:21 PM PDT 24
Finished Mar 14 02:11:44 PM PDT 24
Peak memory 249424 kb
Host smart-c881a577-4819-45d4-b52c-e0ea103a1bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35637
6839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.356376839
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3264438253
Short name T280
Test name
Test status
Simulation time 5371432065 ps
CPU time 61.56 seconds
Started Mar 14 02:11:24 PM PDT 24
Finished Mar 14 02:12:25 PM PDT 24
Peak memory 256892 kb
Host smart-fe01f1c8-312b-4702-8564-31dd088f050c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32644
38253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3264438253
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2640578121
Short name T204
Test name
Test status
Simulation time 272502150 ps
CPU time 21.13 seconds
Started Mar 14 02:11:25 PM PDT 24
Finished Mar 14 02:11:46 PM PDT 24
Peak memory 247592 kb
Host smart-56c8dc7e-502c-4cac-bf7a-f07320d5b859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
78121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2640578121
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1202504935
Short name T381
Test name
Test status
Simulation time 127571535 ps
CPU time 9.15 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:11:32 PM PDT 24
Peak memory 251184 kb
Host smart-eb51f1ba-97de-424b-aaf2-744868798479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12025
04935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1202504935
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3816985520
Short name T517
Test name
Test status
Simulation time 16537545009 ps
CPU time 1262.03 seconds
Started Mar 14 02:11:23 PM PDT 24
Finished Mar 14 02:32:25 PM PDT 24
Peak memory 289340 kb
Host smart-0734e681-1732-4321-82d4-f8aaeb05dc34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816985520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3816985520
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.662947577
Short name T233
Test name
Test status
Simulation time 199911846745 ps
CPU time 5304.48 seconds
Started Mar 14 02:11:22 PM PDT 24
Finished Mar 14 03:39:48 PM PDT 24
Peak memory 355180 kb
Host smart-e742f682-9791-4be4-a6b8-93d39b4d0b18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662947577 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.662947577
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3871016945
Short name T221
Test name
Test status
Simulation time 31698232952 ps
CPU time 1667.84 seconds
Started Mar 14 02:11:37 PM PDT 24
Finished Mar 14 02:39:25 PM PDT 24
Peak memory 267584 kb
Host smart-c4db4cb6-9a81-41c9-bc27-4564e269eb41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871016945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3871016945
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2494850157
Short name T367
Test name
Test status
Simulation time 255052786 ps
CPU time 9.86 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:11:45 PM PDT 24
Peak memory 253768 kb
Host smart-5c50480e-ec72-4c0e-8968-3f5eb32d7183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24948
50157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2494850157
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.749961387
Short name T672
Test name
Test status
Simulation time 299388294 ps
CPU time 27.2 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:12:02 PM PDT 24
Peak memory 255028 kb
Host smart-60e328af-f0b9-4ccd-8796-51701518cc14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74996
1387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.749961387
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.617168402
Short name T89
Test name
Test status
Simulation time 26534353952 ps
CPU time 1186.48 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:31:22 PM PDT 24
Peak memory 282644 kb
Host smart-7b15e65d-cb59-48dc-9097-128ff35daa0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617168402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.617168402
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3240684878
Short name T407
Test name
Test status
Simulation time 177150130058 ps
CPU time 2188.88 seconds
Started Mar 14 02:11:34 PM PDT 24
Finished Mar 14 02:48:04 PM PDT 24
Peak memory 289908 kb
Host smart-96cd99e7-1995-414e-9da0-6a23c2a5ba85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240684878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3240684878
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.751065151
Short name T291
Test name
Test status
Simulation time 215782490775 ps
CPU time 475.57 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:19:31 PM PDT 24
Peak memory 247956 kb
Host smart-215f270b-fe63-4fd3-a74d-5315d960c0e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751065151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.751065151
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1169385234
Short name T509
Test name
Test status
Simulation time 2200200495 ps
CPU time 19.56 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:11:55 PM PDT 24
Peak memory 249072 kb
Host smart-562095f1-8976-4c72-9fcd-203421a8c939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693
85234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1169385234
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2108772959
Short name T390
Test name
Test status
Simulation time 162986542 ps
CPU time 17.61 seconds
Started Mar 14 02:11:36 PM PDT 24
Finished Mar 14 02:11:54 PM PDT 24
Peak memory 248848 kb
Host smart-a22b3adc-791d-4764-ba41-7f0df299577a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21087
72959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2108772959
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1690091134
Short name T473
Test name
Test status
Simulation time 1643275529 ps
CPU time 65.13 seconds
Started Mar 14 02:11:37 PM PDT 24
Finished Mar 14 02:12:42 PM PDT 24
Peak memory 257188 kb
Host smart-47c64007-1a6e-416e-9e6b-45422c4051e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900
91134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1690091134
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2696189480
Short name T266
Test name
Test status
Simulation time 24709395257 ps
CPU time 1814.04 seconds
Started Mar 14 02:11:37 PM PDT 24
Finished Mar 14 02:41:52 PM PDT 24
Peak memory 304396 kb
Host smart-a653f25d-ced9-44e8-943c-362b6ff28215
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696189480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2696189480
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1258296950
Short name T103
Test name
Test status
Simulation time 161749890377 ps
CPU time 2686.03 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:56:21 PM PDT 24
Peak memory 298456 kb
Host smart-d0cb8bd3-0eed-4d0c-a317-36bbbcf5537d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258296950 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1258296950
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2698692632
Short name T483
Test name
Test status
Simulation time 23855767687 ps
CPU time 1582.75 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:37:58 PM PDT 24
Peak memory 270716 kb
Host smart-777e1407-24e5-4a0c-9219-deb00d960a13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698692632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2698692632
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1042063526
Short name T376
Test name
Test status
Simulation time 3749749136 ps
CPU time 60.63 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:12:35 PM PDT 24
Peak memory 256580 kb
Host smart-afadb6cc-e43a-4d9a-ac9a-d0a9f5c24e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10420
63526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1042063526
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.97143289
Short name T627
Test name
Test status
Simulation time 4730933203 ps
CPU time 48.21 seconds
Started Mar 14 02:11:35 PM PDT 24
Finished Mar 14 02:12:24 PM PDT 24
Peak memory 249108 kb
Host smart-ba45e9ae-58dc-4741-9e47-1591b85acaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97143
289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.97143289
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4219673369
Short name T289
Test name
Test status
Simulation time 80155311556 ps
CPU time 1322.56 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 02:33:48 PM PDT 24
Peak memory 273472 kb
Host smart-57f03f4d-7f8e-49df-9b97-a7de72998b71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219673369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4219673369
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.621281799
Short name T33
Test name
Test status
Simulation time 50718741528 ps
CPU time 2946.86 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 03:00:52 PM PDT 24
Peak memory 281972 kb
Host smart-03d72d2b-e6c1-4573-ab6b-c2c8f26a84ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621281799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.621281799
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.371378101
Short name T310
Test name
Test status
Simulation time 13762467126 ps
CPU time 549.51 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 02:20:55 PM PDT 24
Peak memory 249188 kb
Host smart-7e63a8ac-b9f0-4b04-8d2c-2f10e671aceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371378101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.371378101
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4153006655
Short name T574
Test name
Test status
Simulation time 266115296 ps
CPU time 35.64 seconds
Started Mar 14 02:11:36 PM PDT 24
Finished Mar 14 02:12:11 PM PDT 24
Peak memory 249152 kb
Host smart-bd5296e7-926e-48e2-a920-5b88b3014cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
06655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4153006655
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.852767930
Short name T504
Test name
Test status
Simulation time 594277920 ps
CPU time 46.32 seconds
Started Mar 14 02:11:36 PM PDT 24
Finished Mar 14 02:12:23 PM PDT 24
Peak memory 255552 kb
Host smart-549ca27d-2e54-457d-a643-c184ecd95a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85276
7930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.852767930
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.839213625
Short name T436
Test name
Test status
Simulation time 510703551 ps
CPU time 36.67 seconds
Started Mar 14 02:11:37 PM PDT 24
Finished Mar 14 02:12:14 PM PDT 24
Peak memory 255868 kb
Host smart-3a846838-4200-4568-b73c-1de816d2670a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83921
3625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.839213625
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.569391920
Short name T593
Test name
Test status
Simulation time 1751010635 ps
CPU time 75.3 seconds
Started Mar 14 02:11:34 PM PDT 24
Finished Mar 14 02:12:50 PM PDT 24
Peak memory 249172 kb
Host smart-f385a583-9626-468b-970e-f73d272fb1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56939
1920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.569391920
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3435061344
Short name T258
Test name
Test status
Simulation time 285962472995 ps
CPU time 2152.19 seconds
Started Mar 14 02:11:46 PM PDT 24
Finished Mar 14 02:47:39 PM PDT 24
Peak memory 289372 kb
Host smart-1af04b97-c5af-4d54-be84-6b2dd4dd5e4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435061344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3435061344
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1076591215
Short name T529
Test name
Test status
Simulation time 210734127201 ps
CPU time 4447.36 seconds
Started Mar 14 02:11:46 PM PDT 24
Finished Mar 14 03:25:54 PM PDT 24
Peak memory 355384 kb
Host smart-ffb986f5-09dc-4ce3-8560-684ccaf5ed74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076591215 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1076591215
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1684832485
Short name T27
Test name
Test status
Simulation time 277174855722 ps
CPU time 2557.33 seconds
Started Mar 14 02:11:46 PM PDT 24
Finished Mar 14 02:54:24 PM PDT 24
Peak memory 289412 kb
Host smart-ccdac3df-e247-4ffa-8b7b-bc16d9b0b4a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684832485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1684832485
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.85871121
Short name T40
Test name
Test status
Simulation time 12431585610 ps
CPU time 194.76 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 02:15:00 PM PDT 24
Peak memory 250528 kb
Host smart-6fff1eaa-0092-4d1f-ac55-18b9ae833177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85871
121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.85871121
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3655936150
Short name T639
Test name
Test status
Simulation time 268129462 ps
CPU time 31.35 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 02:12:16 PM PDT 24
Peak memory 249240 kb
Host smart-481acb4a-c1b2-45f4-93aa-d80156b8d13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36559
36150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3655936150
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3292926398
Short name T314
Test name
Test status
Simulation time 7401648582 ps
CPU time 756.89 seconds
Started Mar 14 02:12:04 PM PDT 24
Finished Mar 14 02:24:41 PM PDT 24
Peak memory 272572 kb
Host smart-0855e0a1-eae5-4a57-9672-a5c641943a09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292926398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3292926398
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4191498738
Short name T492
Test name
Test status
Simulation time 18179851983 ps
CPU time 1338.17 seconds
Started Mar 14 02:12:05 PM PDT 24
Finished Mar 14 02:34:24 PM PDT 24
Peak memory 273188 kb
Host smart-c126cc63-1502-4281-9fe2-4dd910410a5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191498738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4191498738
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.262547015
Short name T175
Test name
Test status
Simulation time 204986820 ps
CPU time 9.42 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 02:11:55 PM PDT 24
Peak memory 253320 kb
Host smart-9d275da6-fabf-428f-bf21-7474e9848b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26254
7015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.262547015
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3740461446
Short name T426
Test name
Test status
Simulation time 528044805 ps
CPU time 37.98 seconds
Started Mar 14 02:11:47 PM PDT 24
Finished Mar 14 02:12:25 PM PDT 24
Peak memory 255116 kb
Host smart-bd52b3a3-8b41-4d10-806a-ce1ad364af04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37404
61446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3740461446
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3431786420
Short name T70
Test name
Test status
Simulation time 978171682 ps
CPU time 63.06 seconds
Started Mar 14 02:11:45 PM PDT 24
Finished Mar 14 02:12:49 PM PDT 24
Peak memory 249056 kb
Host smart-66c129ef-8c58-4b51-9d85-d4d7b95655cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34317
86420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3431786420
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1548379632
Short name T46
Test name
Test status
Simulation time 685255259 ps
CPU time 15.74 seconds
Started Mar 14 02:11:47 PM PDT 24
Finished Mar 14 02:12:03 PM PDT 24
Peak memory 249080 kb
Host smart-4a672ff4-0db3-4b23-b10b-d1082caa9d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15483
79632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1548379632
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1340144875
Short name T216
Test name
Test status
Simulation time 6132345318 ps
CPU time 101.12 seconds
Started Mar 14 02:12:03 PM PDT 24
Finished Mar 14 02:13:44 PM PDT 24
Peak memory 257288 kb
Host smart-aced9871-0f14-492c-a338-6f275b5133d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340144875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1340144875
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.806929306
Short name T51
Test name
Test status
Simulation time 21283912832 ps
CPU time 1881.11 seconds
Started Mar 14 02:12:05 PM PDT 24
Finished Mar 14 02:43:27 PM PDT 24
Peak memory 289632 kb
Host smart-b4eb31f3-c02d-4ff4-8073-d70d41f84762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806929306 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.806929306
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1821398303
Short name T564
Test name
Test status
Simulation time 18827222132 ps
CPU time 1264.33 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:33:24 PM PDT 24
Peak memory 265640 kb
Host smart-f3026a15-ef26-4c72-9e5f-604e32aa7bf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821398303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1821398303
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.354913958
Short name T617
Test name
Test status
Simulation time 2784127340 ps
CPU time 31.04 seconds
Started Mar 14 02:12:04 PM PDT 24
Finished Mar 14 02:12:35 PM PDT 24
Peak memory 256412 kb
Host smart-5f192e2f-f77f-479e-81c2-e562c805e3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35491
3958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.354913958
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2804389037
Short name T605
Test name
Test status
Simulation time 78039005 ps
CPU time 8.39 seconds
Started Mar 14 02:12:04 PM PDT 24
Finished Mar 14 02:12:12 PM PDT 24
Peak memory 254096 kb
Host smart-95c74d40-1eea-4498-aec4-644498dab758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043
89037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2804389037
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2497196552
Short name T312
Test name
Test status
Simulation time 13171295486 ps
CPU time 1022.81 seconds
Started Mar 14 02:12:18 PM PDT 24
Finished Mar 14 02:29:23 PM PDT 24
Peak memory 272832 kb
Host smart-838cef3c-8695-47b0-a74d-7e555cdef80c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497196552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2497196552
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2924432879
Short name T646
Test name
Test status
Simulation time 108973159633 ps
CPU time 1758.69 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:41:41 PM PDT 24
Peak memory 273704 kb
Host smart-12c3bd4d-c08b-471b-bf9b-ce3ee841a075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924432879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2924432879
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1000316586
Short name T294
Test name
Test status
Simulation time 15050506195 ps
CPU time 233.23 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:16:15 PM PDT 24
Peak memory 255452 kb
Host smart-9cf30bae-fad2-4354-ab29-37c8495cf158
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000316586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1000316586
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2627735793
Short name T566
Test name
Test status
Simulation time 785643527 ps
CPU time 39.73 seconds
Started Mar 14 02:12:04 PM PDT 24
Finished Mar 14 02:12:44 PM PDT 24
Peak memory 249068 kb
Host smart-1e7e3e9c-e36e-4950-881d-ac661dd6f6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
35793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2627735793
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1594576275
Short name T359
Test name
Test status
Simulation time 151630899 ps
CPU time 12.71 seconds
Started Mar 14 02:12:03 PM PDT 24
Finished Mar 14 02:12:16 PM PDT 24
Peak memory 253480 kb
Host smart-cd51db0c-f759-4c49-a869-21d09b36c3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15945
76275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1594576275
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4195298183
Short name T664
Test name
Test status
Simulation time 3563737681 ps
CPU time 58.86 seconds
Started Mar 14 02:12:22 PM PDT 24
Finished Mar 14 02:13:21 PM PDT 24
Peak memory 248928 kb
Host smart-db1f4620-1e42-4ce1-80c5-ef66a041e61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41952
98183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4195298183
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3782034657
Short name T31
Test name
Test status
Simulation time 271128889 ps
CPU time 27.41 seconds
Started Mar 14 02:12:05 PM PDT 24
Finished Mar 14 02:12:32 PM PDT 24
Peak memory 256216 kb
Host smart-a4435f6e-0779-4b34-8685-10843e5caf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37820
34657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3782034657
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1283224215
Short name T502
Test name
Test status
Simulation time 819273001 ps
CPU time 46.38 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:13:08 PM PDT 24
Peak memory 249196 kb
Host smart-4e170603-2da6-46bb-ba34-564e03914610
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283224215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1283224215
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3340127601
Short name T52
Test name
Test status
Simulation time 81606493902 ps
CPU time 1770.3 seconds
Started Mar 14 02:12:18 PM PDT 24
Finished Mar 14 02:41:50 PM PDT 24
Peak memory 305744 kb
Host smart-b5b0663e-5611-4481-aae2-f8dbbec8d3da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340127601 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3340127601
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2325068246
Short name T71
Test name
Test status
Simulation time 105310424179 ps
CPU time 2156.78 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:48:19 PM PDT 24
Peak memory 289344 kb
Host smart-b94d2982-974e-4500-8796-9566959310d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325068246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2325068246
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2990791677
Short name T468
Test name
Test status
Simulation time 9342945000 ps
CPU time 279.03 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:17:00 PM PDT 24
Peak memory 257420 kb
Host smart-24ff7fb7-12a4-4204-829c-96eec65510ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
91677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2990791677
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2307276168
Short name T679
Test name
Test status
Simulation time 255489138 ps
CPU time 21.16 seconds
Started Mar 14 02:12:22 PM PDT 24
Finished Mar 14 02:12:44 PM PDT 24
Peak memory 248716 kb
Host smart-bbe341f8-5b31-4560-9428-7b63717ca026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23072
76168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2307276168
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.675117123
Short name T334
Test name
Test status
Simulation time 34943636492 ps
CPU time 1423.7 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:36:05 PM PDT 24
Peak memory 289516 kb
Host smart-6d434bfa-3926-45a0-bcff-73757a3f2956
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675117123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.675117123
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1516517879
Short name T634
Test name
Test status
Simulation time 70922908399 ps
CPU time 1515.41 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:37:36 PM PDT 24
Peak memory 273688 kb
Host smart-08f41c53-feee-4986-9f16-f21aae396e4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516517879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1516517879
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.4102756862
Short name T47
Test name
Test status
Simulation time 30076823177 ps
CPU time 322.92 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:17:45 PM PDT 24
Peak memory 248424 kb
Host smart-bf1509c3-75aa-4a5d-810d-6ab415b85e59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102756862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4102756862
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3297039560
Short name T349
Test name
Test status
Simulation time 44376973 ps
CPU time 5.82 seconds
Started Mar 14 02:12:22 PM PDT 24
Finished Mar 14 02:12:28 PM PDT 24
Peak memory 249052 kb
Host smart-c14a2576-d62e-4227-96ef-61dbc8f773b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32970
39560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3297039560
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.827181263
Short name T412
Test name
Test status
Simulation time 395087861 ps
CPU time 33.67 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:12:56 PM PDT 24
Peak memory 249248 kb
Host smart-5a8ff503-4607-468d-a8a5-2d4164e13be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82718
1263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.827181263
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4095801165
Short name T351
Test name
Test status
Simulation time 3140542959 ps
CPU time 58.02 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:13:19 PM PDT 24
Peak memory 256408 kb
Host smart-ccc72886-154f-42a8-a5e9-1b97da3b4b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40958
01165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4095801165
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2074547893
Short name T609
Test name
Test status
Simulation time 1001920444 ps
CPU time 61.77 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:13:23 PM PDT 24
Peak memory 249088 kb
Host smart-e5bd4ea0-a9f6-409b-9bf8-34cc669f93b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20745
47893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2074547893
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2779511315
Short name T506
Test name
Test status
Simulation time 18544517844 ps
CPU time 1472.21 seconds
Started Mar 14 02:12:22 PM PDT 24
Finished Mar 14 02:36:55 PM PDT 24
Peak memory 289408 kb
Host smart-1d9792e1-b7b5-411a-85af-8d49c976b4aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779511315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2779511315
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1850877664
Short name T241
Test name
Test status
Simulation time 69120550224 ps
CPU time 2259.36 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:50:01 PM PDT 24
Peak memory 273300 kb
Host smart-93444ffe-156b-436c-9380-7f3cf2a47619
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850877664 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1850877664
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2300378914
Short name T442
Test name
Test status
Simulation time 61713320192 ps
CPU time 1350.91 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 02:35:04 PM PDT 24
Peak memory 284812 kb
Host smart-28dca650-31b7-4ebf-af5d-946764bd912d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300378914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2300378914
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2894029980
Short name T587
Test name
Test status
Simulation time 1932586364 ps
CPU time 77.53 seconds
Started Mar 14 02:12:22 PM PDT 24
Finished Mar 14 02:13:40 PM PDT 24
Peak memory 256936 kb
Host smart-ee0dc9fb-a7e9-4352-99d5-f6f0ff29b07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28940
29980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2894029980
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2200772022
Short name T598
Test name
Test status
Simulation time 260814809 ps
CPU time 25.34 seconds
Started Mar 14 02:12:21 PM PDT 24
Finished Mar 14 02:12:48 PM PDT 24
Peak memory 249116 kb
Host smart-4fc3b896-5333-4369-adee-e2725d2e106b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22007
72022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2200772022
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3674446809
Short name T99
Test name
Test status
Simulation time 31299194237 ps
CPU time 1607.56 seconds
Started Mar 14 02:12:32 PM PDT 24
Finished Mar 14 02:39:19 PM PDT 24
Peak memory 289212 kb
Host smart-ebd3a8d4-341a-4ed9-8cd6-66212d6947e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674446809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3674446809
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.315857045
Short name T356
Test name
Test status
Simulation time 33240886604 ps
CPU time 518.55 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:21:13 PM PDT 24
Peak memory 273612 kb
Host smart-1a109fc7-4d84-4aff-8588-fa56d04412dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315857045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.315857045
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4068797607
Short name T207
Test name
Test status
Simulation time 59616430387 ps
CPU time 646.38 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 02:23:20 PM PDT 24
Peak memory 248340 kb
Host smart-db71ee64-b4b3-4582-bbec-a65628fb09a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068797607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4068797607
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1103777163
Short name T648
Test name
Test status
Simulation time 24007561846 ps
CPU time 81.82 seconds
Started Mar 14 02:12:19 PM PDT 24
Finished Mar 14 02:13:42 PM PDT 24
Peak memory 256544 kb
Host smart-e7460713-63a2-4883-bbe6-519aabebc312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11037
77163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1103777163
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3174924225
Short name T104
Test name
Test status
Simulation time 2290868142 ps
CPU time 88.18 seconds
Started Mar 14 02:12:20 PM PDT 24
Finished Mar 14 02:13:50 PM PDT 24
Peak memory 255752 kb
Host smart-6640953d-1da2-4f71-ab7d-85acb21eb257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31749
24225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3174924225
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.574219402
Short name T601
Test name
Test status
Simulation time 164133308 ps
CPU time 17.66 seconds
Started Mar 14 02:12:32 PM PDT 24
Finished Mar 14 02:12:50 PM PDT 24
Peak memory 256252 kb
Host smart-5e5ecbea-06d8-484b-9df0-c3c56b936a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57421
9402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.574219402
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.99022885
Short name T501
Test name
Test status
Simulation time 2318008297 ps
CPU time 38.48 seconds
Started Mar 14 02:12:23 PM PDT 24
Finished Mar 14 02:13:02 PM PDT 24
Peak memory 256856 kb
Host smart-dfcdd334-e447-409e-a8f5-af6d0bd31af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99022
885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.99022885
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1675108343
Short name T614
Test name
Test status
Simulation time 56702138559 ps
CPU time 2934.67 seconds
Started Mar 14 02:12:35 PM PDT 24
Finished Mar 14 03:01:30 PM PDT 24
Peak memory 300924 kb
Host smart-46a95fe0-cf33-4bbc-b737-9f941c72f7c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675108343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1675108343
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.423253415
Short name T95
Test name
Test status
Simulation time 57525985558 ps
CPU time 3204.23 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 03:05:59 PM PDT 24
Peak memory 289424 kb
Host smart-90286273-ef13-4643-8735-4d8dfba47e45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423253415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.423253415
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1632867354
Short name T644
Test name
Test status
Simulation time 1294310402 ps
CPU time 27.15 seconds
Started Mar 14 02:12:35 PM PDT 24
Finished Mar 14 02:13:02 PM PDT 24
Peak memory 256268 kb
Host smart-5e39c374-ccfc-4c5f-89e5-6855ff9fe63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16328
67354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1632867354
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2363392449
Short name T410
Test name
Test status
Simulation time 368373313 ps
CPU time 36.12 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:13:10 PM PDT 24
Peak memory 257184 kb
Host smart-9fad69c5-9ff7-46ba-95a6-090e201e518d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23633
92449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2363392449
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3603664686
Short name T600
Test name
Test status
Simulation time 45694381251 ps
CPU time 1407.13 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:36:01 PM PDT 24
Peak memory 268928 kb
Host smart-60b522ff-cf34-4008-9a61-91d409d10d6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603664686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3603664686
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3362049896
Short name T420
Test name
Test status
Simulation time 439781183681 ps
CPU time 1786.63 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 02:42:20 PM PDT 24
Peak memory 273272 kb
Host smart-a9a8445d-ed34-4da0-92ba-f94973057c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362049896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3362049896
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1797143182
Short name T307
Test name
Test status
Simulation time 44048494982 ps
CPU time 381.03 seconds
Started Mar 14 02:12:32 PM PDT 24
Finished Mar 14 02:18:53 PM PDT 24
Peak memory 248044 kb
Host smart-b4642d29-b6ff-4e7b-9dba-808b06b99b8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797143182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1797143182
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2199521234
Short name T389
Test name
Test status
Simulation time 1077474376 ps
CPU time 68.42 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 02:13:41 PM PDT 24
Peak memory 255972 kb
Host smart-f633408a-10c8-4aa1-aea8-1afc80a41420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995
21234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2199521234
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3110878146
Short name T706
Test name
Test status
Simulation time 228909302 ps
CPU time 15.18 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 02:12:48 PM PDT 24
Peak memory 247444 kb
Host smart-45141fbd-36e4-4cc0-90d8-e0a4452f2e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
78146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3110878146
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4184623040
Short name T659
Test name
Test status
Simulation time 2748578507 ps
CPU time 58.23 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:13:32 PM PDT 24
Peak memory 255716 kb
Host smart-b2938138-27cf-40f6-8a2b-e29a261e7279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41846
23040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4184623040
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1909248910
Short name T477
Test name
Test status
Simulation time 235027181 ps
CPU time 15.91 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:12:50 PM PDT 24
Peak memory 253168 kb
Host smart-231957d4-8fbd-4cea-82d3-e591f1e949c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19092
48910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1909248910
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1620016080
Short name T21
Test name
Test status
Simulation time 45868845758 ps
CPU time 987.81 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 02:29:01 PM PDT 24
Peak memory 290028 kb
Host smart-c19aaf46-c9c5-4970-b9bd-32e9e61918a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620016080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1620016080
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2368741296
Short name T224
Test name
Test status
Simulation time 219027006617 ps
CPU time 2849.83 seconds
Started Mar 14 02:12:33 PM PDT 24
Finished Mar 14 03:00:03 PM PDT 24
Peak memory 303300 kb
Host smart-0ce67eb7-a28c-4fd4-97a4-a99f7e87c83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368741296 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2368741296
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.213788742
Short name T676
Test name
Test status
Simulation time 59147970952 ps
CPU time 3152.76 seconds
Started Mar 14 02:12:45 PM PDT 24
Finished Mar 14 03:05:18 PM PDT 24
Peak memory 289568 kb
Host smart-3af2b336-da7f-44a2-bf2c-bd7da96843cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213788742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.213788742
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.422426751
Short name T586
Test name
Test status
Simulation time 4879516345 ps
CPU time 77.69 seconds
Started Mar 14 02:12:46 PM PDT 24
Finished Mar 14 02:14:03 PM PDT 24
Peak memory 256916 kb
Host smart-dd966f1b-af86-4bee-9030-c255d2e53c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42242
6751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.422426751
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1926813008
Short name T391
Test name
Test status
Simulation time 853089716 ps
CPU time 21.04 seconds
Started Mar 14 02:12:49 PM PDT 24
Finished Mar 14 02:13:10 PM PDT 24
Peak memory 249048 kb
Host smart-0665c8cd-1852-4038-9adf-f732ee1730ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19268
13008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1926813008
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1386123185
Short name T329
Test name
Test status
Simulation time 33287403474 ps
CPU time 1719.38 seconds
Started Mar 14 02:12:46 PM PDT 24
Finished Mar 14 02:41:25 PM PDT 24
Peak memory 273784 kb
Host smart-237a422e-439f-4d8b-8452-1d3bce53d1f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386123185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1386123185
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1060789280
Short name T619
Test name
Test status
Simulation time 10633048701 ps
CPU time 1114.03 seconds
Started Mar 14 02:12:47 PM PDT 24
Finished Mar 14 02:31:21 PM PDT 24
Peak memory 289392 kb
Host smart-988548b0-3d00-4a3f-9075-dff915d6661b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060789280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1060789280
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.970672260
Short name T512
Test name
Test status
Simulation time 322569493 ps
CPU time 10.06 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:12:45 PM PDT 24
Peak memory 249096 kb
Host smart-274ee01f-bd18-4e96-a0c2-22e3d41ec41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97067
2260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.970672260
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1104133553
Short name T438
Test name
Test status
Simulation time 63255680 ps
CPU time 5.88 seconds
Started Mar 14 02:12:49 PM PDT 24
Finished Mar 14 02:12:56 PM PDT 24
Peak memory 250836 kb
Host smart-11911efe-8fb8-4a70-9dcd-56e444b1a381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
33553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1104133553
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1521815890
Short name T372
Test name
Test status
Simulation time 182599612 ps
CPU time 7.26 seconds
Started Mar 14 02:12:44 PM PDT 24
Finished Mar 14 02:12:52 PM PDT 24
Peak memory 247472 kb
Host smart-6ae953c9-f144-4877-a3e5-c2bf7faf38e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15218
15890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1521815890
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4239171321
Short name T667
Test name
Test status
Simulation time 149066553 ps
CPU time 5.34 seconds
Started Mar 14 02:12:34 PM PDT 24
Finished Mar 14 02:12:40 PM PDT 24
Peak memory 240960 kb
Host smart-9df4a427-dc28-413e-a7c4-08d6bd0e9697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
71321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4239171321
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1942747591
Short name T498
Test name
Test status
Simulation time 7987761413 ps
CPU time 172.56 seconds
Started Mar 14 02:12:46 PM PDT 24
Finished Mar 14 02:15:39 PM PDT 24
Peak memory 257244 kb
Host smart-dc96ff8a-23e9-40d5-8aff-c1a316f01d16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942747591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1942747591
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4284829296
Short name T478
Test name
Test status
Simulation time 306289312837 ps
CPU time 1363.1 seconds
Started Mar 14 02:12:47 PM PDT 24
Finished Mar 14 02:35:30 PM PDT 24
Peak memory 265588 kb
Host smart-1b030dee-a1ef-4d78-8f3b-f2673a4cfdfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284829296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4284829296
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4197440323
Short name T577
Test name
Test status
Simulation time 48853838 ps
CPU time 2.74 seconds
Started Mar 14 02:12:49 PM PDT 24
Finished Mar 14 02:12:52 PM PDT 24
Peak memory 239388 kb
Host smart-e9bd2040-15e4-46aa-bea1-16662b0ee659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
40323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4197440323
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2348373950
Short name T490
Test name
Test status
Simulation time 1009015099 ps
CPU time 65.23 seconds
Started Mar 14 02:12:46 PM PDT 24
Finished Mar 14 02:13:52 PM PDT 24
Peak memory 249068 kb
Host smart-e495adf0-7b54-466d-af14-f26caef90b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
73950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2348373950
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.872062664
Short name T638
Test name
Test status
Simulation time 28737738536 ps
CPU time 1389.9 seconds
Started Mar 14 02:12:57 PM PDT 24
Finished Mar 14 02:36:08 PM PDT 24
Peak memory 290036 kb
Host smart-4d2335b1-7dfa-48ff-a0d6-e94ca35c45d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872062664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.872062664
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1295988368
Short name T448
Test name
Test status
Simulation time 221137199985 ps
CPU time 939.13 seconds
Started Mar 14 02:13:03 PM PDT 24
Finished Mar 14 02:28:42 PM PDT 24
Peak memory 281944 kb
Host smart-da046af9-ac60-4d4b-ba04-5d0f867ce50b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295988368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1295988368
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3453338836
Short name T295
Test name
Test status
Simulation time 33294798646 ps
CPU time 396.29 seconds
Started Mar 14 02:12:49 PM PDT 24
Finished Mar 14 02:19:26 PM PDT 24
Peak memory 248212 kb
Host smart-e12b1da7-7af2-403e-9f8a-280f520a8b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453338836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3453338836
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.4214394299
Short name T591
Test name
Test status
Simulation time 91631597 ps
CPU time 6.66 seconds
Started Mar 14 02:12:46 PM PDT 24
Finished Mar 14 02:12:53 PM PDT 24
Peak memory 249156 kb
Host smart-abf6692f-3f27-4ad6-8cb4-e914cf7d1961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42143
94299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4214394299
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1278330998
Short name T655
Test name
Test status
Simulation time 39626094 ps
CPU time 4.96 seconds
Started Mar 14 02:12:49 PM PDT 24
Finished Mar 14 02:12:54 PM PDT 24
Peak memory 240544 kb
Host smart-c8318628-6bf0-4d97-82a3-46a8b089e8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783
30998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1278330998
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3159349670
Short name T261
Test name
Test status
Simulation time 125171557 ps
CPU time 9.02 seconds
Started Mar 14 02:12:47 PM PDT 24
Finished Mar 14 02:12:56 PM PDT 24
Peak memory 240872 kb
Host smart-36a30496-8c95-4214-ad64-7ae3f055dfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31593
49670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3159349670
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.522241627
Short name T285
Test name
Test status
Simulation time 309282210 ps
CPU time 29.64 seconds
Started Mar 14 02:12:48 PM PDT 24
Finished Mar 14 02:13:18 PM PDT 24
Peak memory 249220 kb
Host smart-ec866e45-e262-40c4-87e2-40f1f1e76995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52224
1627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.522241627
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.219385483
Short name T267
Test name
Test status
Simulation time 4451874028 ps
CPU time 367.93 seconds
Started Mar 14 02:12:58 PM PDT 24
Finished Mar 14 02:19:07 PM PDT 24
Peak memory 273116 kb
Host smart-45504e01-1ed7-489d-8dfc-42cee1c9d54b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219385483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.219385483
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3017518989
Short name T188
Test name
Test status
Simulation time 178335300 ps
CPU time 3.19 seconds
Started Mar 14 02:07:37 PM PDT 24
Finished Mar 14 02:07:40 PM PDT 24
Peak memory 249284 kb
Host smart-0ae44324-5679-419a-8335-ab6888080383
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3017518989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3017518989
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.421335767
Short name T444
Test name
Test status
Simulation time 28026048834 ps
CPU time 1584.23 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:34:03 PM PDT 24
Peak memory 273732 kb
Host smart-834e496d-b2b2-4b72-ba06-81342500196f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421335767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.421335767
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2085053898
Short name T424
Test name
Test status
Simulation time 2660207013 ps
CPU time 13.84 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:07:52 PM PDT 24
Peak memory 249180 kb
Host smart-ed5a9250-0134-48cb-9daf-578c45446fe4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2085053898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2085053898
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.920875445
Short name T569
Test name
Test status
Simulation time 7073533097 ps
CPU time 168.78 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:10:27 PM PDT 24
Peak memory 257288 kb
Host smart-cc495446-ee7e-4b2f-8f3f-96d17efd39ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92087
5445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.920875445
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3996621692
Short name T401
Test name
Test status
Simulation time 5289964296 ps
CPU time 77.56 seconds
Started Mar 14 02:07:39 PM PDT 24
Finished Mar 14 02:08:56 PM PDT 24
Peak memory 255932 kb
Host smart-d63f6ffd-1a6d-44bd-bc9c-154338b5f572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39966
21692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3996621692
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1043080633
Short name T583
Test name
Test status
Simulation time 48925303044 ps
CPU time 672.48 seconds
Started Mar 14 02:07:42 PM PDT 24
Finished Mar 14 02:18:55 PM PDT 24
Peak memory 266552 kb
Host smart-0f997ff8-81ca-4413-bec2-9f07b15bf08d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043080633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1043080633
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1787387968
Short name T459
Test name
Test status
Simulation time 73165002442 ps
CPU time 1128.17 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:26:26 PM PDT 24
Peak memory 273724 kb
Host smart-5453942c-3cd1-4cd4-9216-b674c989e397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787387968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1787387968
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3489557702
Short name T682
Test name
Test status
Simulation time 21133184812 ps
CPU time 446.97 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:15:05 PM PDT 24
Peak memory 247320 kb
Host smart-661bd3a7-b7c9-4183-b320-313cf69dc4f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489557702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3489557702
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3429298583
Short name T203
Test name
Test status
Simulation time 233718439 ps
CPU time 5.93 seconds
Started Mar 14 02:07:41 PM PDT 24
Finished Mar 14 02:07:47 PM PDT 24
Peak memory 249020 kb
Host smart-d8928f6c-941d-42fb-ae22-e744e6da960a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292
98583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3429298583
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1625021729
Short name T590
Test name
Test status
Simulation time 147021740 ps
CPU time 18.37 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:07:57 PM PDT 24
Peak memory 255608 kb
Host smart-d3a647ba-b17d-4eef-96b1-6e13e9c14257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
21729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1625021729
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1363238540
Short name T374
Test name
Test status
Simulation time 1077905601 ps
CPU time 27.88 seconds
Started Mar 14 02:07:40 PM PDT 24
Finished Mar 14 02:08:08 PM PDT 24
Peak memory 249092 kb
Host smart-24f83f7a-980f-4f9b-89a9-9beab4201574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632
38540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1363238540
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1178145965
Short name T546
Test name
Test status
Simulation time 451084174 ps
CPU time 27.74 seconds
Started Mar 14 02:07:41 PM PDT 24
Finished Mar 14 02:08:08 PM PDT 24
Peak memory 249024 kb
Host smart-f7589cd3-faaa-4956-a927-6da69a31a1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
45965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1178145965
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.940896942
Short name T433
Test name
Test status
Simulation time 202924378 ps
CPU time 24.13 seconds
Started Mar 14 02:07:36 PM PDT 24
Finished Mar 14 02:08:00 PM PDT 24
Peak memory 249100 kb
Host smart-681b9319-2390-465f-99dc-bb153a5cd345
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940896942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.940896942
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1120952847
Short name T237
Test name
Test status
Simulation time 118040777892 ps
CPU time 8943.05 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 04:36:42 PM PDT 24
Peak memory 394456 kb
Host smart-026d303d-b40d-4a6a-af66-a15c4a450dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120952847 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1120952847
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1564409630
Short name T196
Test name
Test status
Simulation time 233104790 ps
CPU time 4.13 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:07:58 PM PDT 24
Peak memory 249236 kb
Host smart-fd065c90-ed07-49eb-98ae-e0e07b65305a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1564409630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1564409630
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3679839977
Short name T417
Test name
Test status
Simulation time 41614825864 ps
CPU time 1497.66 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:32:51 PM PDT 24
Peak memory 267864 kb
Host smart-78954076-ca47-4130-81a8-e44975d60a82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679839977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3679839977
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1381866480
Short name T474
Test name
Test status
Simulation time 355034483 ps
CPU time 12.6 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:11 PM PDT 24
Peak memory 249044 kb
Host smart-031ad932-1839-4ef7-b2fd-f75fe9a3f1d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1381866480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1381866480
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1152170135
Short name T236
Test name
Test status
Simulation time 5876704725 ps
CPU time 190.43 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:11:05 PM PDT 24
Peak memory 257100 kb
Host smart-2e9bfd5e-0738-4e38-b69a-e7b9cd1e4b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11521
70135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1152170135
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3858516337
Short name T357
Test name
Test status
Simulation time 409207184 ps
CPU time 11.19 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:07:49 PM PDT 24
Peak memory 255696 kb
Host smart-de56d7c3-1ed5-47ad-b044-67d70149d8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
16337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3858516337
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.895757705
Short name T214
Test name
Test status
Simulation time 15292346368 ps
CPU time 1151.26 seconds
Started Mar 14 02:07:59 PM PDT 24
Finished Mar 14 02:27:10 PM PDT 24
Peak memory 271752 kb
Host smart-c307afdc-7449-43c7-84c9-d6d1ff2d658a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895757705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.895757705
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3404238173
Short name T531
Test name
Test status
Simulation time 257630317021 ps
CPU time 2396.63 seconds
Started Mar 14 02:07:52 PM PDT 24
Finished Mar 14 02:47:50 PM PDT 24
Peak memory 289700 kb
Host smart-51c55884-ee19-4ee6-a5e8-9336ef91dc09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404238173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3404238173
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2461770602
Short name T283
Test name
Test status
Simulation time 7440540827 ps
CPU time 302.49 seconds
Started Mar 14 02:07:52 PM PDT 24
Finished Mar 14 02:12:56 PM PDT 24
Peak memory 248400 kb
Host smart-f32dded5-d473-4b21-9648-a3524915aa4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461770602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2461770602
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2446250254
Short name T430
Test name
Test status
Simulation time 180370194 ps
CPU time 14.29 seconds
Started Mar 14 02:07:39 PM PDT 24
Finished Mar 14 02:07:53 PM PDT 24
Peak memory 254936 kb
Host smart-65ed2f07-3ddd-422e-94cf-05512ac210c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24462
50254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2446250254
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.683198546
Short name T217
Test name
Test status
Simulation time 4118438598 ps
CPU time 62.73 seconds
Started Mar 14 02:07:38 PM PDT 24
Finished Mar 14 02:08:41 PM PDT 24
Peak memory 257132 kb
Host smart-53fe680a-1a3c-4f1a-a962-efe74c169c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68319
8546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.683198546
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.820403402
Short name T545
Test name
Test status
Simulation time 1086787462 ps
CPU time 30.83 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:29 PM PDT 24
Peak memory 249016 kb
Host smart-19f9a47b-f286-4400-82a2-4ff90b944e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82040
3402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.820403402
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.50310907
Short name T396
Test name
Test status
Simulation time 71429250 ps
CPU time 8.35 seconds
Started Mar 14 02:07:41 PM PDT 24
Finished Mar 14 02:07:49 PM PDT 24
Peak memory 257280 kb
Host smart-9d0f5f56-13cf-46ed-96b1-12e1ede4149b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50310
907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.50310907
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1104590571
Short name T72
Test name
Test status
Simulation time 2141502627 ps
CPU time 54.1 seconds
Started Mar 14 02:07:55 PM PDT 24
Finished Mar 14 02:08:49 PM PDT 24
Peak memory 250296 kb
Host smart-5c3ddd9f-cb88-4bfb-afb1-03343249a008
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104590571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1104590571
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3631661735
Short name T450
Test name
Test status
Simulation time 1223449995 ps
CPU time 49.95 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:08:43 PM PDT 24
Peak memory 240864 kb
Host smart-e2812050-e8ee-4680-9e78-f0011c4d0c0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3631661735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3631661735
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2756263425
Short name T358
Test name
Test status
Simulation time 1031025037 ps
CPU time 12.23 seconds
Started Mar 14 02:07:52 PM PDT 24
Finished Mar 14 02:08:06 PM PDT 24
Peak memory 255080 kb
Host smart-d24645dd-b749-4f6e-856a-ef5050565a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27562
63425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2756263425
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.4272614382
Short name T684
Test name
Test status
Simulation time 54016302082 ps
CPU time 1139.85 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:26:55 PM PDT 24
Peak memory 273348 kb
Host smart-4f941c2e-66fe-4499-aca6-8ded1d1dcc8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272614382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.4272614382
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1557036700
Short name T2
Test name
Test status
Simulation time 37327061337 ps
CPU time 400.02 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:14:38 PM PDT 24
Peak memory 248424 kb
Host smart-65dac63f-1cc1-443a-89d6-39d0125f762f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557036700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1557036700
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1657206008
Short name T558
Test name
Test status
Simulation time 121615242 ps
CPU time 9.08 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:07 PM PDT 24
Peak memory 252328 kb
Host smart-d13793d6-c7fd-453f-b1e8-9c1949632037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572
06008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1657206008
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1266149399
Short name T494
Test name
Test status
Simulation time 1289745510 ps
CPU time 79.09 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:09:13 PM PDT 24
Peak memory 255576 kb
Host smart-97fbfcb5-ff9e-4ccf-87b0-e328939c0511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12661
49399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1266149399
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1540431472
Short name T78
Test name
Test status
Simulation time 1968453899 ps
CPU time 43.38 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:08:38 PM PDT 24
Peak memory 255780 kb
Host smart-2cb77516-2e86-45f5-bdfa-13586f388f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
31472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1540431472
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2461430734
Short name T445
Test name
Test status
Simulation time 300566034 ps
CPU time 6.68 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:08:02 PM PDT 24
Peak memory 251044 kb
Host smart-394da983-2c01-4de5-af7f-538050635d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24614
30734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2461430734
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.29872240
Short name T101
Test name
Test status
Simulation time 13613622995 ps
CPU time 870.43 seconds
Started Mar 14 02:07:52 PM PDT 24
Finished Mar 14 02:22:24 PM PDT 24
Peak memory 265508 kb
Host smart-0e0e4fc7-e4ea-4101-8143-d89a3dc8577d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29872240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handl
er_stress_all.29872240
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2383432058
Short name T195
Test name
Test status
Simulation time 55759675 ps
CPU time 2.71 seconds
Started Mar 14 02:07:50 PM PDT 24
Finished Mar 14 02:07:54 PM PDT 24
Peak memory 249268 kb
Host smart-0427b740-d4c6-4fcc-80e1-bbd1aa86c301
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2383432058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2383432058
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3515816777
Short name T642
Test name
Test status
Simulation time 134405467805 ps
CPU time 1784.82 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:37:43 PM PDT 24
Peak memory 273396 kb
Host smart-b83534fe-6dc9-4d20-ac9d-e6fa01f1bc09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515816777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3515816777
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3647636950
Short name T497
Test name
Test status
Simulation time 798203029 ps
CPU time 18.07 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:16 PM PDT 24
Peak memory 240512 kb
Host smart-c575112f-dc00-402c-96b8-c80a6834721d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3647636950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3647636950
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1364493739
Short name T402
Test name
Test status
Simulation time 21328775362 ps
CPU time 320.44 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:13:18 PM PDT 24
Peak memory 257376 kb
Host smart-2c64b288-3ae5-45d8-a33d-5d7da81f2c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
93739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1364493739
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2452183391
Short name T252
Test name
Test status
Simulation time 575675060 ps
CPU time 37.42 seconds
Started Mar 14 02:07:52 PM PDT 24
Finished Mar 14 02:08:31 PM PDT 24
Peak memory 249416 kb
Host smart-e344f8b5-995f-4d59-801c-0d8a4113a95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
83391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2452183391
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.373051619
Short name T90
Test name
Test status
Simulation time 48675179691 ps
CPU time 1146.48 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:27:01 PM PDT 24
Peak memory 281912 kb
Host smart-ede6182f-f1f7-4a2c-90e0-c0a7dddf4127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373051619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.373051619
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2862333063
Short name T173
Test name
Test status
Simulation time 9841912342 ps
CPU time 1003.65 seconds
Started Mar 14 02:07:56 PM PDT 24
Finished Mar 14 02:24:40 PM PDT 24
Peak memory 281428 kb
Host smart-3c68ba4f-187f-44bc-a4cc-c35a896e8fa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862333063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2862333063
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3273571658
Short name T303
Test name
Test status
Simulation time 15912494654 ps
CPU time 172.04 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:10:50 PM PDT 24
Peak memory 248092 kb
Host smart-11b4c341-8313-44c3-9cbc-bfff85e2acfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273571658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3273571658
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3106608053
Short name T599
Test name
Test status
Simulation time 925704975 ps
CPU time 43.18 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:08:40 PM PDT 24
Peak memory 249088 kb
Host smart-92fd7780-f53f-4958-9e84-0eb96b2cf44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
08053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3106608053
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3103942712
Short name T102
Test name
Test status
Simulation time 1558282955 ps
CPU time 53.09 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:08:46 PM PDT 24
Peak memory 247680 kb
Host smart-91e3e364-2a89-4845-9d9e-5cd9e0a11290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039
42712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3103942712
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.432044089
Short name T585
Test name
Test status
Simulation time 445772045 ps
CPU time 11.38 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:08:06 PM PDT 24
Peak memory 253156 kb
Host smart-172d69d7-4893-49b2-b9bd-18e48f798069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43204
4089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.432044089
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1621191707
Short name T696
Test name
Test status
Simulation time 14489967690 ps
CPU time 1488.78 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:32:46 PM PDT 24
Peak memory 297960 kb
Host smart-d61eb9fb-96d4-4799-b321-af5e578c1781
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621191707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1621191707
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3690763638
Short name T92
Test name
Test status
Simulation time 357829560403 ps
CPU time 7669.34 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 04:15:45 PM PDT 24
Peak memory 372108 kb
Host smart-0f8e37ee-ae62-4b0c-846c-0b4418a6575d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690763638 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3690763638
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2798892855
Short name T193
Test name
Test status
Simulation time 115081262 ps
CPU time 3.43 seconds
Started Mar 14 02:07:54 PM PDT 24
Finished Mar 14 02:07:58 PM PDT 24
Peak memory 249212 kb
Host smart-1ca9c7c8-b973-48c9-8384-369d5e2a0861
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2798892855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2798892855
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1078664932
Short name T208
Test name
Test status
Simulation time 26014806050 ps
CPU time 1553.35 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:33:54 PM PDT 24
Peak memory 266692 kb
Host smart-1675f3d4-22ce-4e18-abec-79bbaffd8c0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078664932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1078664932
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2764280777
Short name T678
Test name
Test status
Simulation time 581313123 ps
CPU time 9.83 seconds
Started Mar 14 02:07:48 PM PDT 24
Finished Mar 14 02:07:58 PM PDT 24
Peak memory 240720 kb
Host smart-ca33556a-1a2e-43b0-8251-f87dd2fb96c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2764280777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2764280777
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2505180165
Short name T388
Test name
Test status
Simulation time 1626339612 ps
CPU time 54.67 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:53 PM PDT 24
Peak memory 255924 kb
Host smart-1d2fe8c2-85fb-47b2-8634-55c8c099a9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
80165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2505180165
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3070317114
Short name T365
Test name
Test status
Simulation time 295547330 ps
CPU time 33.08 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:08:27 PM PDT 24
Peak memory 255724 kb
Host smart-0e1fda99-9417-4adb-bfba-a586426e65e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30703
17114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3070317114
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1499972476
Short name T320
Test name
Test status
Simulation time 80626570420 ps
CPU time 1436.03 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:31:55 PM PDT 24
Peak memory 272564 kb
Host smart-551495a8-f6eb-4188-90b7-f4d29c11c095
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499972476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1499972476
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.159122677
Short name T7
Test name
Test status
Simulation time 41663029898 ps
CPU time 1031.59 seconds
Started Mar 14 02:07:56 PM PDT 24
Finished Mar 14 02:25:08 PM PDT 24
Peak memory 289144 kb
Host smart-f100ec47-36fa-4534-8b96-91d6c490f78b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159122677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.159122677
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4275922258
Short name T553
Test name
Test status
Simulation time 1547359768 ps
CPU time 67.3 seconds
Started Mar 14 02:07:57 PM PDT 24
Finished Mar 14 02:09:05 PM PDT 24
Peak memory 248172 kb
Host smart-7edc4b50-74c0-4e20-9e38-ccb2d8a2d899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275922258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4275922258
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3398546359
Short name T172
Test name
Test status
Simulation time 337702628 ps
CPU time 34.1 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:08:27 PM PDT 24
Peak memory 257240 kb
Host smart-13f14bb1-f664-428e-a34f-4627157cfeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
46359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3398546359
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1566537420
Short name T54
Test name
Test status
Simulation time 921122139 ps
CPU time 57.27 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:55 PM PDT 24
Peak memory 249088 kb
Host smart-65ce889f-1bcc-41b5-a092-00a4384a9af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15665
37420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1566537420
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.173521553
Short name T386
Test name
Test status
Simulation time 408076899 ps
CPU time 34.83 seconds
Started Mar 14 02:07:53 PM PDT 24
Finished Mar 14 02:08:29 PM PDT 24
Peak memory 256384 kb
Host smart-49152d9c-5615-463b-9889-b32435c51013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17352
1553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.173521553
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.408506118
Short name T206
Test name
Test status
Simulation time 1783566530 ps
CPU time 30.36 seconds
Started Mar 14 02:07:52 PM PDT 24
Finished Mar 14 02:08:23 PM PDT 24
Peak memory 256412 kb
Host smart-15fa9291-7b80-447e-a62b-c689955ca0bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
6118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.408506118
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.767872755
Short name T455
Test name
Test status
Simulation time 1185199022 ps
CPU time 51.8 seconds
Started Mar 14 02:07:58 PM PDT 24
Finished Mar 14 02:08:50 PM PDT 24
Peak memory 255812 kb
Host smart-aa772d3a-b457-47a5-9501-f86beba94b38
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767872755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.767872755
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.943618798
Short name T109
Test name
Test status
Simulation time 15409169748 ps
CPU time 1072.88 seconds
Started Mar 14 02:08:01 PM PDT 24
Finished Mar 14 02:25:54 PM PDT 24
Peak memory 273912 kb
Host smart-eea5801f-695b-4f36-bdf0-451b2cca594d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943618798 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.943618798
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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