Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T64,T210
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14972	0	0
DisabledNoTrigBkwd_A	2147483647	768158	0	0
DisabledNoTrigFwd_A	2147483647	1414923809	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14972	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T19	2888	580	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T64	2692	424	0	0
T86	49396	0	0	0
T126	555619	0	0	0
T210	0	1032	0	0
T232	2930	644	0	0
T233	0	1491	0	0
T234	0	374	0	0
T235	0	272	0	0
T236	0	961	0	0
T237	0	1142	0	0
T238	0	1104	0	0
T239	0	843	0	0
T240	0	260	0	0
T241	0	775	0	0
T242	0	496	0	0
T243	0	545	0	0
T244	0	1726	0	0
T245	0	408	0	0
T246	0	388	0	0
T247	0	446	0	0
T248	0	1061	0	0
T249	52703	0	0	0
T250	13105	0	0	0
T251	4178	0	0	0
T252	17567	0	0	0
T253	73229	0	0	0
T254	303115	0	0	0
T255	700402	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	768158	0	0
T3	361840	146	0	0
T4	707392	3414	0	0
T5	1524700	3203	0	0
T6	1089748	3034	0	0
T7	2650476	2	0	0
T8	0	2	0	0
T9	0	4	0	0
T14	0	1127	0	0
T15	0	1872	0	0
T16	0	3059	0	0
T17	140428	5	0	0
T18	95500	20	0	0
T19	11552	9	0	0
T20	104108	0	0	0
T21	38240	0	0	0
T22	0	19	0	0
T44	0	30	0	0
T45	0	21	0	0
T46	0	910	0	0
T47	0	712	0	0
T48	0	542	0	0
T49	0	1924	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1414923809	0	0
T1	90504	45897	0	0
T2	27004	18759	0	0
T3	361840	131571	0	0
T4	707392	206646	0	0
T5	1524700	780033	0	0
T6	1089748	590829	0	0
T17	140428	124867	0	0
T18	95500	73440	0	0
T19	11552	8654	0	0
T20	104108	8525	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T236,T242
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662240471	2425	0	0
DisabledNoTrigBkwd_A	662240471	210603	0	0
DisabledNoTrigFwd_A	662240471	319800681	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	2425	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T19	2888	580	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T236	0	961	0	0
T242	0	496	0	0
T246	0	388	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	210603	0	0
T3	90460	48	0	0
T4	176848	972	0	0
T5	381175	17	0	0
T6	272437	1740	0	0
T7	662619	0	0	0
T14	0	8	0	0
T16	0	1581	0	0
T17	35107	0	0	0
T18	23875	20	0	0
T19	2888	9	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	4	0	0
T46	0	312	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	319800681	0	0
T1	22626	3086	0	0
T2	6751	5976	0	0
T3	90460	29430	0	0
T4	176848	6378	0	0
T5	381175	376800	0	0
T6	272437	5874	0	0
T17	35107	35026	0	0
T18	23875	2007	0	0
T19	2888	2141	0	0
T20	26027	2112	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T232,T235,T240
1	1	Covered	T2,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662240471	1176	0	0
DisabledNoTrigBkwd_A	662240471	201755	0	0
DisabledNoTrigFwd_A	662240471	370761718	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1176	0	0
T86	49396	0	0	0
T126	555619	0	0	0
T232	2930	644	0	0
T235	0	272	0	0
T240	0	260	0	0
T249	52703	0	0	0
T250	13105	0	0	0
T251	4178	0	0	0
T252	17567	0	0	0
T253	73229	0	0	0
T254	303115	0	0	0
T255	700402	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	201755	0	0
T3	90460	4	0	0
T4	176848	1152	0	0
T5	381175	1553	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T9	0	4	0	0
T15	0	1872	0	0
T17	35107	3	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	2	0	0
T46	0	597	0	0
T48	0	287	0	0
T49	0	1924	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	370761718	0	0
T1	22626	22559	0	0
T2	6751	586	0	0
T3	90460	77927	0	0
T4	176848	14423	0	0
T5	381175	19438	0	0
T6	272437	272427	0	0
T17	35107	27406	0	0
T18	23875	23811	0	0
T19	2888	2156	0	0
T20	26027	2119	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T233,T237
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662240471	6797	0	0
DisabledNoTrigBkwd_A	662240471	170832	0	0
DisabledNoTrigFwd_A	662240471	354108957	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	6797	0	0
T23	23972	0	0	0
T24	36475	0	0	0
T25	181163	0	0	0
T64	2692	424	0	0
T65	521111	0	0	0
T66	36112	0	0	0
T67	156637	0	0	0
T68	16364	0	0	0
T69	548938	0	0	0
T70	348882	0	0	0
T233	0	1491	0	0
T237	0	1142	0	0
T243	0	545	0	0
T244	0	1726	0	0
T245	0	408	0	0
T248	0	1061	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	170832	0	0
T3	90460	52	0	0
T4	176848	0	0	0
T5	381175	1633	0	0
T6	272437	1294	0	0
T7	662619	2	0	0
T8	0	2	0	0
T14	0	1114	0	0
T17	35107	2	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	6	0	0
T44	0	13	0	0
T45	0	19	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	354108957	0	0
T1	22626	3119	0	0
T2	6751	5525	0	0
T3	90460	12021	0	0
T4	176848	176083	0	0
T5	381175	3175	0	0
T6	272437	40101	0	0
T17	35107	27409	0	0
T18	23875	23811	0	0
T19	2888	2174	0	0
T20	26027	2140	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T210,T234,T238
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	662240471	4574	0	0
DisabledNoTrigBkwd_A	662240471	184968	0	0
DisabledNoTrigFwd_A	662240471	370252453	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	4574	0	0
T33	64800	0	0	0
T53	25052	0	0	0
T77	80078	0	0	0
T80	240652	0	0	0
T210	4473	1032	0	0
T211	329471	0	0	0
T212	19658	0	0	0
T213	378906	0	0	0
T214	10165	0	0	0
T215	57216	0	0	0
T234	0	374	0	0
T238	0	1104	0	0
T239	0	843	0	0
T241	0	775	0	0
T247	0	446	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	184968	0	0
T3	90460	42	0	0
T4	176848	1290	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T14	0	5	0	0
T16	0	1478	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	7	0	0
T44	0	17	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	712	0	0
T48	0	255	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	370252453	0	0
T1	22626	17133	0	0
T2	6751	6672	0	0
T3	90460	12193	0	0
T4	176848	9762	0	0
T5	381175	380620	0	0
T6	272437	272427	0	0
T17	35107	35026	0	0
T18	23875	23811	0	0
T19	2888	2183	0	0
T20	26027	2154	0	0