Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T22
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T3,T17,T22
1	1	1	Covered	T3,T20,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T22
0	1	Covered	T23,T24,T25
1	0	Covered	T3,T22,T26

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T22
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T22,T26

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T22
1	0	Covered	T27,T28
1	1	Covered	T23,T24,T25

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T5,T18,T19

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T17,T6

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T7,T22

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T4,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T5
Phase1St	193	Covered	T3,T4,T5
Phase2St	210	Covered	T3,T4,T5
Phase3St	228	Covered	T3,T4,T5
TerminalSt	244	Covered	T3,T4,T5
TimeoutSt	154	Covered	T3,T20,T22

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T3,T4,T5
IdleSt->TimeoutSt	154	Covered	T3,T20,T22
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T29,T28,T30
Phase0St->Phase1St	193	Covered	T3,T4,T5
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T4,T14,T31
Phase1St->Phase2St	210	Covered	T3,T4,T5
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T6,T25,T32
Phase2St->Phase3St	228	Covered	T3,T4,T5
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T6,T25,T33
Phase3St->TerminalSt	244	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T3,T17,T6
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T20,T22,T31
TimeoutSt->Phase0St	167	Covered	T3,T22,T26

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T14,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T25,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T25,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T17,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1132	0	0
CheckAccumTrig0_A	2147483647	2274	0	0
CheckAccumTrig1_A	2147483647	118	0	0
CheckClr_A	2147483647	1015	0	0
CheckEn_A	2147483647	1073817047	0	0
CheckPhase0_A	2147483647	2570	0	0
CheckPhase1_A	2147483647	2525	0	0
CheckPhase2_A	2147483647	2476	0	0
CheckPhase3_A	2147483647	2425	0	0
CheckTimeout0_A	2147483647	2921	0	0
CheckTimeoutSt1_A	2147483647	372299	0	0
CheckTimeoutSt2_A	2147483647	2584	0	0
CheckTimeoutStTrig_A	2147483647	215	0	0
ErrorStAllEscAsserted_A	2147483647	5762	0	0
ErrorStIsTerminal_A	2147483647	4802	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1132	0	0
T10	133660	264	0	0
T11	0	302	0	0
T12	0	137	0	0
T28	1901344	0	0	0
T29	818584	0	0	0
T35	0	296	0	0
T36	0	133	0	0
T37	482392	0	0	0
T38	41700	0	0	0
T39	143740	0	0	0
T40	486124	0	0	0
T41	1360472	0	0	0
T42	2231044	0	0	0
T43	92088	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2274	0	0
T3	271380	5	0	0
T4	707392	4	0	0
T5	1524700	3	0	0
T6	1089748	8	0	0
T7	2650476	1	0	0
T8	421875	1	0	0
T9	0	1	0	0
T14	0	5	0	0
T15	0	3	0	0
T16	0	2	0	0
T17	140428	2	0	0
T18	95500	1	0	0
T19	11552	1	0	0
T20	104108	0	0	0
T21	38240	0	0	0
T22	0	4	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	5	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T23	23972	0	0	0
T24	36475	0	0	0
T25	0	1	0	0
T26	25512	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	3	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	572474	1	0	0
T62	0	2	0	0
T63	198078	0	0	0
T64	2692	0	0	0
T65	521111	0	0	0
T66	36112	0	0	0
T67	156637	0	0	0
T68	16364	0	0	0
T69	548938	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1015	0	0
T3	180920	1	0	0
T4	530544	1	0	0
T5	1143525	0	0	0
T6	1089748	6	0	0
T7	2650476	0	0	0
T8	843750	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	140428	1	0	0
T18	95500	0	0	0
T19	11552	0	0	0
T20	104108	0	0	0
T21	38240	0	0	0
T22	0	2	0	0
T23	0	4	0	0
T25	0	9	0	0
T26	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T66	0	1	0	0
T67	0	3	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1073817047	0	0
T1	90504	45895	0	0
T2	27004	18757	0	0
T3	361840	50181	0	0
T4	707392	206646	0	0
T5	1524700	401109	0	0
T6	1089748	590829	0	0
T17	140428	99552	0	0
T18	95500	73437	0	0
T19	11552	8654	0	0
T20	104108	8525	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2570	0	0
T3	361840	6	0	0
T4	707392	4	0	0
T5	1524700	3	0	0
T6	1089748	8	0	0
T7	2650476	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	5	0	0
T15	0	3	0	0
T16	0	2	0	0
T17	140428	2	0	0
T18	95500	1	0	0
T19	11552	1	0	0
T20	104108	1	0	0
T21	38240	0	0	0
T22	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2525	0	0
T3	361840	6	0	0
T4	707392	3	0	0
T5	1524700	3	0	0
T6	1089748	8	0	0
T7	2650476	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	0	2	0	0
T17	140428	2	0	0
T18	95500	1	0	0
T19	11552	1	0	0
T20	104108	1	0	0
T21	38240	0	0	0
T22	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2476	0	0
T3	361840	6	0	0
T4	707392	3	0	0
T5	1524700	3	0	0
T6	1089748	6	0	0
T7	2650476	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	0	2	0	0
T17	140428	2	0	0
T18	95500	1	0	0
T19	11552	1	0	0
T20	104108	1	0	0
T21	38240	0	0	0
T22	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2425	0	0
T3	361840	6	0	0
T4	707392	3	0	0
T5	1524700	3	0	0
T6	1089748	5	0	0
T7	2650476	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T14	0	4	0	0
T15	0	3	0	0
T16	0	2	0	0
T17	140428	2	0	0
T18	95500	1	0	0
T19	11552	1	0	0
T20	104108	1	0	0
T21	38240	0	0	0
T22	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2921	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	2650476	0	0	0
T8	1265625	0	0	0
T9	2451297	0	0	0
T13	98619	0	0	0
T14	684552	0	0	0
T15	976161	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	104108	9	0	0
T21	38240	0	0	0
T22	190662	4	0	0
T23	0	2	0	0
T24	0	3	0	0
T25	0	7	0	0
T26	0	2	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	4	0	0
T50	0	176	0	0
T51	0	2	0	0
T52	0	11	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	36	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	55113	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	372299	0	0
T3	90460	4	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	2650476	0	0	0
T8	1265625	0	0	0
T9	2451297	0	0	0
T13	98619	0	0	0
T14	684552	0	0	0
T15	976161	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	104108	1074	0	0
T21	38240	0	0	0
T22	190662	296	0	0
T23	0	255	0	0
T24	0	516	0	0
T25	0	200	0	0
T26	0	139	0	0
T31	0	37	0	0
T32	0	297	0	0
T33	0	879	0	0
T50	0	19616	0	0
T51	0	849	0	0
T52	0	2504	0	0
T71	0	39	0	0
T72	0	154	0	0
T73	0	193	0	0
T74	0	3	0	0
T75	0	158	0	0
T76	0	2210	0	0
T77	0	190	0	0
T78	0	119	0	0
T79	55113	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T7	1987857	0	0	0
T8	1265625	0	0	0
T9	2451297	0	0	0
T13	98619	0	0	0
T14	684552	0	0	0
T15	1301548	0	0	0
T16	341840	0	0	0
T20	78081	8	0	0
T21	28680	0	0	0
T22	254216	3	0	0
T23	0	1	0	0
T24	0	2	0	0
T25	0	5	0	0
T26	0	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	4	0	0
T44	221734	0	0	0
T45	78133	0	0	0
T46	134896	0	0	0
T47	131157	0	0	0
T48	939235	0	0	0
T49	274677	0	0	0
T50	0	174	0	0
T52	0	4	0	0
T54	0	32	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	36	0	0
T79	73484	0	0	0
T80	0	4	0	0
T81	0	8	0	0
T82	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	215	0	0
T23	23972	1	0	0
T24	72950	1	0	0
T25	362326	1	0	0
T28	0	5	0	0
T29	0	1	0	0
T32	0	2	0	0
T41	0	1	0	0
T50	667722	1	0	0
T51	11396	1	0	0
T52	0	3	0	0
T54	0	2	0	0
T68	16364	0	0	0
T69	548938	0	0	0
T70	697764	0	0	0
T71	244930	0	0	0
T72	631288	0	0	0
T73	39388	1	0	0
T78	0	1	0	0
T82	0	3	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	1460310	0	0	0
T91	452854	0	0	0
T92	45050	0	0	0
T93	753170	0	0	0
T94	35570	0	0	0
T95	30319	0	0	0
T96	122431	0	0	0
T97	100803	0	0	0
T98	15818	0	0	0
T99	625337	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5762	0	0
T10	133660	1429	0	0
T11	0	1393	0	0
T12	0	708	0	0
T28	1901344	0	0	0
T29	818584	0	0	0
T35	0	1496	0	0
T36	0	736	0	0
T37	482392	0	0	0
T38	41700	0	0	0
T39	143740	0	0	0
T40	486124	0	0	0
T41	1360472	0	0	0
T42	2231044	0	0	0
T43	92088	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4802	0	0
T10	133660	1189	0	0
T11	0	1153	0	0
T12	0	588	0	0
T28	1901344	0	0	0
T29	818584	0	0	0
T35	0	1256	0	0
T36	0	616	0	0
T37	482392	0	0	0
T38	41700	0	0	0
T39	143740	0	0	0
T40	486124	0	0	0
T41	1360472	0	0	0
T42	2231044	0	0	0
T43	92088	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	90504	90236	0	0
T2	27004	26688	0	0
T3	361840	361516	0	0
T4	707392	707356	0	0
T5	1524700	1524676	0	0
T6	1089748	1089708	0	0
T17	140428	140104	0	0
T18	95500	95244	0	0
T19	11552	11288	0	0
T20	104108	103812	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T22
1	0	1	Covered	T2,T4,T21
1	1	0	Covered	T22,T100,T31
1	1	1	Covered	T20,T31,T26

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T31,T26
0	1	Covered	T23,T32,T52
1	0	Covered	T26,T25,T51

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T31,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T25,T51

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T31,T26
1	0	Not Covered
1	1	Covered	T23,T32,T52

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T15,T48,T49

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T17
1	Covered	T4,T9,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T3,T15,T46

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T9
1	Covered	T3,T5,T17

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T17,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T46

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T5
Phase1St	193	Covered	T3,T4,T5
Phase2St	210	Covered	T3,T4,T5
Phase3St	228	Covered	T3,T4,T5
TerminalSt	244	Covered	T3,T4,T5
TimeoutSt	154	Covered	T20,T31,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T3,T4,T5
IdleSt->TimeoutSt	154	Covered	T20,T31,T26
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T28,T30,T101
Phase0St->Phase1St	193	Covered	T3,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T54,T56,T59
Phase1St->Phase2St	210	Covered	T3,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T32,T80,T58
Phase2St->Phase3St	228	Covered	T3,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T33,T59,T102
Phase3St->TerminalSt	244	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T15,T31
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T20,T31,T23
TimeoutSt->Phase0St	167	Covered	T26,T23,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T31,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T23,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T31,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T31,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T54,T56,T59
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T80,T58
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T59,T102
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T15,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662240471	307	0	0
CheckAccumTrig0_A	662240471	497	0	0
CheckAccumTrig1_A	662240471	30	0	0
CheckClr_A	662240471	216	0	0
CheckEn_A	662098084	258032485	0	0
CheckPhase0_A	662240471	563	0	0
CheckPhase1_A	662240471	557	0	0
CheckPhase2_A	662240471	545	0	0
CheckPhase3_A	662240471	533	0	0
CheckTimeout0_A	662240471	575	0	0
CheckTimeoutSt1_A	662240471	85823	0	0
CheckTimeoutSt2_A	662240471	494	0	0
CheckTimeoutStTrig_A	662240471	50	0	0
ErrorStAllEscAsserted_A	662240471	1427	0	0
ErrorStIsTerminal_A	662240471	1187	0	0
u_state_regs_A	662240471	662070422	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	307	0	0
T10	33415	78	0	0
T11	0	67	0	0
T12	0	47	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	83	0	0
T36	0	32	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	497	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T9	0	1	0	0
T15	0	3	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	30	0	0
T23	23972	0	0	0
T24	36475	0	0	0
T25	0	1	0	0
T26	25512	1	0	0
T41	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T63	198078	0	0	0
T64	2692	0	0	0
T65	521111	0	0	0
T66	36112	0	0	0
T67	156637	0	0	0
T68	16364	0	0	0
T69	548938	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	216	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T15	0	2	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T31	0	1	0	0
T32	0	1	0	0
T51	0	2	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662098084	258032485	0	0
T1	22626	22558	0	0
T2	6751	586	0	0
T3	90460	6609	0	0
T4	176848	14423	0	0
T5	381175	8696	0	0
T6	272437	272427	0	0
T17	35107	2094	0	0
T18	23875	23810	0	0
T19	2888	2156	0	0
T20	26027	2119	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	563	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T9	0	1	0	0
T15	0	3	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	557	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T9	0	1	0	0
T15	0	3	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	545	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T9	0	1	0	0
T15	0	3	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	533	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T9	0	1	0	0
T15	0	3	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	575	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	4	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T23	0	2	0	0
T25	0	3	0	0
T26	0	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	0	5	0	0
T76	0	9	0	0
T79	18371	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	85823	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	501	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T23	0	255	0	0
T25	0	85	0	0
T26	0	3	0	0
T31	0	37	0	0
T32	0	236	0	0
T50	0	353	0	0
T51	0	1	0	0
T52	0	298	0	0
T76	0	496	0	0
T79	18371	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	494	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	4	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T31	0	1	0	0
T50	0	4	0	0
T52	0	2	0	0
T54	0	23	0	0
T76	0	9	0	0
T79	18371	0	0	0
T80	0	4	0	0
T81	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	50	0	0
T23	23972	1	0	0
T24	36475	0	0	0
T25	181163	0	0	0
T28	0	2	0	0
T32	0	2	0	0
T52	0	2	0	0
T54	0	1	0	0
T68	16364	0	0	0
T69	548938	0	0	0
T70	348882	0	0	0
T71	122465	0	0	0
T72	315644	0	0	0
T82	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	730155	0	0	0
T91	226427	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1427	0	0
T10	33415	353	0	0
T11	0	356	0	0
T12	0	200	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	353	0	0
T36	0	165	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1187	0	0
T10	33415	293	0	0
T11	0	296	0	0
T12	0	170	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	293	0	0
T36	0	135	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	662070422	0	0
T1	22626	22559	0	0
T2	6751	6672	0	0
T3	90460	90379	0	0
T4	176848	176839	0	0
T5	381175	381169	0	0
T6	272437	272427	0	0
T17	35107	35026	0	0
T18	23875	23811	0	0
T19	2888	2822	0	0
T20	26027	25953	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T17
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T17

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T5,T17

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T22
1	0	1	Covered	T5,T17,T7
1	1	0	Covered	T3,T17,T22
1	1	1	Covered	T20,T24,T25

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T24,T25
0	1	Covered	T50,T73,T52
1	0	Covered	T61,T34,T62

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T24,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T61,T34,T62

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T24,T25
1	0	Not Covered
1	1	Covered	T50,T73,T52

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T6
1	Covered	T5,T8,T22

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T17,T6,T14

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T17
1	Covered	T7,T45,T46

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T5,T17,T6
1	Covered	T3,T44,T26

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T7,T14

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T17,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T5,T6,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T5,T17
Phase1St	193	Covered	T3,T5,T17
Phase2St	210	Covered	T3,T5,T17
Phase3St	228	Covered	T3,T5,T17
TerminalSt	244	Covered	T3,T5,T17
TimeoutSt	154	Covered	T20,T24,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T3,T5,T17
IdleSt->TimeoutSt	154	Covered	T20,T24,T25
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T101,T103,T104
Phase0St->Phase1St	193	Covered	T3,T5,T17
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T25,T60,T105
Phase1St->Phase2St	210	Covered	T3,T5,T17
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T25,T106,T56
Phase2St->Phase3St	228	Covered	T3,T5,T17
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T107,T108,T61
Phase3St->TerminalSt	244	Covered	T3,T5,T17
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T17,T49,T67
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T20,T24,T25
TimeoutSt->Phase0St	167	Covered	T50,T73,T52

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T24,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T50,T73,T52
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T24,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T24,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T101,T103,T104
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T5,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T5,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T60,T105
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T5,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T5,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T25,T106,T56
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T5,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T107,T108,T61
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T5,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T5,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T49,T67
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T5,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662240471	242	0	0
CheckAccumTrig0_A	662240471	473	0	0
CheckAccumTrig1_A	662240471	17	0	0
CheckClr_A	662240471	199	0	0
CheckEn_A	662098084	281883520	0	0
CheckPhase0_A	662240471	540	0	0
CheckPhase1_A	662240471	531	0	0
CheckPhase2_A	662240471	520	0	0
CheckPhase3_A	662240471	511	0	0
CheckTimeout0_A	662240471	657	0	0
CheckTimeoutSt1_A	662240471	87251	0	0
CheckTimeoutSt2_A	662240471	584	0	0
CheckTimeoutStTrig_A	662240471	55	0	0
ErrorStAllEscAsserted_A	662240471	1426	0	0
ErrorStIsTerminal_A	662240471	1186	0	0
u_state_regs_A	662240471	662070422	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	242	0	0
T10	33415	57	0	0
T11	0	66	0	0
T12	0	27	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	60	0	0
T36	0	32	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	473	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	1	0	0
T6	272437	1	0	0
T7	662619	1	0	0
T8	0	1	0	0
T14	0	1	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	17	0	0
T34	203122	1	0	0
T61	572474	1	0	0
T62	0	1	0	0
T102	430806	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	118634	0	0	0
T117	359802	0	0	0
T118	22803	0	0	0
T119	90018	0	0	0
T120	60755	0	0	0
T121	128808	0	0	0
T122	634436	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	199	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T23	0	2	0	0
T25	0	4	0	0
T32	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T67	0	1	0	0
T72	0	3	0	0
T92	0	2	0	0
T123	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662098084	281883520	0	0
T1	22626	3119	0	0
T2	6751	5524	0	0
T3	90460	12021	0	0
T4	176848	176083	0	0
T5	381175	3175	0	0
T6	272437	40101	0	0
T17	35107	27408	0	0
T18	23875	23810	0	0
T19	2888	2174	0	0
T20	26027	2140	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	540	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	1	0	0
T6	272437	1	0	0
T7	662619	1	0	0
T8	0	1	0	0
T14	0	1	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	531	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	1	0	0
T6	272437	1	0	0
T7	662619	1	0	0
T8	0	1	0	0
T14	0	1	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	520	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	1	0	0
T6	272437	1	0	0
T7	662619	1	0	0
T8	0	1	0	0
T14	0	1	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	511	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	1	0	0
T6	272437	1	0	0
T7	662619	1	0	0
T8	0	1	0	0
T14	0	1	0	0
T17	35107	1	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	657	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T24	0	2	0	0
T25	0	2	0	0
T33	0	4	0	0
T50	0	80	0	0
T52	0	2	0	0
T71	0	1	0	0
T73	0	2	0	0
T75	0	1	0	0
T76	0	11	0	0
T79	18371	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	87251	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	110	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T24	0	366	0	0
T25	0	71	0	0
T33	0	879	0	0
T50	0	8497	0	0
T52	0	972	0	0
T71	0	39	0	0
T73	0	193	0	0
T75	0	158	0	0
T76	0	652	0	0
T79	18371	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	584	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T24	0	2	0	0
T25	0	2	0	0
T33	0	4	0	0
T50	0	79	0	0
T52	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	11	0	0
T79	18371	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	55	0	0
T28	0	3	0	0
T32	171756	0	0	0
T50	333861	1	0	0
T51	11396	0	0	0
T52	0	1	0	0
T73	39388	1	0	0
T78	0	1	0	0
T82	0	1	0	0
T94	35570	0	0	0
T95	30319	0	0	0
T96	122431	0	0	0
T97	100803	0	0	0
T98	15818	0	0	0
T99	625337	0	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1426	0	0
T10	33415	359	0	0
T11	0	345	0	0
T12	0	173	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	367	0	0
T36	0	182	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1186	0	0
T10	33415	299	0	0
T11	0	285	0	0
T12	0	143	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	307	0	0
T36	0	152	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	662070422	0	0
T1	22626	22559	0	0
T2	6751	6672	0	0
T3	90460	90379	0	0
T4	176848	176839	0	0
T5	381175	381169	0	0
T6	272437	272427	0	0
T17	35107	35026	0	0
T18	23875	23811	0	0
T19	2888	2822	0	0
T20	26027	25953	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T20
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T20

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T14

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T22
1	0	1	Covered	T1,T4,T21
1	1	0	Covered	T22,T31,T24
1	1	1	Covered	T20,T22,T26

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T26
0	1	Covered	T20,T52,T78
1	0	Covered	T52,T75,T55

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T20,T22,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T52,T75,T55

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T26
1	0	Not Covered
1	1	Covered	T20,T52,T78

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T20,T14
1	Covered	T4,T22,T46

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T49,T100,T31

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T22
1	Covered	T3,T20,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T3,T44,T45

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T14,T44

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T20,T44

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T22,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T20,T14,T44

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T20
Phase1St	193	Covered	T3,T4,T20
Phase2St	210	Covered	T3,T4,T20
Phase3St	228	Covered	T3,T4,T20
TerminalSt	244	Covered	T3,T4,T20
TimeoutSt	154	Covered	T20,T22,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T3,T4,T14
IdleSt->TimeoutSt	154	Covered	T20,T22,T26
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T103,T112,T128
Phase0St->Phase1St	193	Covered	T3,T4,T20
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T31,T52,T34
Phase1St->Phase2St	210	Covered	T3,T4,T20
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T31,T106,T129
Phase2St->Phase3St	228	Covered	T3,T4,T20
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T32,T130,T131
Phase3St->TerminalSt	244	Covered	T3,T4,T20
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T3,T22,T31
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T22,T26,T50
TimeoutSt->Phase0St	167	Covered	T20,T52,T75

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T52,T75
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T22,T26,T50
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T103,T112,T128
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T52,T34
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T106,T129
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T130,T131
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T22,T31
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662240471	263	0	0
CheckAccumTrig0_A	662240471	489	0	0
CheckAccumTrig1_A	662240471	19	0	0
CheckClr_A	662240471	211	0	0
CheckEn_A	662098084	302605075	0	0
CheckPhase0_A	662240471	548	0	0
CheckPhase1_A	662240471	540	0	0
CheckPhase2_A	662240471	529	0	0
CheckPhase3_A	662240471	524	0	0
CheckTimeout0_A	662240471	889	0	0
CheckTimeoutSt1_A	662240471	114051	0	0
CheckTimeoutSt2_A	662240471	824	0	0
CheckTimeoutStTrig_A	662240471	45	0	0
ErrorStAllEscAsserted_A	662240471	1437	0	0
ErrorStIsTerminal_A	662240471	1197	0	0
u_state_regs_A	662240471	662070422	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	263	0	0
T10	33415	55	0	0
T11	0	86	0	0
T12	0	29	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	58	0	0
T36	0	35	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	489	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	19	0	0
T52	500310	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T74	10983	0	0	0
T75	0	1	0	0
T89	0	1	0	0
T129	0	3	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	472789	0	0	0
T136	20843	0	0	0
T137	583874	0	0	0
T138	85420	0	0	0
T139	97465	0	0	0
T140	89811	0	0	0
T141	194673	0	0	0
T142	152358	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	211	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T25	0	1	0	0
T31	0	3	0	0
T32	0	2	0	0
T52	0	7	0	0
T63	0	5	0	0
T73	0	3	0	0
T92	0	3	0	0
T99	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662098084	302605075	0	0
T1	22626	17132	0	0
T2	6751	6671	0	0
T3	90460	2121	0	0
T4	176848	9762	0	0
T5	381175	380619	0	0
T6	272437	272427	0	0
T17	35107	35025	0	0
T18	23875	23810	0	0
T19	2888	2183	0	0
T20	26027	2154	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	548	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	540	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	529	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	524	0	0
T3	90460	2	0	0
T4	176848	1	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T14	0	1	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	889	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	63554	1	0	0
T26	0	1	0	0
T50	0	87	0	0
T52	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	18371	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	114051	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	62	0	0
T21	9560	0	0	0
T22	63554	128	0	0
T26	0	136	0	0
T50	0	10502	0	0
T52	0	1234	0	0
T74	0	3	0	0
T76	0	354	0	0
T77	0	190	0	0
T78	0	119	0	0
T79	18371	0	0	0
T81	0	554	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	824	0	0
T15	325387	0	0	0
T16	341840	0	0	0
T22	63554	1	0	0
T26	0	1	0	0
T44	221734	0	0	0
T45	78133	0	0	0
T46	134896	0	0	0
T47	131157	0	0	0
T48	939235	0	0	0
T49	274677	0	0	0
T50	0	87	0	0
T52	0	1	0	0
T54	0	2	0	0
T74	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0
T79	18371	0	0	0
T81	0	4	0	0
T124	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	45	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	1	0	0
T21	9560	0	0	0
T22	63554	0	0	0
T30	0	1	0	0
T41	0	1	0	0
T52	0	2	0	0
T56	0	4	0	0
T78	0	1	0	0
T79	18371	0	0	0
T88	0	1	0	0
T107	0	1	0	0
T126	0	2	0	0
T143	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1437	0	0
T10	33415	346	0	0
T11	0	352	0	0
T12	0	161	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	392	0	0
T36	0	186	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1197	0	0
T10	33415	286	0	0
T11	0	292	0	0
T12	0	131	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	332	0	0
T36	0	156	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	662070422	0	0
T1	22626	22559	0	0
T2	6751	6672	0	0
T3	90460	90379	0	0
T4	176848	176839	0	0
T5	381175	381169	0	0
T6	272437	272427	0	0
T17	35107	35026	0	0
T18	23875	23811	0	0
T19	2888	2822	0	0
T20	26027	25953	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T22
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T3,T22,T100
1	1	1	Covered	T3,T20,T22

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T20,T22
0	1	Covered	T24,T25,T51
1	0	Covered	T3,T22,T50

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T20,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T22,T50

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T20,T22
1	0	Covered	T27,T28
1	1	Covered	T24,T25,T51

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T18,T19,T16

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T14,T22

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T22,T48,T67

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T18,T19,T14
1	Covered	T3,T4,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T5,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T6,T19

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T10,T11,T12
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T3,T4,T5
Phase1St	193	Covered	T3,T4,T5
Phase2St	210	Covered	T3,T4,T5
Phase3St	228	Covered	T3,T4,T5
TerminalSt	244	Covered	T3,T4,T5
TimeoutSt	154	Covered	T3,T20,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T10,T11,T12
IdleSt->Phase0St	147	Covered	T4,T5,T6
IdleSt->TimeoutSt	154	Covered	T3,T20,T22
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T29,T143,T34
Phase0St->Phase1St	193	Covered	T3,T4,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T4,T14,T80
Phase1St->Phase2St	210	Covered	T3,T4,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T6,T56,T58
Phase2St->Phase3St	228	Covered	T3,T4,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T6,T25,T124
Phase3St->TerminalSt	244	Covered	T3,T4,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T6,T14,T22
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T20,T22,T25
TimeoutSt->Phase0St	167	Covered	T3,T22,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T22,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T22,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T103,T144
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T14,T80
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T58,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T25,T82
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T6,T14,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	662240471	320	0	0
CheckAccumTrig0_A	662240471	815	0	0
CheckAccumTrig1_A	662240471	52	0	0
CheckClr_A	662240471	389	0	0
CheckEn_A	662098084	231295967	0	0
CheckPhase0_A	662240471	919	0	0
CheckPhase1_A	662240471	897	0	0
CheckPhase2_A	662240471	882	0	0
CheckPhase3_A	662240471	857	0	0
CheckTimeout0_A	662240471	800	0	0
CheckTimeoutSt1_A	662240471	85174	0	0
CheckTimeoutSt2_A	662240471	682	0	0
CheckTimeoutStTrig_A	662240471	65	0	0
ErrorStAllEscAsserted_A	662240471	1472	0	0
ErrorStIsTerminal_A	662240471	1232	0	0
u_state_regs_A	662240471	662070422	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	320	0	0
T10	33415	74	0	0
T11	0	83	0	0
T12	0	34	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	95	0	0
T36	0	34	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	815	0	0
T4	176848	2	0	0
T5	381175	1	0	0
T6	272437	7	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	1	0	0
T19	2888	1	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	52	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T43	0	1	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	3	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	389	0	0
T4	176848	1	0	0
T5	381175	0	0	0
T6	272437	6	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T14	0	2	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	2	0	0
T25	0	2	0	0
T26	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T66	0	1	0	0
T67	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662098084	231295967	0	0
T1	22626	3086	0	0
T2	6751	5976	0	0
T3	90460	29430	0	0
T4	176848	6378	0	0
T5	381175	8619	0	0
T6	272437	5874	0	0
T17	35107	35025	0	0
T18	23875	2007	0	0
T19	2888	2141	0	0
T20	26027	2112	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	919	0	0
T3	90460	1	0	0
T4	176848	2	0	0
T5	381175	1	0	0
T6	272437	7	0	0
T7	662619	0	0	0
T14	0	3	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	1	0	0
T19	2888	1	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	2	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	897	0	0
T3	90460	1	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	7	0	0
T7	662619	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	1	0	0
T19	2888	1	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	2	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	882	0	0
T3	90460	1	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	5	0	0
T7	662619	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	1	0	0
T19	2888	1	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	2	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	857	0	0
T3	90460	1	0	0
T4	176848	1	0	0
T5	381175	1	0	0
T6	272437	4	0	0
T7	662619	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T17	35107	0	0	0
T18	23875	1	0	0
T19	2888	1	0	0
T20	26027	0	0	0
T21	9560	0	0	0
T22	0	2	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	800	0	0
T3	90460	1	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	3	0	0
T21	9560	0	0	0
T22	0	3	0	0
T24	0	1	0	0
T25	0	2	0	0
T32	0	2	0	0
T50	0	5	0	0
T51	0	1	0	0
T72	0	1	0	0
T76	0	11	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	85174	0	0
T3	90460	4	0	0
T4	176848	0	0	0
T5	381175	0	0	0
T6	272437	0	0	0
T7	662619	0	0	0
T17	35107	0	0	0
T18	23875	0	0	0
T19	2888	0	0	0
T20	26027	401	0	0
T21	9560	0	0	0
T22	0	168	0	0
T24	0	150	0	0
T25	0	44	0	0
T32	0	61	0	0
T50	0	264	0	0
T51	0	848	0	0
T72	0	154	0	0
T76	0	708	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	682	0	0
T7	662619	0	0	0
T8	421875	0	0	0
T9	817099	0	0	0
T13	32873	0	0	0
T14	228184	0	0	0
T15	325387	0	0	0
T20	26027	3	0	0
T21	9560	0	0	0
T22	63554	2	0	0
T25	0	1	0	0
T27	0	1	0	0
T32	0	1	0	0
T50	0	4	0	0
T54	0	7	0	0
T72	0	1	0	0
T76	0	11	0	0
T79	18371	0	0	0
T82	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	65	0	0
T24	36475	1	0	0
T25	181163	1	0	0
T29	0	1	0	0
T41	0	1	0	0
T50	333861	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T70	348882	0	0	0
T71	122465	0	0	0
T72	315644	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	1	0	0
T90	730155	0	0	0
T91	226427	0	0	0
T92	45050	0	0	0
T93	753170	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1472	0	0
T10	33415	371	0	0
T11	0	340	0	0
T12	0	174	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	384	0	0
T36	0	203	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	1232	0	0
T10	33415	311	0	0
T11	0	280	0	0
T12	0	144	0	0
T28	475336	0	0	0
T29	204646	0	0	0
T35	0	324	0	0
T36	0	173	0	0
T37	120598	0	0	0
T38	10425	0	0	0
T39	35935	0	0	0
T40	121531	0	0	0
T41	340118	0	0	0
T42	557761	0	0	0
T43	23022	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	662240471	662070422	0	0
T1	22626	22559	0	0
T2	6751	6672	0	0
T3	90460	90379	0	0
T4	176848	176839	0	0
T5	381175	381169	0	0
T6	272437	272427	0	0
T17	35107	35026	0	0
T18	23875	23811	0	0
T19	2888	2822	0	0
T20	26027	25953	0	0