Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	92407	1			T17	22		T21	5076		T22	3280
class_i[0x1]	55447	1			T4	11		T17	871		T21	1
class_i[0x2]	37815	1			T2	4		T3	44		T17	5346
class_i[0x3]	62443	1			T2	4		T4	1		T22	79

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63755	1			T2	2		T3	17		T4	1
alert[0x1]	61458	1			T3	15		T4	6		T17	1265
alert[0x2]	59537	1			T2	6		T3	7		T17	2250
alert[0x3]	63362	1			T3	5		T4	5		T17	1364

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

247862

1

T2

4

T3

44

T4

12

esc_ping_fail

250

1

T2

4

T8

2

T9

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	63680	1			T3	17		T4	1		T17	1360
esc_integrity_fail	alert[0x1]	61398	1			T3	15		T4	6		T17	1265
esc_integrity_fail	alert[0x2]	59479	1			T2	4		T3	7		T17	2250
esc_integrity_fail	alert[0x3]	63305	1			T3	5		T4	5		T17	1364
esc_ping_fail	alert[0x0]	75	1			T2	2		T8	1		T9	3
esc_ping_fail	alert[0x1]	60	1			T307	1		T70	1		T73	2
esc_ping_fail	alert[0x2]	58	1			T2	2		T9	2		T307	1
esc_ping_fail	alert[0x3]	57	1			T8	1		T9	3		T307	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	92347	1			T17	22		T21	5076		T22	3280
esc_integrity_fail	class_i[0x1]	55399	1			T4	11		T17	871		T21	1
esc_integrity_fail	class_i[0x2]	37743	1			T2	4		T3	44		T17	5346
esc_integrity_fail	class_i[0x3]	62373	1			T4	1		T22	79		T29	4
esc_ping_fail	class_i[0x0]	60	1			T8	2		T307	3		T70	3
esc_ping_fail	class_i[0x1]	48	1			T9	6		T70	1		T72	4
esc_ping_fail	class_i[0x2]	72	1			T9	1		T301	1		T297	7
esc_ping_fail	class_i[0x3]	70	1			T2	4		T9	1		T307	1