Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	701372543	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	701372543	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	701372543	701200975	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	701372543	701200975	0	0
tb.dut.EdnKnownO_A	0	0	701372543	701200975	0	0
tb.dut.EscPKnownO_A	0	0	701372543	701200975	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	701372543	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	701372543	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	701372543	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	701372543	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	701372543	80	0	0
tb.dut.IrqAKnownO_A	0	0	701372543	701200975	0	0
tb.dut.IrqBKnownO_A	0	0	701372543	701200975	0	0
tb.dut.IrqCKnownO_A	0	0	701372543	701200975	0	0
tb.dut.IrqDKnownO_A	0	0	701372543	701200975	0	0
tb.dut.TlAReadyKnownO_A	0	0	701372543	701200975	0	0
tb.dut.TlDValidKnownO_A	0	0	701372543	701200975	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	728844627	2860197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	728844627	19085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	728844627	19585	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	728844627	17980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	728844627	19596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	728844627	20459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	728844627	19669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	728844627	17794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	728844627	18105	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	728844627	19497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	728844627	18869	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	728844627	18546	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	728844627	19977	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	728844627	17565	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	728844627	19141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	728844627	18573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	728844627	18867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	728844627	17822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	728844627	18748	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	728844627	19729	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	728844627	19664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	728844627	19082	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	728844627	18300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	728844627	19079	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	728844627	19925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	728844627	19017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	728844627	18142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	728844627	20654	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	728844627	17542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	728844627	17870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	728844627	19983	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	728844627	19179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	728844627	18141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	728844627	17223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	728844627	17921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	728844627	17698	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	728844627	18205	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	728844627	19162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	728844627	17966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	728844627	19015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	728844627	19143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	728844627	20325	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	728844627	20085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	728844627	19763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	728844627	18798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	728844627	18362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	728844627	19010	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	728844627	20375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	728844627	19063	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	728844627	20101	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	728844627	17866	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	728844627	20214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	728844627	18942	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	728844627	18361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	728844627	20741	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	728844627	19030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	728844627	17739	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	728844627	19443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	728844627	18712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	728844627	19218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	728844627	21593	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	728844627	19688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	728844627	18998	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	728844627	18939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	728844627	18945	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	728844627	18895	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	728844627	18819	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	728844627	19858	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	728844627	19053	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	728844627	19581	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	728844627	37783	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	728844627	19208	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	728844627	19060	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	728844627	19652	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	728844627	18789	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	728844627	18553	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	728844627	19461	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	728844627	17469	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	728844627	20714	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	701372543	1154	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	701372543	194072	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	701372543	355465809	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	701372543	277	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	701372543	730	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	701372543	41	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	701372543	315	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	701180638	243081837	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	701372543	820	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	701372543	804	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	701372543	782	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	701372543	771	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	701372543	2074	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	701372543	194288	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	701372543	1969	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	701372543	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701372543	1448	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	701372543	1208	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	701372543	701200975	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	701372543	5563	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	701372543	177368	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	701372543	412127459	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	701372543	284	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	701372543	499	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	701372543	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	701372543	218	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	701180638	322100996	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	701372543	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	701372543	551	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	701372543	534	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	701372543	523	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	701372543	1501	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	701372543	133393	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	701372543	1422	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	701372543	57	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701372543	1492	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	701372543	1252	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	701372543	701200975	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	701372543	1667	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	701372543	178070	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	701372543	398524496	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	701372543	296	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	701372543	465	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	701372543	17	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	701372543	187	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	701180638	327687150	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	701372543	523	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	701372543	517	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	701372543	507	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	701372543	499	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	701372543	812	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	701372543	87326	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	701372543	744	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	701372543	50	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701372543	1464	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	701372543	1224	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	701372543	701200975	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	701372543	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	701372543	3090	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	701372543	203656	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	701372543	414552543	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	701372543	301	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	701372543	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	701372543	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	701372543	262	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	701180638	310696610	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	701372543	602	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	701372543	584	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	701372543	572	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	701372543	563	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	701372543	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	701372543	59524	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	701372543	436	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	701372543	55	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	701372543	1442	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	701372543	1202	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	701372543	701200975	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	728844627	134248258	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	728844627	728195455	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	728844627	728195455	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	728844627	202918003	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	728844627	728195455	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	728844627	728195455	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	831	831	0	0
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