Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	166	1			T2	1		T17	1		T22	1
index[0x1]	165	1			T17	1		T22	3		T48	1
index[0x2]	181	1			T17	2		T21	1		T29	1
index[0x3]	209	1			T21	1		T49	1		T14	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	232	1			T17	1		T22	1		T48	1
lens_less_than_1000[1]	137	1			T50	1		T31	1		T78	1
lens_less_than_1000[2]	94	1			T17	1		T15	1		T26	1
lens_less_than_1000[3]	83	1			T21	1		T29	2		T51	1
lens_less_than_1000[4]	70	1			T22	2		T16	2		T76	1
lens_less_than_1000[5]	36	1			T17	2		T214	1		T105	2
lens_less_than_1000[6]	28	1			T22	1		T54	1		T35	1
lens_less_than_1000[7]	18	1			T2	1		T21	1		T14	1
lens_less_than_1000[8]	6	1			T95	1		T64	1		T270	1
lens_less_than_1000[9]	5	1			T86	1		T271	1		T272	1
len_2	12	1			T91	1		T57	1		T93	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2]]	[lens_less_than_1000[8]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	56	1			T15	1		T33	2		T36	1
index[0x0]	lens_less_than_1000[1]	27	1			T25	1		T27	1		T88	1
index[0x0]	lens_less_than_1000[2]	20	1			T17	1		T25	1		T27	2
index[0x0]	lens_less_than_1000[3]	22	1			T29	1		T85	1		T56	1
index[0x0]	lens_less_than_1000[4]	9	1			T22	1		T273	1		T105	1
index[0x0]	lens_less_than_1000[5]	13	1			T214	1		T105	1		T45	1
index[0x0]	lens_less_than_1000[6]	6	1			T35	1		T274	1		T112	3
index[0x0]	lens_less_than_1000[7]	5	1			T2	1		T60	1		T111	1
index[0x0]	lens_less_than_1000[8]	3	1			T95	1		T270	1		T265	1
index[0x0]	lens_less_than_1000[9]	1	1			T275	1		-	-		-	-
index[0x0]	len_2	4	1			T91	1		T93	1		T276	1
index[0x1]	lens_less_than_1000[0]	58	1			T22	1		T48	1		T277	1
index[0x1]	lens_less_than_1000[1]	32	1			T27	1		T33	1		T69	1
index[0x1]	lens_less_than_1000[2]	16	1			T25	1		T35	2		T62	1
index[0x1]	lens_less_than_1000[3]	15	1			T27	1		T119	1		T93	1
index[0x1]	lens_less_than_1000[4]	19	1			T22	1		T212	1		T69	1
index[0x1]	lens_less_than_1000[5]	8	1			T17	1		T278	1		T63	1
index[0x1]	lens_less_than_1000[6]	9	1			T22	1		T54	1		T96	3
index[0x1]	lens_less_than_1000[7]	4	1			T103	1		T222	1		T279	1
index[0x1]	lens_less_than_1000[8]	1	1			T280	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T281	1		-	-		-	-
index[0x1]	len_2	2	1			T57	1		T282	1		-	-
index[0x2]	lens_less_than_1000[0]	54	1			T17	1		T9	1		T79	1
index[0x2]	lens_less_than_1000[1]	33	1			T33	1		T60	1		T219	1
index[0x2]	lens_less_than_1000[2]	25	1			T88	1		T35	1		T283	1
index[0x2]	lens_less_than_1000[3]	28	1			T21	1		T29	1		T51	1
index[0x2]	lens_less_than_1000[4]	12	1			T76	1		T86	1		T273	1
index[0x2]	lens_less_than_1000[5]	9	1			T17	1		T105	1		T278	1
index[0x2]	lens_less_than_1000[6]	9	1			T122	3		T127	1		T284	1
index[0x2]	lens_less_than_1000[7]	5	1			T201	1		T256	1		T285	1
index[0x2]	lens_less_than_1000[9]	3	1			T86	1		T271	1		T272	1
index[0x2]	len_2	3	1			T286	1		T287	1		T288	1
index[0x3]	lens_less_than_1000[0]	64	1			T49	1		T15	1		T52	3
index[0x3]	lens_less_than_1000[1]	45	1			T50	1		T31	1		T78	1
index[0x3]	lens_less_than_1000[2]	33	1			T15	1		T26	1		T33	1
index[0x3]	lens_less_than_1000[3]	18	1			T77	1		T85	1		T219	1
index[0x3]	lens_less_than_1000[4]	30	1			T16	2		T31	1		T27	1
index[0x3]	lens_less_than_1000[5]	6	1			T289	1		T97	2		T121	1
index[0x3]	lens_less_than_1000[6]	4	1			T112	4		-	-		-	-
index[0x3]	lens_less_than_1000[7]	4	1			T21	1		T14	1		T279	1
index[0x3]	lens_less_than_1000[8]	2	1			T64	1		T280	1		-	-
index[0x3]	len_2	3	1			T126	2		T288	1		-	-