Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.04	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	7	33	82.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	7	33	82.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T17	1		T79	1		T88	1
class_index[0x1]	57	1			T17	1		T15	1		T27	1
class_index[0x2]	50	1			T25	1		T33	1		T88	1
class_index[0x3]	55	1			T17	1		T25	2		T119	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	92	1			T17	2		T15	1		T25	2
intr_timeout_cnt[1]	49	1			T119	1		T105	1		T94	1
intr_timeout_cnt[2]	19	1			T35	1		T60	1		T93	1
intr_timeout_cnt[3]	9	1			T88	1		T35	1		T252	1
intr_timeout_cnt[4]	15	1			T89	2		T96	1		T253	1
intr_timeout_cnt[5]	8	1			T25	1		T116	1		T254	1
intr_timeout_cnt[6]	7	1			T124	1		T252	2		T104	1
intr_timeout_cnt[7]	13	1			T17	1		T92	1		T95	1
intr_timeout_cnt[8]	6	1			T93	1		T118	1		T68	1
intr_timeout_cnt[9]	5	1			T92	1		T255	1		T68	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	7	33	82.50	7

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[4] , intr_timeout_cnt[5]]	--	--	2
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T79	1		T35	6		T91	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T97	1		T256	1		T257	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T35	1		T60	1		T96	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T88	1		T258	1		T259	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T104	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T17	1		T95	1		T127	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T118	1		T68	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T17	1		T15	1		T27	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T94	1		T28	1		T260	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T93	1		T45	1		T254	1
class_index[0x1]	intr_timeout_cnt[4]	7	1			T89	2		T96	1		T253	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T261	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	6	1			T124	1		T252	2		T262	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T263	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T127	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T262	1		T113	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T25	1		T33	1		T88	1
class_index[0x2]	intr_timeout_cnt[1]	8	1			T124	1		T264	1		T252	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T117	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	1	1			T252	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T107	1		T262	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	5	1			T254	1		T266	1		T267	2
class_index[0x2]	intr_timeout_cnt[7]	6	1			T92	1		T113	1		T261	2
class_index[0x2]	intr_timeout_cnt[8]	3	1			T93	1		T257	1		T104	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T255	1		T68	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T17	1		T25	1		T120	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T119	1		T105	1		T127	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T95	1		T266	1		T268	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T35	1		T269	1		T266	1
class_index[0x3]	intr_timeout_cnt[4]	6	1			T125	3		T270	1		T127	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T25	1		T116	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T265	1		T113	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T92	1		-	-		-	-