Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	356186	1			T1	7		T2	51		T3	9
all_values[1]	356186	1			T1	7		T2	51		T3	9
all_values[2]	356186	1			T1	7		T2	51		T3	9
all_values[3]	356186	1			T1	7		T2	51		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709552

1

T1

18

T3

14

T4

2526

auto[1]

715192

1

T1

10

T2

204

T3

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

849830

1

T1

16

T2

178

T3

7

auto[1]

574914

1

T1

12

T2

26

T3

29

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102338	1			T1	3		T3	1		T4	326
all_values[0]	auto[0]	auto[1]	74738	1			T1	2		T3	5		T4	309
all_values[0]	auto[1]	auto[0]	103913	1			T1	1		T2	50		T3	1
all_values[0]	auto[1]	auto[1]	75197	1			T1	1		T2	1		T3	2
all_values[1]	auto[0]	auto[0]	107319	1			T1	3		T3	1		T4	330
all_values[1]	auto[0]	auto[1]	69976	1			T1	2		T3	1		T4	324
all_values[1]	auto[1]	auto[0]	108775	1			T1	1		T2	33		T4	310
all_values[1]	auto[1]	auto[1]	70116	1			T1	1		T2	18		T3	7
all_values[2]	auto[0]	auto[0]	106989	1			T1	3		T4	314		T5	541
all_values[2]	auto[0]	auto[1]	70546	1			T1	2		T3	3		T4	310
all_values[2]	auto[1]	auto[0]	108073	1			T1	1		T2	50		T3	1
all_values[2]	auto[1]	auto[1]	70578	1			T1	1		T2	1		T3	5
all_values[3]	auto[0]	auto[0]	105574	1			T1	2		T3	1		T4	310
all_values[3]	auto[0]	auto[1]	72072	1			T1	1		T3	2		T4	303
all_values[3]	auto[1]	auto[0]	106849	1			T1	2		T2	45		T3	2
all_values[3]	auto[1]	auto[1]	71691	1			T1	2		T2	6		T3	4