Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	356186	1			T1	7		T2	51		T3	9
all_pins[1]	356186	1			T1	7		T2	51		T3	9
all_pins[2]	356186	1			T1	7		T2	51		T3	9
all_pins[3]	356186	1			T1	7		T2	51		T3	9

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1137162	1			T1	23		T2	178		T3	18
values[0x1]	287582	1			T1	5		T2	26		T3	18
transitions[0x0=>0x1]	191266	1			T1	2		T2	25		T3	9
transitions[0x1=>0x0]	191513	1			T1	3		T2	25		T3	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280989	1			T1	6		T2	50		T3	7
all_pins[0]	values[0x1]	75197	1			T1	1		T2	1		T3	2
all_pins[0]	transitions[0x0=>0x1]	74587	1			T2	1		T4	313		T5	2
all_pins[0]	transitions[0x1=>0x0]	71328	1			T1	2		T2	6		T3	3
all_pins[1]	values[0x0]	286070	1			T1	6		T2	33		T3	2
all_pins[1]	values[0x1]	70116	1			T1	1		T2	18		T3	7
all_pins[1]	transitions[0x0=>0x1]	38070	1			T1	1		T2	18		T3	5
all_pins[1]	transitions[0x1=>0x0]	43151	1			T1	1		T2	1		T4	161
all_pins[2]	values[0x0]	285608	1			T1	6		T2	50		T3	4
all_pins[2]	values[0x1]	70578	1			T1	1		T2	1		T3	5
all_pins[2]	transitions[0x0=>0x1]	38784	1			T2	1		T3	1		T4	174
all_pins[2]	transitions[0x1=>0x0]	38322	1			T2	18		T3	3		T4	155
all_pins[3]	values[0x0]	284495	1			T1	5		T2	45		T3	5
all_pins[3]	values[0x1]	71691	1			T1	2		T2	6		T3	4
all_pins[3]	transitions[0x0=>0x1]	39825	1			T1	1		T2	5		T3	3
all_pins[3]	transitions[0x1=>0x0]	38712	1			T3	4		T4	155		T5	322