Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	95386	1			T4	1390		T21	354		T22	323
accum_cnt_1000	232166	1			T4	2218		T5	2240		T17	256
accum_cnt_100	24791	1			T4	109		T5	280		T17	77
accum_cnt_50	76700	1			T2	4		T4	103		T5	256
accum_cnt_10	175199	1			T1	11		T2	87		T4	31
accum_cnt_0	406783	1			T1	5		T2	57		T3	48

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	262689	1			T1	4		T2	37		T3	12
class_index[0x1]	262689	1			T1	4		T2	37		T3	12
class_index[0x2]	262689	1			T1	4		T2	37		T3	12
class_index[0x3]	262689	1			T1	4		T2	37		T3	12

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24941	1			T4	335		T21	354		T22	323
class_index[0x0]	accum_cnt_1000	65761	1			T4	560		T21	493		T22	401
class_index[0x0]	accum_cnt_100	7211	1			T4	30		T21	43		T22	68
class_index[0x0]	accum_cnt_50	23365	1			T4	30		T17	27		T20	5
class_index[0x0]	accum_cnt_10	52488	1			T2	24		T4	8		T17	30
class_index[0x0]	accum_cnt_0	78654	1			T1	4		T2	13		T3	12
class_index[0x1]	accum_cnt_2000	23803	1			T4	395		T14	46		T15	147
class_index[0x1]	accum_cnt_1000	55239	1			T4	513		T5	1110		T17	67
class_index[0x1]	accum_cnt_100	5876	1			T4	25		T5	136		T17	34
class_index[0x1]	accum_cnt_50	15454	1			T2	4		T4	23		T5	140
class_index[0x1]	accum_cnt_10	41161	1			T1	4		T2	31		T4	7
class_index[0x1]	accum_cnt_0	110886	1			T2	2		T3	12		T4	1
class_index[0x2]	accum_cnt_2000	24624	1			T4	267		T14	12		T16	344
class_index[0x2]	accum_cnt_1000	56345	1			T4	628		T17	86		T22	35
class_index[0x2]	accum_cnt_100	6210	1			T4	31		T17	28		T22	35
class_index[0x2]	accum_cnt_50	16197	1			T4	28		T17	32		T22	21
class_index[0x2]	accum_cnt_10	42005	1			T1	3		T4	9		T17	32
class_index[0x2]	accum_cnt_0	109302	1			T1	1		T2	37		T3	12
class_index[0x3]	accum_cnt_2000	22018	1			T4	393		T15	157		T51	380
class_index[0x3]	accum_cnt_1000	54821	1			T4	517		T5	1130		T17	103
class_index[0x3]	accum_cnt_100	5494	1			T4	23		T5	144		T17	15
class_index[0x3]	accum_cnt_50	21684	1			T4	22		T5	116		T17	37
class_index[0x3]	accum_cnt_10	39545	1			T1	4		T2	32		T4	7
class_index[0x3]	accum_cnt_0	107941	1			T2	5		T3	12		T4	2