Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3973	1			T8	1		T29	70		T15	60
alert[0x1]	3734	1			T17	1198		T25	85		T34	12
alert[0x2]	4189	1			T8	1		T15	7		T119	28
alert[0x3]	4309	1			T17	44		T8	1		T29	14
alert[0x4]	7210	1			T15	17		T34	46		T119	71
alert[0x5]	10624	1			T17	131		T15	67		T52	1
alert[0x6]	3873	1			T27	21		T9	1		T33	70
alert[0x7]	5928	1			T2	2		T15	12		T9	1
alert[0x8]	12680	1			T17	811		T31	1		T9	1
alert[0x9]	7191	1			T2	1		T8	1		T15	16
alert[0xa]	4034	1			T33	154		T54	4		T35	16
alert[0xb]	3896	1			T27	155		T33	71		T129	3
alert[0xc]	2123	1			T17	40		T8	1		T15	11
alert[0xd]	3726	1			T17	120		T15	264		T34	617
alert[0xe]	4558	1			T33	468		T34	40		T216	2
alert[0xf]	4443	1			T29	11		T15	53		T25	70
alert[0x10]	6016	1			T15	67		T25	6		T33	36
alert[0x11]	8078	1			T15	138		T25	3		T34	461
alert[0x12]	5955	1			T15	1		T27	11		T33	487
alert[0x13]	6303	1			T17	334		T7	1		T9	1
alert[0x14]	4614	1			T2	1		T29	27		T13	1
alert[0x15]	3620	1			T5	1		T7	2		T33	92
alert[0x16]	2632	1			T2	1		T17	107		T129	4
alert[0x17]	5228	1			T3	1		T17	33		T15	170
alert[0x18]	1644	1			T9	1		T129	17		T273	9
alert[0x19]	5178	1			T17	10		T25	16		T33	20
alert[0x1a]	4191	1			T15	181		T9	1		T33	22
alert[0x1b]	4829	1			T2	1		T17	703		T29	1
alert[0x1c]	13131	1			T2	1		T6	1		T15	125
alert[0x1d]	5521	1			T5	2		T33	1280		T212	1
alert[0x1e]	5161	1			T22	152		T33	237		T34	93
alert[0x1f]	3218	1			T17	84		T25	7		T27	43
alert[0x20]	7939	1			T2	1		T22	106		T15	12
alert[0x21]	6814	1			T2	1		T129	2		T34	462
alert[0x22]	3694	1			T6	1		T9	1		T291	3
alert[0x23]	5556	1			T8	1		T33	306		T34	40
alert[0x24]	6918	1			T33	457		T85	2258		T119	333
alert[0x25]	3707	1			T8	1		T15	48		T34	24
alert[0x26]	10874	1			T17	218		T33	266		T34	7
alert[0x27]	2209	1			T2	1		T25	28		T9	1
alert[0x28]	5515	1			T17	3		T7	2		T15	200
alert[0x29]	9986	1			T15	71		T9	1		T33	234
alert[0x2a]	2836	1			T2	2		T17	81		T25	11
alert[0x2b]	8167	1			T17	1435		T15	424		T25	11
alert[0x2c]	7772	1			T21	2		T8	1		T33	13
alert[0x2d]	4877	1			T2	1		T33	118		T34	28
alert[0x2e]	7299	1			T33	47		T119	16		T35	24
alert[0x2f]	4984	1			T216	5		T54	13		T292	1
alert[0x30]	5290	1			T2	2		T34	87		T291	26
alert[0x31]	7636	1			T2	2		T17	1261		T31	20
alert[0x32]	4800	1			T27	1		T119	40		T292	5
alert[0x33]	4310	1			T2	1		T27	328		T9	1
alert[0x34]	8160	1			T8	1		T33	249		T34	480
alert[0x35]	4058	1			T15	87		T31	1		T25	43
alert[0x36]	8995	1			T17	33		T33	1116		T216	3
alert[0x37]	2271	1			T2	1		T15	4		T25	15
alert[0x38]	5441	1			T2	1		T8	2		T27	10
alert[0x39]	5302	1			T17	165		T15	493		T27	11
alert[0x3a]	14288	1			T33	47		T291	12		T119	4217
alert[0x3b]	8572	1			T3	6		T17	453		T8	1
alert[0x3c]	9196	1			T8	1		T15	261		T27	55
alert[0x3d]	2581	1			T33	151		T119	35		T56	20
alert[0x3e]	4784	1			T15	180		T33	88		T85	15
alert[0x3f]	3152	1			T3	2		T21	1		T33	83
alert[0x40]	4816	1			T2	1		T33	233		T34	98

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77059	1			T2	1		T17	7264		T22	258
class_i[0x1]	114535	1			T2	18		T3	9		T5	1
class_i[0x2]	78314	1			T5	2		T21	3		T8	2
class_i[0x3]	104701	1			T2	2		T29	122		T15	8

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

373993

1

T3

9

T17

7264

T21

3

alert_ping_fail

616

1

T2

21

T5

3

T8

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3961	1			T29	70		T15	60		T54	176
alert_integrity_fail	alert[0x1]	3725	1			T17	1198		T25	85		T34	12
alert_integrity_fail	alert[0x2]	4183	1			T15	7		T119	28		T54	1
alert_integrity_fail	alert[0x3]	4302	1			T17	44		T29	14		T15	19
alert_integrity_fail	alert[0x4]	7199	1			T15	17		T34	46		T119	71
alert_integrity_fail	alert[0x5]	10614	1			T17	131		T15	67		T293	9
alert_integrity_fail	alert[0x6]	3861	1			T27	21		T33	70		T34	1
alert_integrity_fail	alert[0x7]	5915	1			T15	12		T34	298		T291	4
alert_integrity_fail	alert[0x8]	12671	1			T17	811		T31	1		T54	141
alert_integrity_fail	alert[0x9]	7178	1			T15	16		T27	4		T33	460
alert_integrity_fail	alert[0xa]	4026	1			T33	154		T54	4		T35	16
alert_integrity_fail	alert[0xb]	3883	1			T27	155		T33	71		T129	3
alert_integrity_fail	alert[0xc]	2112	1			T17	40		T15	11		T33	28
alert_integrity_fail	alert[0xd]	3715	1			T17	120		T15	264		T34	617
alert_integrity_fail	alert[0xe]	4551	1			T33	468		T34	40		T216	2
alert_integrity_fail	alert[0xf]	4438	1			T29	11		T15	53		T25	70
alert_integrity_fail	alert[0x10]	6008	1			T15	67		T25	6		T33	36
alert_integrity_fail	alert[0x11]	8071	1			T15	138		T25	3		T34	461
alert_integrity_fail	alert[0x12]	5947	1			T15	1		T27	11		T33	487
alert_integrity_fail	alert[0x13]	6289	1			T17	334		T33	10		T88	2
alert_integrity_fail	alert[0x14]	4601	1			T29	27		T15	249		T27	3
alert_integrity_fail	alert[0x15]	3599	1			T33	92		T105	130		T59	22
alert_integrity_fail	alert[0x16]	2624	1			T17	107		T129	4		T85	4
alert_integrity_fail	alert[0x17]	5221	1			T3	1		T17	33		T15	170
alert_integrity_fail	alert[0x18]	1636	1			T129	17		T273	9		T54	16
alert_integrity_fail	alert[0x19]	5169	1			T17	10		T25	16		T33	20
alert_integrity_fail	alert[0x1a]	4182	1			T15	181		T33	22		T35	15
alert_integrity_fail	alert[0x1b]	4821	1			T17	703		T29	1		T15	780
alert_integrity_fail	alert[0x1c]	13118	1			T15	125		T25	5		T27	94
alert_integrity_fail	alert[0x1d]	5510	1			T33	1280		T85	311		T119	171
alert_integrity_fail	alert[0x1e]	5154	1			T22	152		T33	237		T34	93
alert_integrity_fail	alert[0x1f]	3205	1			T17	84		T25	7		T27	43
alert_integrity_fail	alert[0x20]	7933	1			T22	106		T15	12		T25	7
alert_integrity_fail	alert[0x21]	6809	1			T129	2		T34	462		T105	3
alert_integrity_fail	alert[0x22]	3685	1			T291	3		T54	145		T35	5
alert_integrity_fail	alert[0x23]	5547	1			T33	306		T34	40		T56	7
alert_integrity_fail	alert[0x24]	6908	1			T33	457		T85	2258		T119	333
alert_integrity_fail	alert[0x25]	3702	1			T15	48		T34	24		T119	27
alert_integrity_fail	alert[0x26]	10860	1			T17	218		T33	266		T34	7
alert_integrity_fail	alert[0x27]	2199	1			T25	28		T34	126		T54	39
alert_integrity_fail	alert[0x28]	5503	1			T17	3		T15	200		T119	16
alert_integrity_fail	alert[0x29]	9974	1			T15	71		T33	234		T54	133
alert_integrity_fail	alert[0x2a]	2826	1			T17	81		T25	11		T33	87
alert_integrity_fail	alert[0x2b]	8159	1			T17	1435		T15	424		T25	11
alert_integrity_fail	alert[0x2c]	7763	1			T21	2		T33	13		T216	23
alert_integrity_fail	alert[0x2d]	4867	1			T33	118		T34	28		T54	2
alert_integrity_fail	alert[0x2e]	7290	1			T33	47		T119	16		T35	24
alert_integrity_fail	alert[0x2f]	4969	1			T216	5		T54	13		T292	1
alert_integrity_fail	alert[0x30]	5280	1			T34	87		T291	26		T55	9
alert_integrity_fail	alert[0x31]	7616	1			T17	1261		T31	20		T34	12
alert_integrity_fail	alert[0x32]	4792	1			T27	1		T119	40		T292	5
alert_integrity_fail	alert[0x33]	4298	1			T27	328		T34	74		T35	602
alert_integrity_fail	alert[0x34]	8156	1			T33	249		T34	480		T291	3
alert_integrity_fail	alert[0x35]	4044	1			T15	87		T31	1		T25	43
alert_integrity_fail	alert[0x36]	8986	1			T17	33		T33	1116		T216	3
alert_integrity_fail	alert[0x37]	2263	1			T15	4		T25	15		T34	27
alert_integrity_fail	alert[0x38]	5431	1			T27	10		T119	2		T45	18
alert_integrity_fail	alert[0x39]	5297	1			T17	165		T15	493		T27	11
alert_integrity_fail	alert[0x3a]	14282	1			T33	47		T291	12		T119	4217
alert_integrity_fail	alert[0x3b]	8566	1			T3	6		T17	453		T27	171
alert_integrity_fail	alert[0x3c]	9188	1			T15	261		T27	55		T85	10
alert_integrity_fail	alert[0x3d]	2574	1			T33	151		T119	35		T56	20
alert_integrity_fail	alert[0x3e]	4776	1			T15	180		T33	88		T85	15
alert_integrity_fail	alert[0x3f]	3148	1			T3	2		T21	1		T33	83
alert_integrity_fail	alert[0x40]	4813	1			T33	233		T34	98		T291	1
alert_ping_fail	alert[0x0]	12	1			T8	1		T9	1		T218	1
alert_ping_fail	alert[0x1]	9	1			T294	1		T295	1		T296	1
alert_ping_fail	alert[0x2]	6	1			T8	1		T297	1		T298	1
alert_ping_fail	alert[0x3]	7	1			T8	1		T299	1		T300	2
alert_ping_fail	alert[0x4]	11	1			T70	1		T217	1		T301	1
alert_ping_fail	alert[0x5]	10	1			T52	1		T302	1		T303	1
alert_ping_fail	alert[0x6]	12	1			T9	1		T247	1		T299	2
alert_ping_fail	alert[0x7]	13	1			T2	2		T9	1		T72	1
alert_ping_fail	alert[0x8]	9	1			T9	1		T295	1		T304	2
alert_ping_fail	alert[0x9]	13	1			T2	1		T8	1		T73	1
alert_ping_fail	alert[0xa]	8	1			T305	1		T295	1		T306	1
alert_ping_fail	alert[0xb]	13	1			T218	2		T299	1		T301	1
alert_ping_fail	alert[0xc]	11	1			T8	1		T9	1		T72	1
alert_ping_fail	alert[0xd]	11	1			T307	1		T73	1		T297	1
alert_ping_fail	alert[0xe]	7	1			T294	1		T295	1		T296	1
alert_ping_fail	alert[0xf]	5	1			T299	1		T301	1		T297	1
alert_ping_fail	alert[0x10]	8	1			T308	1		T295	1		T309	1
alert_ping_fail	alert[0x11]	7	1			T307	1		T217	1		T41	1
alert_ping_fail	alert[0x12]	8	1			T307	1		T73	1		T310	1
alert_ping_fail	alert[0x13]	14	1			T7	1		T9	1		T73	1
alert_ping_fail	alert[0x14]	13	1			T2	1		T13	1		T311	1
alert_ping_fail	alert[0x15]	21	1			T5	1		T7	2		T307	1
alert_ping_fail	alert[0x16]	8	1			T2	1		T47	1		T312	1
alert_ping_fail	alert[0x17]	7	1			T9	1		T41	1		T294	1
alert_ping_fail	alert[0x18]	8	1			T9	1		T301	1		T294	1
alert_ping_fail	alert[0x19]	9	1			T70	1		T42	1		T301	1
alert_ping_fail	alert[0x1a]	9	1			T9	1		T72	2		T73	1
alert_ping_fail	alert[0x1b]	8	1			T2	1		T72	1		T218	1
alert_ping_fail	alert[0x1c]	13	1			T2	1		T6	1		T299	1
alert_ping_fail	alert[0x1d]	11	1			T5	2		T212	1		T73	2
alert_ping_fail	alert[0x1e]	7	1			T307	1		T297	1		T303	1
alert_ping_fail	alert[0x1f]	13	1			T307	1		T73	1		T299	1
alert_ping_fail	alert[0x20]	6	1			T2	1		T41	1		T313	1
alert_ping_fail	alert[0x21]	5	1			T2	1		T217	1		T302	1
alert_ping_fail	alert[0x22]	9	1			T6	1		T9	1		T70	1
alert_ping_fail	alert[0x23]	9	1			T8	1		T41	1		T296	1
alert_ping_fail	alert[0x24]	10	1			T72	1		T73	1		T303	1
alert_ping_fail	alert[0x25]	5	1			T8	1		T217	1		T218	1
alert_ping_fail	alert[0x26]	14	1			T70	1		T73	1		T314	1
alert_ping_fail	alert[0x27]	10	1			T2	1		T9	1		T217	1
alert_ping_fail	alert[0x28]	12	1			T7	2		T72	1		T73	1
alert_ping_fail	alert[0x29]	12	1			T9	1		T70	1		T73	1
alert_ping_fail	alert[0x2a]	10	1			T2	2		T9	1		T299	1
alert_ping_fail	alert[0x2b]	8	1			T42	1		T299	1		T315	1
alert_ping_fail	alert[0x2c]	9	1			T8	1		T307	1		T70	1
alert_ping_fail	alert[0x2d]	10	1			T2	1		T73	1		T218	1
alert_ping_fail	alert[0x2e]	9	1			T290	1		T299	2		T316	1
alert_ping_fail	alert[0x2f]	15	1			T217	1		T297	1		T302	1
alert_ping_fail	alert[0x30]	10	1			T2	2		T42	1		T301	1
alert_ping_fail	alert[0x31]	20	1			T2	2		T70	1		T72	1
alert_ping_fail	alert[0x32]	8	1			T218	1		T41	1		T297	1
alert_ping_fail	alert[0x33]	12	1			T2	1		T9	1		T73	1
alert_ping_fail	alert[0x34]	4	1			T8	1		T70	1		T300	1
alert_ping_fail	alert[0x35]	14	1			T9	1		T217	1		T301	2
alert_ping_fail	alert[0x36]	9	1			T307	1		T72	2		T41	1
alert_ping_fail	alert[0x37]	8	1			T2	1		T307	1		T70	1
alert_ping_fail	alert[0x38]	10	1			T2	1		T8	2		T314	1
alert_ping_fail	alert[0x39]	5	1			T218	1		T299	1		T300	1
alert_ping_fail	alert[0x3a]	6	1			T299	1		T294	1		T300	1
alert_ping_fail	alert[0x3b]	6	1			T8	1		T301	1		T297	2
alert_ping_fail	alert[0x3c]	8	1			T8	1		T294	2		T310	1
alert_ping_fail	alert[0x3d]	7	1			T294	1		T298	1		T317	1
alert_ping_fail	alert[0x3e]	8	1			T300	1		T302	1		T303	2
alert_ping_fail	alert[0x3f]	4	1			T42	1		T303	1		T318	1
alert_ping_fail	alert[0x40]	3	1			T2	1		T217	1		T319	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	76906	1			T17	7264		T22	258		T15	25
alert_integrity_fail	class_i[0x1]	114414	1			T3	9		T15	8		T31	9
alert_integrity_fail	class_i[0x2]	78160	1			T21	3		T29	1		T15	3976
alert_integrity_fail	class_i[0x3]	104513	1			T29	122		T15	8		T27	1095
alert_ping_fail	class_i[0x0]	153	1			T2	1		T8	9		T7	5
alert_ping_fail	class_i[0x1]	121	1			T2	18		T5	1		T8	2
alert_ping_fail	class_i[0x2]	154	1			T5	2		T8	2		T6	2
alert_ping_fail	class_i[0x3]	188	1			T2	2		T9	15		T307	7