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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.76 99.97 100.00 100.00 99.38 99.44


Total test records in report: 831
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T774 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3627737231 Mar 19 01:34:08 PM PDT 24 Mar 19 01:34:10 PM PDT 24 6058650 ps
T149 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.353949786 Mar 19 01:33:04 PM PDT 24 Mar 19 01:35:32 PM PDT 24 2312735314 ps
T775 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2742092468 Mar 19 01:33:51 PM PDT 24 Mar 19 01:34:15 PM PDT 24 1543491627 ps
T776 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3645589569 Mar 19 01:33:22 PM PDT 24 Mar 19 01:33:56 PM PDT 24 505525420 ps
T777 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4257055724 Mar 19 01:33:21 PM PDT 24 Mar 19 01:33:24 PM PDT 24 38073573 ps
T778 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2692044826 Mar 19 01:33:31 PM PDT 24 Mar 19 01:33:32 PM PDT 24 6448180 ps
T152 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1230014346 Mar 19 01:32:59 PM PDT 24 Mar 19 01:38:07 PM PDT 24 8010388142 ps
T779 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3895687755 Mar 19 01:33:52 PM PDT 24 Mar 19 01:33:58 PM PDT 24 38185713 ps
T780 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2535352057 Mar 19 01:33:19 PM PDT 24 Mar 19 01:33:25 PM PDT 24 77826871 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3182446770 Mar 19 01:33:21 PM PDT 24 Mar 19 01:33:28 PM PDT 24 570451303 ps
T164 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2530342761 Mar 19 01:33:51 PM PDT 24 Mar 19 01:43:22 PM PDT 24 6010568759 ps
T782 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3594906285 Mar 19 01:33:58 PM PDT 24 Mar 19 01:33:59 PM PDT 24 22997343 ps
T783 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.875215951 Mar 19 01:33:57 PM PDT 24 Mar 19 01:34:05 PM PDT 24 67314237 ps
T784 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1730659895 Mar 19 01:33:01 PM PDT 24 Mar 19 01:33:12 PM PDT 24 142630693 ps
T785 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1901448749 Mar 19 01:34:05 PM PDT 24 Mar 19 01:34:07 PM PDT 24 19310480 ps
T786 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.724465702 Mar 19 01:33:59 PM PDT 24 Mar 19 01:34:00 PM PDT 24 10303637 ps
T140 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1674585868 Mar 19 01:33:18 PM PDT 24 Mar 19 01:52:14 PM PDT 24 16117833542 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.406393463 Mar 19 01:32:55 PM PDT 24 Mar 19 01:33:18 PM PDT 24 303220536 ps
T788 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2162463462 Mar 19 01:34:07 PM PDT 24 Mar 19 01:34:08 PM PDT 24 12682284 ps
T789 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1748079745 Mar 19 01:33:35 PM PDT 24 Mar 19 01:33:53 PM PDT 24 1005200833 ps
T790 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4111315801 Mar 19 01:33:24 PM PDT 24 Mar 19 01:33:33 PM PDT 24 291498865 ps
T791 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3073834295 Mar 19 01:33:35 PM PDT 24 Mar 19 01:33:40 PM PDT 24 7297237 ps
T792 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.905103551 Mar 19 01:33:52 PM PDT 24 Mar 19 01:33:59 PM PDT 24 37770720 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2162261818 Mar 19 01:33:08 PM PDT 24 Mar 19 01:33:16 PM PDT 24 59302938 ps
T794 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3377926306 Mar 19 01:33:59 PM PDT 24 Mar 19 01:34:00 PM PDT 24 7409255 ps
T795 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4005497652 Mar 19 01:33:14 PM PDT 24 Mar 19 01:34:07 PM PDT 24 1377872336 ps
T796 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2586092926 Mar 19 01:34:05 PM PDT 24 Mar 19 01:34:06 PM PDT 24 24388405 ps
T188 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3056928108 Mar 19 01:33:35 PM PDT 24 Mar 19 01:34:51 PM PDT 24 9822205236 ps
T797 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.298564438 Mar 19 01:33:14 PM PDT 24 Mar 19 01:33:21 PM PDT 24 293836670 ps
T195 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1531503445 Mar 19 01:33:50 PM PDT 24 Mar 19 01:33:54 PM PDT 24 109478053 ps
T155 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3363760712 Mar 19 01:32:55 PM PDT 24 Mar 19 01:34:24 PM PDT 24 1565820673 ps
T159 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2455255871 Mar 19 01:33:36 PM PDT 24 Mar 19 01:36:55 PM PDT 24 1616681494 ps
T143 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3101029380 Mar 19 01:33:57 PM PDT 24 Mar 19 01:39:55 PM PDT 24 5165606666 ps
T798 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2612934701 Mar 19 01:33:51 PM PDT 24 Mar 19 01:33:55 PM PDT 24 63877223 ps
T799 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4041098076 Mar 19 01:33:09 PM PDT 24 Mar 19 01:39:23 PM PDT 24 19652157935 ps
T166 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3741291143 Mar 19 01:33:50 PM PDT 24 Mar 19 01:41:56 PM PDT 24 5989372616 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.699988830 Mar 19 01:33:52 PM PDT 24 Mar 19 01:34:08 PM PDT 24 1006693311 ps
T801 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.44480463 Mar 19 01:33:04 PM PDT 24 Mar 19 01:34:49 PM PDT 24 6516256996 ps
T157 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.85424193 Mar 19 01:33:10 PM PDT 24 Mar 19 01:53:29 PM PDT 24 279117128031 ps
T156 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1999843946 Mar 19 01:33:42 PM PDT 24 Mar 19 01:36:40 PM PDT 24 10077027868 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2373233015 Mar 19 01:33:08 PM PDT 24 Mar 19 01:35:12 PM PDT 24 15206804965 ps
T165 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2266561758 Mar 19 01:32:56 PM PDT 24 Mar 19 01:39:02 PM PDT 24 2249943113 ps
T803 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.765244157 Mar 19 01:33:59 PM PDT 24 Mar 19 01:34:01 PM PDT 24 9676333 ps
T804 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2768756622 Mar 19 01:33:10 PM PDT 24 Mar 19 01:33:22 PM PDT 24 133943303 ps
T805 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2439594917 Mar 19 01:33:07 PM PDT 24 Mar 19 01:33:34 PM PDT 24 344554715 ps
T806 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.121941627 Mar 19 01:34:04 PM PDT 24 Mar 19 01:34:06 PM PDT 24 13167871 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3886170112 Mar 19 01:33:01 PM PDT 24 Mar 19 01:33:03 PM PDT 24 6628592 ps
T163 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3924327194 Mar 19 01:33:50 PM PDT 24 Mar 19 01:38:59 PM PDT 24 4221384940 ps
T187 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4099686474 Mar 19 01:33:46 PM PDT 24 Mar 19 01:33:48 PM PDT 24 64347266 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.869801509 Mar 19 01:33:02 PM PDT 24 Mar 19 01:33:19 PM PDT 24 1834249121 ps
T809 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.389951063 Mar 19 01:33:51 PM PDT 24 Mar 19 01:33:53 PM PDT 24 22684822 ps
T810 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2068344121 Mar 19 01:33:44 PM PDT 24 Mar 19 01:33:57 PM PDT 24 176744687 ps
T162 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.392110129 Mar 19 01:33:36 PM PDT 24 Mar 19 01:49:56 PM PDT 24 63145619720 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.683398458 Mar 19 01:33:58 PM PDT 24 Mar 19 01:33:59 PM PDT 24 10652931 ps
T167 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.518475129 Mar 19 01:33:16 PM PDT 24 Mar 19 01:35:28 PM PDT 24 8935121388 ps
T812 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4069983052 Mar 19 01:33:58 PM PDT 24 Mar 19 01:33:59 PM PDT 24 6794668 ps
T813 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3642312970 Mar 19 01:33:35 PM PDT 24 Mar 19 01:33:38 PM PDT 24 35675244 ps
T814 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1982247522 Mar 19 01:33:28 PM PDT 24 Mar 19 01:33:34 PM PDT 24 64805663 ps
T815 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3467237983 Mar 19 01:34:07 PM PDT 24 Mar 19 01:34:09 PM PDT 24 12366843 ps
T816 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.709614459 Mar 19 01:33:58 PM PDT 24 Mar 19 01:34:00 PM PDT 24 7731932 ps
T817 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.4120205203 Mar 19 01:33:52 PM PDT 24 Mar 19 01:34:05 PM PDT 24 310897462 ps
T818 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2756724252 Mar 19 01:33:59 PM PDT 24 Mar 19 01:34:08 PM PDT 24 197616642 ps
T819 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1441687327 Mar 19 01:34:02 PM PDT 24 Mar 19 01:34:07 PM PDT 24 63284881 ps
T160 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3688995400 Mar 19 01:33:52 PM PDT 24 Mar 19 01:38:37 PM PDT 24 4865766610 ps
T183 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2607074512 Mar 19 01:33:35 PM PDT 24 Mar 19 01:34:01 PM PDT 24 153436601 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2404266138 Mar 19 01:33:07 PM PDT 24 Mar 19 01:33:32 PM PDT 24 660240317 ps
T821 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.815315275 Mar 19 01:33:41 PM PDT 24 Mar 19 01:33:45 PM PDT 24 25294442 ps
T822 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2731849898 Mar 19 01:33:59 PM PDT 24 Mar 19 01:39:21 PM PDT 24 8599130613 ps
T823 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.597960692 Mar 19 01:34:07 PM PDT 24 Mar 19 01:34:08 PM PDT 24 12559892 ps
T169 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2451012878 Mar 19 01:33:41 PM PDT 24 Mar 19 01:36:09 PM PDT 24 4381148711 ps
T161 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2067718547 Mar 19 01:33:50 PM PDT 24 Mar 19 01:38:53 PM PDT 24 38346796390 ps
T824 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3840270010 Mar 19 01:33:36 PM PDT 24 Mar 19 01:34:02 PM PDT 24 2651919608 ps
T825 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2408975943 Mar 19 01:33:50 PM PDT 24 Mar 19 01:34:11 PM PDT 24 647935683 ps
T826 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2379037486 Mar 19 01:33:58 PM PDT 24 Mar 19 01:34:00 PM PDT 24 6223135 ps
T827 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2712093467 Mar 19 01:33:22 PM PDT 24 Mar 19 01:33:29 PM PDT 24 195438123 ps
T828 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3767278195 Mar 19 01:33:50 PM PDT 24 Mar 19 01:33:56 PM PDT 24 215151544 ps
T829 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1689087891 Mar 19 01:33:35 PM PDT 24 Mar 19 01:33:46 PM PDT 24 152651256 ps
T830 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3115033632 Mar 19 01:34:06 PM PDT 24 Mar 19 01:34:07 PM PDT 24 16049879 ps
T168 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2894502766 Mar 19 01:33:56 PM PDT 24 Mar 19 01:43:11 PM PDT 24 7609554933 ps
T831 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1698888632 Mar 19 01:33:50 PM PDT 24 Mar 19 01:34:26 PM PDT 24 1002839435 ps
T170 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4107406585 Mar 19 01:33:50 PM PDT 24 Mar 19 01:40:03 PM PDT 24 63934901315 ps

Test location /workspace/coverage/default/5.alert_handler_stress_all.858199789
Short name T17
Test name
Test status
Simulation time 121751440736 ps
CPU time 3726.32 seconds
Started Mar 19 02:02:16 PM PDT 24
Finished Mar 19 03:04:23 PM PDT 24
Peak memory 297912 kb
Host smart-934be8ad-f4bd-4153-a406-a8e6d17c5dee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858199789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.858199789
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.479454725
Short name T33
Test name
Test status
Simulation time 66712083165 ps
CPU time 6472.23 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 03:52:44 PM PDT 24
Peak memory 320984 kb
Host smart-2f158775-3920-4281-91c0-801ccf158764
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479454725 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.479454725
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3260959856
Short name T4
Test name
Test status
Simulation time 74801815963 ps
CPU time 1880.52 seconds
Started Mar 19 02:08:20 PM PDT 24
Finished Mar 19 02:39:41 PM PDT 24
Peak memory 272880 kb
Host smart-b1276f0c-92aa-4fc7-aa9f-1501a1336241
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260959856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3260959856
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.715231035
Short name T11
Test name
Test status
Simulation time 484155990 ps
CPU time 27.11 seconds
Started Mar 19 02:02:12 PM PDT 24
Finished Mar 19 02:02:39 PM PDT 24
Peak memory 269648 kb
Host smart-328de921-4217-411d-858d-4e072db59324
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=715231035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.715231035
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1038446411
Short name T172
Test name
Test status
Simulation time 442667759 ps
CPU time 36.22 seconds
Started Mar 19 01:33:49 PM PDT 24
Finished Mar 19 01:34:25 PM PDT 24
Peak memory 245108 kb
Host smart-8f143617-1f1c-49ad-98aa-937ac099f828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1038446411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1038446411
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3232537176
Short name T27
Test name
Test status
Simulation time 474005961934 ps
CPU time 8509.32 seconds
Started Mar 19 02:07:35 PM PDT 24
Finished Mar 19 04:29:25 PM PDT 24
Peak memory 322708 kb
Host smart-ee617f63-df61-46e3-8e84-caa83901bc74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232537176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3232537176
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.419842236
Short name T105
Test name
Test status
Simulation time 64019919715 ps
CPU time 7043.29 seconds
Started Mar 19 02:07:06 PM PDT 24
Finished Mar 19 04:04:32 PM PDT 24
Peak memory 354128 kb
Host smart-ace4176c-6803-4ba1-b1b9-54219e7301c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419842236 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.419842236
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1822633764
Short name T25
Test name
Test status
Simulation time 149505062676 ps
CPU time 4778.49 seconds
Started Mar 19 01:58:59 PM PDT 24
Finished Mar 19 03:18:39 PM PDT 24
Peak memory 338760 kb
Host smart-642aace8-3ae6-4920-a1d9-17bab634ee6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822633764 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1822633764
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3360276126
Short name T132
Test name
Test status
Simulation time 53482124479 ps
CPU time 1011.24 seconds
Started Mar 19 01:32:55 PM PDT 24
Finished Mar 19 01:49:47 PM PDT 24
Peak memory 270692 kb
Host smart-dea38028-debd-4785-97d0-ce4f81dc30f8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360276126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3360276126
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1027038720
Short name T52
Test name
Test status
Simulation time 46800287753 ps
CPU time 1011.81 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:20:02 PM PDT 24
Peak memory 269372 kb
Host smart-1f0557c2-b3d1-4a7b-9714-56b141bdfaf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027038720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1027038720
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3101029380
Short name T143
Test name
Test status
Simulation time 5165606666 ps
CPU time 358.22 seconds
Started Mar 19 01:33:57 PM PDT 24
Finished Mar 19 01:39:55 PM PDT 24
Peak memory 265144 kb
Host smart-1ea09c49-666c-44dc-b0b0-0e702e478136
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3101029380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3101029380
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.884069835
Short name T196
Test name
Test status
Simulation time 1303417192 ps
CPU time 20.16 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:03:22 PM PDT 24
Peak memory 248752 kb
Host smart-82201fb9-784a-4c74-9123-38308c78ef95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=884069835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.884069835
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1471591013
Short name T21
Test name
Test status
Simulation time 20405800608 ps
CPU time 2696.24 seconds
Started Mar 19 02:02:39 PM PDT 24
Finished Mar 19 02:47:36 PM PDT 24
Peak memory 322404 kb
Host smart-59b7e7b4-2c60-4e25-bf61-e322dffb53f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471591013 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1471591013
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3807611422
Short name T104
Test name
Test status
Simulation time 115883378559 ps
CPU time 1764.15 seconds
Started Mar 19 02:03:04 PM PDT 24
Finished Mar 19 02:32:29 PM PDT 24
Peak memory 273516 kb
Host smart-373b10c2-b82d-4403-b5d0-efc2242da977
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807611422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3807611422
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.686890177
Short name T97
Test name
Test status
Simulation time 5221159762 ps
CPU time 389.4 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:09:30 PM PDT 24
Peak memory 265380 kb
Host smart-7dfacadb-c561-426a-9480-ba06382a9921
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686890177 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.686890177
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.202705161
Short name T56
Test name
Test status
Simulation time 93314627601 ps
CPU time 3014.17 seconds
Started Mar 19 02:05:12 PM PDT 24
Finished Mar 19 02:55:27 PM PDT 24
Peak memory 281676 kb
Host smart-c40f2d3e-d42e-4f43-9d7b-543c60366df6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202705161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.202705161
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.85424193
Short name T157
Test name
Test status
Simulation time 279117128031 ps
CPU time 1217.85 seconds
Started Mar 19 01:33:10 PM PDT 24
Finished Mar 19 01:53:29 PM PDT 24
Peak memory 272732 kb
Host smart-ed11cb6d-1192-49b6-97cf-55c5bec2c2a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85424193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.85424193
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1551941143
Short name T244
Test name
Test status
Simulation time 234017258061 ps
CPU time 3332.35 seconds
Started Mar 19 02:08:20 PM PDT 24
Finished Mar 19 03:03:53 PM PDT 24
Peak memory 288868 kb
Host smart-104770a1-7132-4401-858a-ef79a49f8be8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551941143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1551941143
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2455255871
Short name T159
Test name
Test status
Simulation time 1616681494 ps
CPU time 196.41 seconds
Started Mar 19 01:33:36 PM PDT 24
Finished Mar 19 01:36:55 PM PDT 24
Peak memory 264908 kb
Host smart-8e9a3b5f-5e25-4773-ae38-452f3a0cf252
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2455255871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2455255871
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.189804820
Short name T9
Test name
Test status
Simulation time 10331419390 ps
CPU time 415.68 seconds
Started Mar 19 02:06:20 PM PDT 24
Finished Mar 19 02:13:16 PM PDT 24
Peak memory 247092 kb
Host smart-46f7be92-6d89-47ab-8c78-5fcf8d37fab8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189804820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.189804820
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4244633278
Short name T174
Test name
Test status
Simulation time 27954330 ps
CPU time 1.53 seconds
Started Mar 19 01:34:04 PM PDT 24
Finished Mar 19 01:34:06 PM PDT 24
Peak memory 236632 kb
Host smart-b3e721c3-6b55-41f5-9763-5e8298ebb917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4244633278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4244633278
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.84652891
Short name T146
Test name
Test status
Simulation time 17174260178 ps
CPU time 1213.06 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:53:54 PM PDT 24
Peak memory 265400 kb
Host smart-3150f647-a728-44ab-b089-568dc80f05db
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84652891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.84652891
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.4022497379
Short name T5
Test name
Test status
Simulation time 45981945817 ps
CPU time 2757.58 seconds
Started Mar 19 02:03:23 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 289380 kb
Host smart-962e4fef-e564-41e6-8243-fb5708aeb34d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022497379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.4022497379
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2777974619
Short name T35
Test name
Test status
Simulation time 59569401840 ps
CPU time 5246.57 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 03:30:27 PM PDT 24
Peak memory 354504 kb
Host smart-841b31a9-ca6d-4bd7-8286-e0cd5f352f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777974619 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2777974619
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2831766206
Short name T135
Test name
Test status
Simulation time 12763215895 ps
CPU time 1039.92 seconds
Started Mar 19 01:33:04 PM PDT 24
Finished Mar 19 01:50:24 PM PDT 24
Peak memory 272800 kb
Host smart-e8487b31-5aee-4dcb-8b2c-76ee4a48d6e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831766206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2831766206
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3585804948
Short name T2
Test name
Test status
Simulation time 13362858561 ps
CPU time 573.27 seconds
Started Mar 19 02:12:16 PM PDT 24
Finished Mar 19 02:21:50 PM PDT 24
Peak memory 247756 kb
Host smart-fe230c85-23e6-4826-b2e9-1500dd0098d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585804948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3585804948
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2112771752
Short name T7
Test name
Test status
Simulation time 94005377514 ps
CPU time 1216.9 seconds
Started Mar 19 02:02:05 PM PDT 24
Finished Mar 19 02:22:22 PM PDT 24
Peak memory 265340 kb
Host smart-8415f339-4a88-4015-9e2b-05c4e2ec4e40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112771752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2112771752
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3109017502
Short name T342
Test name
Test status
Simulation time 61262431 ps
CPU time 9.82 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 252304 kb
Host smart-c49c2701-349c-422e-8944-2ae7197a78e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109017502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3109017502
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3688995400
Short name T160
Test name
Test status
Simulation time 4865766610 ps
CPU time 284.46 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:38:37 PM PDT 24
Peak memory 270408 kb
Host smart-a50c529c-17ce-4187-95b1-691ff6c0fcd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3688995400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3688995400
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1363456920
Short name T299
Test name
Test status
Simulation time 13244300142 ps
CPU time 522.6 seconds
Started Mar 19 02:05:00 PM PDT 24
Finished Mar 19 02:13:45 PM PDT 24
Peak memory 247848 kb
Host smart-7fa746d3-2476-43ea-9c84-3a72b4383064
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363456920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1363456920
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1067709845
Short name T298
Test name
Test status
Simulation time 177097648601 ps
CPU time 501.62 seconds
Started Mar 19 02:07:58 PM PDT 24
Finished Mar 19 02:16:21 PM PDT 24
Peak memory 247968 kb
Host smart-a4ed00a1-e773-4b16-9296-9bbda385beb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067709845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1067709845
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.64520636
Short name T141
Test name
Test status
Simulation time 7866543275 ps
CPU time 495.81 seconds
Started Mar 19 01:33:31 PM PDT 24
Finished Mar 19 01:41:47 PM PDT 24
Peak memory 267428 kb
Host smart-26e50fc1-27d5-486c-a936-0802c9c9a891
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64520636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.64520636
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.309674075
Short name T178
Test name
Test status
Simulation time 4512836087 ps
CPU time 69.25 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:34:51 PM PDT 24
Peak memory 240340 kb
Host smart-60dedd28-6aa6-4bb5-96a1-8170ec9eaab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=309674075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.309674075
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1959977747
Short name T323
Test name
Test status
Simulation time 32363277211 ps
CPU time 1490.6 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:28:49 PM PDT 24
Peak memory 289296 kb
Host smart-0e976e67-d33c-4aa1-b0c1-01a8d27ec6fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959977747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1959977747
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3296592482
Short name T127
Test name
Test status
Simulation time 93805321294 ps
CPU time 3562.94 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 03:02:26 PM PDT 24
Peak memory 306104 kb
Host smart-f61c95e1-388d-4e99-80be-08fe2be0ad9e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296592482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3296592482
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1262750605
Short name T136
Test name
Test status
Simulation time 6845975449 ps
CPU time 193.56 seconds
Started Mar 19 01:32:53 PM PDT 24
Finished Mar 19 01:36:07 PM PDT 24
Peak memory 265180 kb
Host smart-b849eba6-6f22-40aa-82f4-7167363361c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262750605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1262750605
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1475705203
Short name T113
Test name
Test status
Simulation time 334641940356 ps
CPU time 2355.89 seconds
Started Mar 19 02:03:07 PM PDT 24
Finished Mar 19 02:42:23 PM PDT 24
Peak memory 281784 kb
Host smart-98458b8d-98ec-42f7-8c34-606bd397f38c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475705203 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1475705203
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1112969978
Short name T294
Test name
Test status
Simulation time 79134430656 ps
CPU time 614.26 seconds
Started Mar 19 02:08:53 PM PDT 24
Finished Mar 19 02:19:08 PM PDT 24
Peak memory 247172 kb
Host smart-523f926a-265a-4d66-a5f5-e82bb1d06f10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112969978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1112969978
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4148599863
Short name T596
Test name
Test status
Simulation time 34934163251 ps
CPU time 2159.58 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 273476 kb
Host smart-14462c3b-4b59-4985-86bb-7528f135e9a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148599863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4148599863
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2530759349
Short name T110
Test name
Test status
Simulation time 153583129842 ps
CPU time 2124.81 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:38:28 PM PDT 24
Peak memory 289624 kb
Host smart-317294b3-23a5-44eb-b5c3-fe1b67622cd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530759349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2530759349
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3201218978
Short name T271
Test name
Test status
Simulation time 161988913211 ps
CPU time 1439.28 seconds
Started Mar 19 02:07:06 PM PDT 24
Finished Mar 19 02:31:07 PM PDT 24
Peak memory 289600 kb
Host smart-1aabd8f0-450d-4147-9f7e-3c4ed3e66fed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201218978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3201218978
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3275633978
Short name T724
Test name
Test status
Simulation time 6765340 ps
CPU time 1.46 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:33:52 PM PDT 24
Peak memory 236576 kb
Host smart-03a163d5-adb8-4540-8db2-fe93e7c8582e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3275633978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3275633978
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3977870545
Short name T47
Test name
Test status
Simulation time 42108949129 ps
CPU time 941.38 seconds
Started Mar 19 02:05:01 PM PDT 24
Finished Mar 19 02:20:44 PM PDT 24
Peak memory 272904 kb
Host smart-d0f8b361-4b1e-4783-905f-f83b58a4b5a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977870545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3977870545
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3426262737
Short name T280
Test name
Test status
Simulation time 21989440462 ps
CPU time 1105.69 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:24:08 PM PDT 24
Peak memory 284368 kb
Host smart-5efd8d8b-770b-4716-ba95-e67bb27bc1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426262737 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3426262737
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.178944862
Short name T569
Test name
Test status
Simulation time 20533794744 ps
CPU time 544.85 seconds
Started Mar 19 01:58:59 PM PDT 24
Finished Mar 19 02:08:05 PM PDT 24
Peak memory 247728 kb
Host smart-47210bd0-80e6-4667-b1c3-f4f3ed2974e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178944862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.178944862
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1478890120
Short name T335
Test name
Test status
Simulation time 61182451782 ps
CPU time 1858.84 seconds
Started Mar 19 02:07:36 PM PDT 24
Finished Mar 19 02:38:35 PM PDT 24
Peak memory 273468 kb
Host smart-e207167c-777c-4dbb-80c0-c4e6390f7b09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478890120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1478890120
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.928250697
Short name T252
Test name
Test status
Simulation time 76167456391 ps
CPU time 2672.94 seconds
Started Mar 19 02:09:24 PM PDT 24
Finished Mar 19 02:53:58 PM PDT 24
Peak memory 289556 kb
Host smart-117603d1-9a7c-4a73-b78c-bcd142041723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928250697 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.928250697
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1576075974
Short name T171
Test name
Test status
Simulation time 193172564 ps
CPU time 3.54 seconds
Started Mar 19 01:33:20 PM PDT 24
Finished Mar 19 01:33:26 PM PDT 24
Peak memory 235788 kb
Host smart-224f504f-4b5d-4dd6-8f74-a51d2c3c36b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1576075974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1576075974
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.392110129
Short name T162
Test name
Test status
Simulation time 63145619720 ps
CPU time 977.24 seconds
Started Mar 19 01:33:36 PM PDT 24
Finished Mar 19 01:49:56 PM PDT 24
Peak memory 265152 kb
Host smart-28b23f15-af57-4f57-946a-0071ac4a467a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392110129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.392110129
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3071353221
Short name T137
Test name
Test status
Simulation time 12471695149 ps
CPU time 1191.31 seconds
Started Mar 19 01:33:27 PM PDT 24
Finished Mar 19 01:53:18 PM PDT 24
Peak memory 272960 kb
Host smart-93a02273-5adf-4978-8a43-06144f3eebf4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071353221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3071353221
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2067718547
Short name T161
Test name
Test status
Simulation time 38346796390 ps
CPU time 302.2 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:38:53 PM PDT 24
Peak memory 265296 kb
Host smart-1c2331da-bd06-4c7f-a0ec-a5fc26ca2276
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2067718547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2067718547
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2774234198
Short name T228
Test name
Test status
Simulation time 18026587 ps
CPU time 3.02 seconds
Started Mar 19 01:58:58 PM PDT 24
Finished Mar 19 01:59:01 PM PDT 24
Peak memory 249128 kb
Host smart-f193dc9d-8fab-4054-b08c-48f019e51445
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2774234198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2774234198
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.173998917
Short name T240
Test name
Test status
Simulation time 43334744 ps
CPU time 2.83 seconds
Started Mar 19 02:02:24 PM PDT 24
Finished Mar 19 02:02:27 PM PDT 24
Peak memory 249112 kb
Host smart-faf70c0f-84c0-472c-b3b9-55334899916d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=173998917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.173998917
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1614298169
Short name T237
Test name
Test status
Simulation time 630327591 ps
CPU time 3.83 seconds
Started Mar 19 02:03:45 PM PDT 24
Finished Mar 19 02:03:49 PM PDT 24
Peak memory 249116 kb
Host smart-6130ca2a-ec4b-4305-964b-87417b17cd33
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1614298169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1614298169
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1536010283
Short name T19
Test name
Test status
Simulation time 167352281 ps
CPU time 4.27 seconds
Started Mar 19 02:04:10 PM PDT 24
Finished Mar 19 02:04:14 PM PDT 24
Peak memory 249112 kb
Host smart-98f95abd-6f2b-4bf8-80b7-a7b65e54b31b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1536010283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1536010283
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4074340818
Short name T737
Test name
Test status
Simulation time 19388854 ps
CPU time 1.46 seconds
Started Mar 19 01:33:36 PM PDT 24
Finished Mar 19 01:33:40 PM PDT 24
Peak memory 235672 kb
Host smart-21b2f079-2543-40af-b67d-e1241dec8665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4074340818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4074340818
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.764852163
Short name T217
Test name
Test status
Simulation time 15985952637 ps
CPU time 355.64 seconds
Started Mar 19 02:03:04 PM PDT 24
Finished Mar 19 02:09:02 PM PDT 24
Peak memory 248224 kb
Host smart-b5e398b6-9637-419d-8b01-7f4211f23312
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764852163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.764852163
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1148192749
Short name T68
Test name
Test status
Simulation time 85000613741 ps
CPU time 3718.35 seconds
Started Mar 19 02:03:14 PM PDT 24
Finished Mar 19 03:05:13 PM PDT 24
Peak memory 306348 kb
Host smart-e2cdc2c7-f343-430a-b73b-91ddb2f39236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148192749 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1148192749
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.337771223
Short name T303
Test name
Test status
Simulation time 24909804331 ps
CPU time 508.35 seconds
Started Mar 19 02:03:44 PM PDT 24
Finished Mar 19 02:12:12 PM PDT 24
Peak memory 248148 kb
Host smart-292ce724-3452-4b09-ac22-f3e0a3e3bbcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337771223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.337771223
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3654099519
Short name T126
Test name
Test status
Simulation time 452792795006 ps
CPU time 4569.3 seconds
Started Mar 19 02:04:33 PM PDT 24
Finished Mar 19 03:20:43 PM PDT 24
Peak memory 306184 kb
Host smart-981d450d-2a02-41d5-9cba-7899e44818ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654099519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3654099519
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3515735362
Short name T266
Test name
Test status
Simulation time 61837992214 ps
CPU time 3932.07 seconds
Started Mar 19 02:06:20 PM PDT 24
Finished Mar 19 03:11:52 PM PDT 24
Peak memory 289932 kb
Host smart-9ede6ee5-80ed-4cae-9b9a-3ef3d87df909
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515735362 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3515735362
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2545857011
Short name T265
Test name
Test status
Simulation time 14950594761 ps
CPU time 1495.63 seconds
Started Mar 19 02:11:42 PM PDT 24
Finished Mar 19 02:36:41 PM PDT 24
Peak memory 286104 kb
Host smart-4e596f22-1966-48b6-bd1b-d501096499e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545857011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2545857011
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1230014346
Short name T152
Test name
Test status
Simulation time 8010388142 ps
CPU time 306.6 seconds
Started Mar 19 01:32:59 PM PDT 24
Finished Mar 19 01:38:07 PM PDT 24
Peak memory 266140 kb
Host smart-69f6f979-9473-42b5-94b9-b6b6684c9b8e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230014346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1230014346
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2660318414
Short name T262
Test name
Test status
Simulation time 1592337737 ps
CPU time 50.13 seconds
Started Mar 19 01:58:52 PM PDT 24
Finished Mar 19 01:59:42 PM PDT 24
Peak memory 255856 kb
Host smart-ddbfbfb2-4996-4e83-b727-c0b9ec04c5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
18414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2660318414
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.4124942405
Short name T103
Test name
Test status
Simulation time 31394204403 ps
CPU time 1766.86 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:32:37 PM PDT 24
Peak memory 298156 kb
Host smart-a5b0cba2-8ed8-4cdc-96a7-5808bfb41219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124942405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.4124942405
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.830031052
Short name T281
Test name
Test status
Simulation time 1171575435 ps
CPU time 76.41 seconds
Started Mar 19 02:04:52 PM PDT 24
Finished Mar 19 02:06:08 PM PDT 24
Peak memory 255268 kb
Host smart-2c90cedf-56e4-4beb-91db-1d542fa4bd34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830031052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.830031052
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.978218040
Short name T247
Test name
Test status
Simulation time 74752461187 ps
CPU time 1608.12 seconds
Started Mar 19 02:04:09 PM PDT 24
Finished Mar 19 02:30:58 PM PDT 24
Peak memory 287464 kb
Host smart-62d940dd-e2ae-4320-9ea6-c439f1465af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978218040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.978218040
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2020573337
Short name T96
Test name
Test status
Simulation time 149072250586 ps
CPU time 8638.18 seconds
Started Mar 19 02:04:47 PM PDT 24
Finished Mar 19 04:28:47 PM PDT 24
Peak memory 395072 kb
Host smart-0ba07ac2-0248-4544-b434-ab265e9ca6a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020573337 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2020573337
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.57503129
Short name T325
Test name
Test status
Simulation time 38810916585 ps
CPU time 2207.26 seconds
Started Mar 19 02:04:31 PM PDT 24
Finished Mar 19 02:41:19 PM PDT 24
Peak memory 281364 kb
Host smart-3adad14f-6ba4-4883-9717-6af56f7de70e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57503129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.57503129
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2879596515
Short name T261
Test name
Test status
Simulation time 126207600527 ps
CPU time 3616.09 seconds
Started Mar 19 02:06:10 PM PDT 24
Finished Mar 19 03:06:26 PM PDT 24
Peak memory 298044 kb
Host smart-0f970e4b-493e-4090-a9cb-d8935d940ca9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879596515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2879596515
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1884441926
Short name T282
Test name
Test status
Simulation time 4352918845 ps
CPU time 481.2 seconds
Started Mar 19 02:06:32 PM PDT 24
Finished Mar 19 02:14:33 PM PDT 24
Peak memory 265264 kb
Host smart-71bc2b01-9fec-48ab-9cd4-a0a10b99d1c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884441926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1884441926
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.361410462
Short name T554
Test name
Test status
Simulation time 12179407006 ps
CPU time 500.96 seconds
Started Mar 19 02:06:44 PM PDT 24
Finished Mar 19 02:15:06 PM PDT 24
Peak memory 247044 kb
Host smart-bfe9f05b-fb2a-488a-872b-69f4f742d098
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361410462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.361410462
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.4152991073
Short name T112
Test name
Test status
Simulation time 108490472979 ps
CPU time 3103.69 seconds
Started Mar 19 02:07:47 PM PDT 24
Finished Mar 19 02:59:31 PM PDT 24
Peak memory 289500 kb
Host smart-072692cf-51e8-4cac-b30c-7315ee3a2d28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152991073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4152991073
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2924624271
Short name T275
Test name
Test status
Simulation time 16109278450 ps
CPU time 1506 seconds
Started Mar 19 02:08:07 PM PDT 24
Finished Mar 19 02:33:14 PM PDT 24
Peak memory 289368 kb
Host smart-c649d49b-8679-4e81-b7e8-8159c1a823ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924624271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2924624271
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.541872635
Short name T263
Test name
Test status
Simulation time 281391288 ps
CPU time 16.6 seconds
Started Mar 19 02:09:25 PM PDT 24
Finished Mar 19 02:09:42 PM PDT 24
Peak memory 248876 kb
Host smart-9176ef26-68fc-43ec-a40e-2605bc00126e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54187
2635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.541872635
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.988883695
Short name T288
Test name
Test status
Simulation time 191525289550 ps
CPU time 3222.05 seconds
Started Mar 19 02:12:15 PM PDT 24
Finished Mar 19 03:05:58 PM PDT 24
Peak memory 289344 kb
Host smart-4641e467-42d8-4190-b10a-b90c08ad3e22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988883695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.988883695
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2804245504
Short name T92
Test name
Test status
Simulation time 73832971690 ps
CPU time 2211.48 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:49:22 PM PDT 24
Peak memory 282796 kb
Host smart-a4181a4a-0c2b-4820-a77a-f788bb394da5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804245504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2804245504
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2122336004
Short name T34
Test name
Test status
Simulation time 12349379100 ps
CPU time 1051.53 seconds
Started Mar 19 02:03:27 PM PDT 24
Finished Mar 19 02:20:59 PM PDT 24
Peak memory 288636 kb
Host smart-9b2c14ac-6239-480f-9b29-d1bd8243d06d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122336004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2122336004
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3982000460
Short name T179
Test name
Test status
Simulation time 222021344 ps
CPU time 4.65 seconds
Started Mar 19 01:33:07 PM PDT 24
Finished Mar 19 01:33:12 PM PDT 24
Peak memory 236632 kb
Host smart-d77b6025-c129-4e13-a9d0-f04c1daad7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3982000460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3982000460
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3363760712
Short name T155
Test name
Test status
Simulation time 1565820673 ps
CPU time 89.22 seconds
Started Mar 19 01:32:55 PM PDT 24
Finished Mar 19 01:34:24 PM PDT 24
Peak memory 256812 kb
Host smart-593ec692-5c15-45a4-a2cd-3f575b8c7463
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3363760712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3363760712
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1513757136
Short name T177
Test name
Test status
Simulation time 890766095 ps
CPU time 44.17 seconds
Started Mar 19 01:33:00 PM PDT 24
Finished Mar 19 01:33:45 PM PDT 24
Peak memory 239624 kb
Host smart-054357ea-2336-4a60-9d16-60250dc32c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1513757136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1513757136
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2461915502
Short name T148
Test name
Test status
Simulation time 2086422802 ps
CPU time 146.79 seconds
Started Mar 19 01:33:01 PM PDT 24
Finished Mar 19 01:35:28 PM PDT 24
Peak memory 256876 kb
Host smart-231b8992-53c2-4ae4-91b7-ab32b9feee19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2461915502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2461915502
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3939006037
Short name T180
Test name
Test status
Simulation time 1419721872 ps
CPU time 57.62 seconds
Started Mar 19 01:32:56 PM PDT 24
Finished Mar 19 01:33:54 PM PDT 24
Peak memory 240276 kb
Host smart-585a9824-b872-432d-88fc-75b90d209eb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3939006037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3939006037
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3009576354
Short name T181
Test name
Test status
Simulation time 3329441780 ps
CPU time 47.99 seconds
Started Mar 19 01:33:57 PM PDT 24
Finished Mar 19 01:34:46 PM PDT 24
Peak memory 240336 kb
Host smart-1f466b95-3399-459c-bf99-94eafe4a1963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3009576354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3009576354
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.4013430737
Short name T189
Test name
Test status
Simulation time 54382426 ps
CPU time 4.28 seconds
Started Mar 19 01:33:02 PM PDT 24
Finished Mar 19 01:33:07 PM PDT 24
Peak memory 236940 kb
Host smart-286fd8b7-df16-475c-8cf1-7418bcd45823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4013430737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.4013430737
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2607074512
Short name T183
Test name
Test status
Simulation time 153436601 ps
CPU time 25.61 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:34:01 PM PDT 24
Peak memory 240316 kb
Host smart-8677b0e9-fea7-461d-99a6-a1d0cdcb3f51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2607074512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2607074512
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3056928108
Short name T188
Test name
Test status
Simulation time 9822205236 ps
CPU time 75.56 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:34:51 PM PDT 24
Peak memory 239728 kb
Host smart-7a6a101b-301f-4789-8c71-c6e351df1fda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3056928108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3056928108
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2533865026
Short name T184
Test name
Test status
Simulation time 54395212 ps
CPU time 2.17 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:33:54 PM PDT 24
Peak memory 237032 kb
Host smart-4af4464b-f165-4402-94c9-9a98cf4ef834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2533865026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2533865026
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1596861555
Short name T145
Test name
Test status
Simulation time 170574661652 ps
CPU time 1173.58 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:53:24 PM PDT 24
Peak memory 272044 kb
Host smart-070a6843-d371-49da-9a80-7eca591b2b9a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596861555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1596861555
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1604091758
Short name T138
Test name
Test status
Simulation time 10057925512 ps
CPU time 156.8 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:36:35 PM PDT 24
Peak memory 265108 kb
Host smart-b22b5614-5a3b-4f31-b12f-70bc7f5de299
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1604091758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1604091758
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2583129263
Short name T185
Test name
Test status
Simulation time 142011593 ps
CPU time 7.21 seconds
Started Mar 19 01:33:06 PM PDT 24
Finished Mar 19 01:33:15 PM PDT 24
Peak memory 236880 kb
Host smart-e24b6675-c290-4a5b-b3c9-c7341c4b0f07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2583129263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2583129263
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2543139825
Short name T194
Test name
Test status
Simulation time 10471388767 ps
CPU time 40.12 seconds
Started Mar 19 01:33:16 PM PDT 24
Finished Mar 19 01:33:57 PM PDT 24
Peak memory 237268 kb
Host smart-c816139e-54b0-44b4-aca6-544ac2a10b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2543139825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2543139825
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1531503445
Short name T195
Test name
Test status
Simulation time 109478053 ps
CPU time 3.02 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:33:54 PM PDT 24
Peak memory 237612 kb
Host smart-1bebb219-05da-4224-9631-c9a9500834e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1531503445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1531503445
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.326377256
Short name T186
Test name
Test status
Simulation time 1278675383 ps
CPU time 44.47 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:34:36 PM PDT 24
Peak memory 239620 kb
Host smart-b73242e6-5a45-4a11-88a3-a17a038e464a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=326377256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.326377256
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2838182746
Short name T182
Test name
Test status
Simulation time 2580169608 ps
CPU time 45.53 seconds
Started Mar 19 01:34:02 PM PDT 24
Finished Mar 19 01:34:48 PM PDT 24
Peak memory 245160 kb
Host smart-87311cac-de55-4e08-8ab5-2cb9f2963090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2838182746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2838182746
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1566531914
Short name T173
Test name
Test status
Simulation time 61734880 ps
CPU time 2.36 seconds
Started Mar 19 01:33:17 PM PDT 24
Finished Mar 19 01:33:19 PM PDT 24
Peak memory 236584 kb
Host smart-3a8acc6a-be4a-436d-860f-fdb01911f48f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1566531914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1566531914
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2380107652
Short name T23
Test name
Test status
Simulation time 119625664 ps
CPU time 8.69 seconds
Started Mar 19 02:02:12 PM PDT 24
Finished Mar 19 02:02:21 PM PDT 24
Peak memory 240696 kb
Host smart-cd61a8b6-a0d6-42d3-abe6-79c648cf086d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23801
07652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2380107652
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1805670258
Short name T28
Test name
Test status
Simulation time 682169706 ps
CPU time 29.22 seconds
Started Mar 19 02:07:57 PM PDT 24
Finished Mar 19 02:08:27 PM PDT 24
Peak memory 249288 kb
Host smart-db40005c-ac73-478b-ade4-7d70e953968b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18056
70258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1805670258
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2248046340
Short name T24
Test name
Test status
Simulation time 1701189886 ps
CPU time 61.39 seconds
Started Mar 19 02:07:57 PM PDT 24
Finished Mar 19 02:08:59 PM PDT 24
Peak memory 255508 kb
Host smart-4adec434-9272-4923-aede-cc1c0294249d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22480
46340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2248046340
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2271087461
Short name T250
Test name
Test status
Simulation time 2242131288 ps
CPU time 153.3 seconds
Started Mar 19 01:32:58 PM PDT 24
Finished Mar 19 01:35:32 PM PDT 24
Peak memory 236628 kb
Host smart-2be3ec1e-4282-444e-a61d-d9c295a3ff3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2271087461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2271087461
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.6836131
Short name T749
Test name
Test status
Simulation time 1687492460 ps
CPU time 221.55 seconds
Started Mar 19 01:32:55 PM PDT 24
Finished Mar 19 01:36:37 PM PDT 24
Peak memory 236524 kb
Host smart-7c8d5fbd-142b-4a79-992c-de11802899cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=6836131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.6836131
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4083059078
Short name T719
Test name
Test status
Simulation time 38243564 ps
CPU time 5.59 seconds
Started Mar 19 01:32:56 PM PDT 24
Finished Mar 19 01:33:02 PM PDT 24
Peak memory 240156 kb
Host smart-cf5eb3b6-28f6-4f0b-a153-560a3fd15850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4083059078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4083059078
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2949850607
Short name T344
Test name
Test status
Simulation time 104673261 ps
CPU time 7.6 seconds
Started Mar 19 01:32:58 PM PDT 24
Finished Mar 19 01:33:06 PM PDT 24
Peak memory 252312 kb
Host smart-cac980a0-ce9d-4e43-987d-ed324168974f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949850607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2949850607
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3560619041
Short name T772
Test name
Test status
Simulation time 90747464 ps
CPU time 4.45 seconds
Started Mar 19 01:32:56 PM PDT 24
Finished Mar 19 01:33:01 PM PDT 24
Peak memory 236544 kb
Host smart-c2e1b104-e232-4b93-8d69-b5340f47a5fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3560619041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3560619041
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2504732823
Short name T728
Test name
Test status
Simulation time 8683135 ps
CPU time 1.59 seconds
Started Mar 19 01:32:53 PM PDT 24
Finished Mar 19 01:32:55 PM PDT 24
Peak memory 236580 kb
Host smart-afb12492-429c-47b9-a8ca-92726e44886e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504732823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2504732823
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2036699265
Short name T206
Test name
Test status
Simulation time 260682160 ps
CPU time 19.59 seconds
Started Mar 19 01:32:53 PM PDT 24
Finished Mar 19 01:33:13 PM PDT 24
Peak memory 244860 kb
Host smart-ce0e3ce1-5e62-4430-a940-ce67c723074e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2036699265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2036699265
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1769093752
Short name T754
Test name
Test status
Simulation time 759489923 ps
CPU time 12.74 seconds
Started Mar 19 01:32:53 PM PDT 24
Finished Mar 19 01:33:06 PM PDT 24
Peak memory 248508 kb
Host smart-29a66994-6f12-4b6e-b38b-f653855dfe3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1769093752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1769093752
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3853789317
Short name T210
Test name
Test status
Simulation time 4374282033 ps
CPU time 281.62 seconds
Started Mar 19 01:33:01 PM PDT 24
Finished Mar 19 01:37:43 PM PDT 24
Peak memory 240464 kb
Host smart-9c839931-c45f-476d-bd0c-a466f9b502db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3853789317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3853789317
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.550614012
Short name T763
Test name
Test status
Simulation time 3028212189 ps
CPU time 107.54 seconds
Started Mar 19 01:33:01 PM PDT 24
Finished Mar 19 01:34:48 PM PDT 24
Peak memory 236656 kb
Host smart-9d720313-ab6c-4568-a466-906bf694b4fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=550614012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.550614012
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3891212046
Short name T725
Test name
Test status
Simulation time 85012756 ps
CPU time 5.79 seconds
Started Mar 19 01:33:00 PM PDT 24
Finished Mar 19 01:33:06 PM PDT 24
Peak memory 240184 kb
Host smart-7b1934c7-3f96-4163-abd9-f8dc3607ae55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3891212046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3891212046
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.471526972
Short name T191
Test name
Test status
Simulation time 99024610 ps
CPU time 7.46 seconds
Started Mar 19 01:32:59 PM PDT 24
Finished Mar 19 01:33:07 PM PDT 24
Peak memory 240416 kb
Host smart-1a9d0834-25d0-4656-90d3-9acfe99e311b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471526972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.471526972
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.738949417
Short name T762
Test name
Test status
Simulation time 56562910 ps
CPU time 4.67 seconds
Started Mar 19 01:33:01 PM PDT 24
Finished Mar 19 01:33:05 PM PDT 24
Peak memory 235692 kb
Host smart-a216c6a7-9d14-4b3b-a0a7-e8b5267e5d47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=738949417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.738949417
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3886170112
Short name T807
Test name
Test status
Simulation time 6628592 ps
CPU time 1.35 seconds
Started Mar 19 01:33:01 PM PDT 24
Finished Mar 19 01:33:03 PM PDT 24
Peak memory 235816 kb
Host smart-17077970-ea66-4e77-a464-76ef2ca6a030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3886170112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3886170112
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3458428179
Short name T739
Test name
Test status
Simulation time 308026989 ps
CPU time 19.58 seconds
Started Mar 19 01:33:02 PM PDT 24
Finished Mar 19 01:33:22 PM PDT 24
Peak memory 240348 kb
Host smart-1ac9c789-7429-441e-95c2-f0d0f885de0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3458428179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3458428179
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2266561758
Short name T165
Test name
Test status
Simulation time 2249943113 ps
CPU time 366.2 seconds
Started Mar 19 01:32:56 PM PDT 24
Finished Mar 19 01:39:02 PM PDT 24
Peak memory 265200 kb
Host smart-e05e269d-9cda-4bcb-8459-98e98e82c151
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266561758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2266561758
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.406393463
Short name T787
Test name
Test status
Simulation time 303220536 ps
CPU time 23.68 seconds
Started Mar 19 01:32:55 PM PDT 24
Finished Mar 19 01:33:18 PM PDT 24
Peak memory 248572 kb
Host smart-5ff74791-478d-4d42-9ab3-08c70fe3d669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=406393463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.406393463
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3796865132
Short name T730
Test name
Test status
Simulation time 544804588 ps
CPU time 11.24 seconds
Started Mar 19 01:33:36 PM PDT 24
Finished Mar 19 01:33:50 PM PDT 24
Peak memory 252788 kb
Host smart-0fefd271-f9ec-446f-97c6-e4dfb956e92e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796865132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3796865132
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1054101270
Short name T349
Test name
Test status
Simulation time 115149291 ps
CPU time 7.86 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:33:43 PM PDT 24
Peak memory 240244 kb
Host smart-a3ef72c6-2b6f-498c-b27e-b2578c8abf7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1054101270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1054101270
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3840270010
Short name T824
Test name
Test status
Simulation time 2651919608 ps
CPU time 23.5 seconds
Started Mar 19 01:33:36 PM PDT 24
Finished Mar 19 01:34:02 PM PDT 24
Peak memory 243940 kb
Host smart-9e308da6-0f41-49bd-a7ea-6ee6a5c8b7ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3840270010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3840270010
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3798674814
Short name T139
Test name
Test status
Simulation time 8200009901 ps
CPU time 617.02 seconds
Started Mar 19 01:33:36 PM PDT 24
Finished Mar 19 01:43:55 PM PDT 24
Peak memory 266184 kb
Host smart-fc9fd702-08fc-4a68-b638-223a93eefad2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798674814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3798674814
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1748079745
Short name T789
Test name
Test status
Simulation time 1005200833 ps
CPU time 17.89 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:33:53 PM PDT 24
Peak memory 248532 kb
Host smart-91135419-b949-4b48-b5ab-b6b63fb8fd84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1748079745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1748079745
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2946204591
Short name T752
Test name
Test status
Simulation time 119977921 ps
CPU time 10.42 seconds
Started Mar 19 01:33:42 PM PDT 24
Finished Mar 19 01:33:53 PM PDT 24
Peak memory 250592 kb
Host smart-b0d63919-23a1-4297-ad9d-f65375477b8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946204591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2946204591
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.55177856
Short name T190
Test name
Test status
Simulation time 19651349 ps
CPU time 3.35 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:33:45 PM PDT 24
Peak memory 238480 kb
Host smart-22934c04-6d7d-4380-b101-4cf35f13e1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=55177856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.55177856
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.970141600
Short name T721
Test name
Test status
Simulation time 14293641 ps
CPU time 1.5 seconds
Started Mar 19 01:33:43 PM PDT 24
Finished Mar 19 01:33:44 PM PDT 24
Peak memory 235760 kb
Host smart-192d1e41-40e1-4c37-b295-73c64f859d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=970141600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.970141600
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4194667279
Short name T758
Test name
Test status
Simulation time 181096858 ps
CPU time 25.8 seconds
Started Mar 19 01:33:44 PM PDT 24
Finished Mar 19 01:34:10 PM PDT 24
Peak memory 244824 kb
Host smart-f76abb72-720a-4ab4-8c1d-4f7ec8a78988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4194667279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.4194667279
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2451012878
Short name T169
Test name
Test status
Simulation time 4381148711 ps
CPU time 147.5 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:36:09 PM PDT 24
Peak memory 264884 kb
Host smart-9f457779-9efd-4fad-b8f5-6e5e3cd97ad8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2451012878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2451012878
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.815315275
Short name T821
Test name
Test status
Simulation time 25294442 ps
CPU time 3.68 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:33:45 PM PDT 24
Peak memory 240288 kb
Host smart-f3f1317b-a955-4508-9048-cd4f257cb1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=815315275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.815315275
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4099686474
Short name T187
Test name
Test status
Simulation time 64347266 ps
CPU time 2.02 seconds
Started Mar 19 01:33:46 PM PDT 24
Finished Mar 19 01:33:48 PM PDT 24
Peak memory 236660 kb
Host smart-5bc8b2b8-0f20-4717-bf63-7e743a1b34fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4099686474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4099686474
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2925009641
Short name T746
Test name
Test status
Simulation time 148125126 ps
CPU time 12.32 seconds
Started Mar 19 01:33:43 PM PDT 24
Finished Mar 19 01:33:56 PM PDT 24
Peak memory 248568 kb
Host smart-745d5e23-596f-4846-8558-2ed71e086354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925009641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2925009641
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3675063738
Short name T350
Test name
Test status
Simulation time 443137173 ps
CPU time 4.94 seconds
Started Mar 19 01:33:43 PM PDT 24
Finished Mar 19 01:33:48 PM PDT 24
Peak memory 236384 kb
Host smart-1be69dca-fa7c-4a9e-9338-8d1c0167ba75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3675063738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3675063738
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.982692876
Short name T736
Test name
Test status
Simulation time 6843198 ps
CPU time 1.46 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:33:43 PM PDT 24
Peak memory 236600 kb
Host smart-3408d449-0d83-477a-af44-0b1bc77ba29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=982692876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.982692876
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.422642619
Short name T747
Test name
Test status
Simulation time 318845220 ps
CPU time 21.47 seconds
Started Mar 19 01:33:45 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 248544 kb
Host smart-08a594f8-74f6-4eec-bd86-1a67c92e7472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=422642619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.422642619
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1999843946
Short name T156
Test name
Test status
Simulation time 10077027868 ps
CPU time 177.77 seconds
Started Mar 19 01:33:42 PM PDT 24
Finished Mar 19 01:36:40 PM PDT 24
Peak memory 265144 kb
Host smart-a281a3d2-1279-4db8-b85d-04cd9c2a2364
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1999843946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1999843946
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2693747348
Short name T133
Test name
Test status
Simulation time 8695506441 ps
CPU time 685.52 seconds
Started Mar 19 01:33:41 PM PDT 24
Finished Mar 19 01:45:07 PM PDT 24
Peak memory 265208 kb
Host smart-a2266f1d-9301-4de7-ba13-b5161bbd66a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693747348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2693747348
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2068344121
Short name T810
Test name
Test status
Simulation time 176744687 ps
CPU time 13.17 seconds
Started Mar 19 01:33:44 PM PDT 24
Finished Mar 19 01:33:57 PM PDT 24
Peak memory 253188 kb
Host smart-24aef1d4-e797-4ea2-8de7-6b415d258411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068344121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2068344121
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3767278195
Short name T828
Test name
Test status
Simulation time 215151544 ps
CPU time 5.76 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:33:56 PM PDT 24
Peak memory 239880 kb
Host smart-927f39a2-1d8a-41b9-90e1-00c4231a499c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767278195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3767278195
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.544782451
Short name T723
Test name
Test status
Simulation time 65558780 ps
CPU time 4.6 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:33:57 PM PDT 24
Peak memory 235700 kb
Host smart-2c83f141-0d3b-4e67-9eff-814cd2a9efa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=544782451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.544782451
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.467419537
Short name T726
Test name
Test status
Simulation time 16434308 ps
CPU time 1.34 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:33:52 PM PDT 24
Peak memory 234816 kb
Host smart-02f3ba08-1b45-40a4-82a5-7c1b775e63f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=467419537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.467419537
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2019489637
Short name T770
Test name
Test status
Simulation time 2727089535 ps
CPU time 53.34 seconds
Started Mar 19 01:33:49 PM PDT 24
Finished Mar 19 01:34:43 PM PDT 24
Peak memory 244908 kb
Host smart-9e56d744-2758-4eed-a7b3-6f59ab910baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2019489637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2019489637
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4107406585
Short name T170
Test name
Test status
Simulation time 63934901315 ps
CPU time 373.13 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:40:03 PM PDT 24
Peak memory 265108 kb
Host smart-1f9de486-53ff-45f4-b62e-9f3db1440d58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4107406585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4107406585
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.4120205203
Short name T817
Test name
Test status
Simulation time 310897462 ps
CPU time 12.85 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:34:05 PM PDT 24
Peak memory 248700 kb
Host smart-27700b49-0162-43d4-b0f3-e9288ed0b118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4120205203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.4120205203
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.905103551
Short name T792
Test name
Test status
Simulation time 37770720 ps
CPU time 7.22 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 256792 kb
Host smart-feb30154-e4a1-499b-ad64-e3cfcb42d331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905103551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.905103551
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3091519438
Short name T732
Test name
Test status
Simulation time 105280792 ps
CPU time 9.85 seconds
Started Mar 19 01:33:49 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 240196 kb
Host smart-e29be82f-c740-4fab-b5c2-d32a84ae4c1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3091519438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3091519438
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.389951063
Short name T809
Test name
Test status
Simulation time 22684822 ps
CPU time 1.45 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:33:53 PM PDT 24
Peak memory 235812 kb
Host smart-37bceead-2334-43b0-b142-a90249578824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=389951063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.389951063
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2408975943
Short name T825
Test name
Test status
Simulation time 647935683 ps
CPU time 20.72 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:34:11 PM PDT 24
Peak memory 248520 kb
Host smart-884a5617-572c-4767-ab38-331a0781003f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2408975943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2408975943
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2742092468
Short name T775
Test name
Test status
Simulation time 1543491627 ps
CPU time 23.75 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:34:15 PM PDT 24
Peak memory 253016 kb
Host smart-0b28fa08-b5be-427f-ba73-b4408b332a56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2742092468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2742092468
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3389528209
Short name T760
Test name
Test status
Simulation time 236158106 ps
CPU time 5.72 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:33:57 PM PDT 24
Peak memory 239568 kb
Host smart-0be65b4c-6d5f-4cae-bdfd-ed21c64fd0f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389528209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3389528209
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2612934701
Short name T798
Test name
Test status
Simulation time 63877223 ps
CPU time 3.45 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:33:55 PM PDT 24
Peak memory 236424 kb
Host smart-b7d120bf-8018-4dc7-8547-0790bd27681f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2612934701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2612934701
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1588886875
Short name T741
Test name
Test status
Simulation time 12036537 ps
CPU time 1.28 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:33:52 PM PDT 24
Peak memory 234792 kb
Host smart-d3696d8c-79f5-4412-9eb9-ab54c748dcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1588886875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1588886875
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1698888632
Short name T831
Test name
Test status
Simulation time 1002839435 ps
CPU time 36.19 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:34:26 PM PDT 24
Peak memory 248548 kb
Host smart-a8c09305-eb17-4461-b7b0-176f6a4bb3c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1698888632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1698888632
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3924327194
Short name T163
Test name
Test status
Simulation time 4221384940 ps
CPU time 308.43 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:38:59 PM PDT 24
Peak memory 265100 kb
Host smart-df4266fe-2b90-4767-8286-b4aa01a1e0c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3924327194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3924327194
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2530342761
Short name T164
Test name
Test status
Simulation time 6010568759 ps
CPU time 569.81 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:43:22 PM PDT 24
Peak memory 269492 kb
Host smart-1ac76f9d-75c0-4e21-972a-9d017114e395
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530342761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2530342761
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3396807429
Short name T733
Test name
Test status
Simulation time 208561093 ps
CPU time 8.27 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 248580 kb
Host smart-25270abf-d73c-4a92-aea1-c8da63571f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3396807429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3396807429
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.699988830
Short name T800
Test name
Test status
Simulation time 1006693311 ps
CPU time 15.56 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 250872 kb
Host smart-a16901fa-6ce6-4916-aae3-38dfb8957a82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699988830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.699988830
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3895687755
Short name T779
Test name
Test status
Simulation time 38185713 ps
CPU time 5.8 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:33:58 PM PDT 24
Peak memory 240220 kb
Host smart-d0aa4e64-ca3a-4b59-83bc-4ce8c23aef6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3895687755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3895687755
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1072527951
Short name T204
Test name
Test status
Simulation time 1438453624 ps
CPU time 47.96 seconds
Started Mar 19 01:33:51 PM PDT 24
Finished Mar 19 01:34:39 PM PDT 24
Peak memory 244868 kb
Host smart-f7445737-e00e-45f0-90de-a56692d9d718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1072527951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1072527951
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3741291143
Short name T166
Test name
Test status
Simulation time 5989372616 ps
CPU time 485.79 seconds
Started Mar 19 01:33:50 PM PDT 24
Finished Mar 19 01:41:56 PM PDT 24
Peak memory 268856 kb
Host smart-0a8a5d8b-f6f6-4891-a897-37eeccdb5b80
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741291143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3741291143
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.440265909
Short name T740
Test name
Test status
Simulation time 204455524 ps
CPU time 16.74 seconds
Started Mar 19 01:33:52 PM PDT 24
Finished Mar 19 01:34:09 PM PDT 24
Peak memory 252868 kb
Host smart-31679bea-a07c-4eea-861d-e8224da79cda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=440265909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.440265909
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1848379617
Short name T753
Test name
Test status
Simulation time 42600228 ps
CPU time 3.72 seconds
Started Mar 19 01:33:57 PM PDT 24
Finished Mar 19 01:34:01 PM PDT 24
Peak memory 238264 kb
Host smart-25fd98c5-94b5-4edc-bcf7-b47335096df2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1848379617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1848379617
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3801954224
Short name T744
Test name
Test status
Simulation time 22686905 ps
CPU time 1.4 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 236656 kb
Host smart-26beabf2-820d-46b7-b4d7-e50a24b5f9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3801954224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3801954224
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.199679757
Short name T203
Test name
Test status
Simulation time 94209757 ps
CPU time 11.4 seconds
Started Mar 19 01:34:00 PM PDT 24
Finished Mar 19 01:34:12 PM PDT 24
Peak memory 243952 kb
Host smart-072dfcb8-d46b-459d-8564-4a09dd523242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=199679757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.199679757
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1735449666
Short name T147
Test name
Test status
Simulation time 59664304249 ps
CPU time 835.97 seconds
Started Mar 19 01:34:00 PM PDT 24
Finished Mar 19 01:47:56 PM PDT 24
Peak memory 272360 kb
Host smart-60d378b7-35f1-408b-ab4b-4c194b7a6660
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735449666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1735449666
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1793908067
Short name T717
Test name
Test status
Simulation time 267341288 ps
CPU time 17.83 seconds
Started Mar 19 01:34:00 PM PDT 24
Finished Mar 19 01:34:18 PM PDT 24
Peak memory 248564 kb
Host smart-20f7ccd1-f87f-496f-8642-c29681aef75a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1793908067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1793908067
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2756724252
Short name T818
Test name
Test status
Simulation time 197616642 ps
CPU time 9.52 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 250780 kb
Host smart-b2b41c66-91d2-45dc-9435-5f2d37aec919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756724252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2756724252
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1441687327
Short name T819
Test name
Test status
Simulation time 63284881 ps
CPU time 5.37 seconds
Started Mar 19 01:34:02 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 235692 kb
Host smart-0daca24a-56f3-41a2-b20c-6097ba068f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1441687327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1441687327
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.4069983052
Short name T812
Test name
Test status
Simulation time 6794668 ps
CPU time 1.52 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 235796 kb
Host smart-538e7c46-efdc-48ed-8f7d-7a2525705414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4069983052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.4069983052
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3216121135
Short name T768
Test name
Test status
Simulation time 169090123 ps
CPU time 25.02 seconds
Started Mar 19 01:34:00 PM PDT 24
Finished Mar 19 01:34:25 PM PDT 24
Peak memory 248344 kb
Host smart-a4fa3d57-f23e-4ebe-9509-6a1b8e13dbb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3216121135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3216121135
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2391501621
Short name T134
Test name
Test status
Simulation time 6618104860 ps
CPU time 155.15 seconds
Started Mar 19 01:33:57 PM PDT 24
Finished Mar 19 01:36:33 PM PDT 24
Peak memory 265180 kb
Host smart-bad6b8d6-8a5c-4eae-9b1e-720cd015a483
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2391501621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2391501621
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2731849898
Short name T822
Test name
Test status
Simulation time 8599130613 ps
CPU time 320.89 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:39:21 PM PDT 24
Peak memory 264968 kb
Host smart-5a83b34f-310d-4a06-b2c3-6ba72ba069f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731849898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2731849898
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1445103438
Short name T750
Test name
Test status
Simulation time 2515996221 ps
CPU time 20.13 seconds
Started Mar 19 01:34:02 PM PDT 24
Finished Mar 19 01:34:23 PM PDT 24
Peak memory 252784 kb
Host smart-4b2209fe-b5d7-4969-b485-ba2f5f23b677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1445103438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1445103438
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1809935433
Short name T347
Test name
Test status
Simulation time 1411786741 ps
CPU time 8.72 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 239460 kb
Host smart-b148c95f-2d2b-4f39-9aea-3a147a1be08c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809935433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1809935433
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3075988015
Short name T764
Test name
Test status
Simulation time 36794955 ps
CPU time 5.83 seconds
Started Mar 19 01:34:02 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 240228 kb
Host smart-bea9f867-7abc-48fa-bbfb-0101df38ada2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3075988015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3075988015
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.683398458
Short name T811
Test name
Test status
Simulation time 10652931 ps
CPU time 1.33 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 236584 kb
Host smart-0b2ecb72-695d-4151-8c79-fbc297208030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=683398458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.683398458
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4236096087
Short name T193
Test name
Test status
Simulation time 353545263 ps
CPU time 25.13 seconds
Started Mar 19 01:33:57 PM PDT 24
Finished Mar 19 01:34:22 PM PDT 24
Peak memory 244764 kb
Host smart-05962811-64ff-4bbd-b794-8f1893fdece7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4236096087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4236096087
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2894502766
Short name T168
Test name
Test status
Simulation time 7609554933 ps
CPU time 554.14 seconds
Started Mar 19 01:33:56 PM PDT 24
Finished Mar 19 01:43:11 PM PDT 24
Peak memory 265108 kb
Host smart-5eafbd70-3b2d-44de-a6e8-366ea50533d1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894502766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2894502766
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.875215951
Short name T783
Test name
Test status
Simulation time 67314237 ps
CPU time 8.43 seconds
Started Mar 19 01:33:57 PM PDT 24
Finished Mar 19 01:34:05 PM PDT 24
Peak memory 248512 kb
Host smart-8aced17e-25ed-4511-9dff-dd8130646afc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=875215951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.875215951
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1290885726
Short name T211
Test name
Test status
Simulation time 118463239 ps
CPU time 4.4 seconds
Started Mar 19 01:34:02 PM PDT 24
Finished Mar 19 01:34:06 PM PDT 24
Peak memory 236664 kb
Host smart-5dd04b2f-a982-4701-b079-b0617d3f1e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1290885726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1290885726
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.44480463
Short name T801
Test name
Test status
Simulation time 6516256996 ps
CPU time 105.18 seconds
Started Mar 19 01:33:04 PM PDT 24
Finished Mar 19 01:34:49 PM PDT 24
Peak memory 240300 kb
Host smart-aeffa806-07d9-4cc8-89e0-9c67135e96b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=44480463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.44480463
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3858657617
Short name T348
Test name
Test status
Simulation time 7575417929 ps
CPU time 424.67 seconds
Started Mar 19 01:33:02 PM PDT 24
Finished Mar 19 01:40:07 PM PDT 24
Peak memory 240268 kb
Host smart-acb9fe8d-108c-47e2-988d-cc2d7ee1f8f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3858657617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3858657617
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1730659895
Short name T784
Test name
Test status
Simulation time 142630693 ps
CPU time 10.59 seconds
Started Mar 19 01:33:01 PM PDT 24
Finished Mar 19 01:33:12 PM PDT 24
Peak memory 240228 kb
Host smart-8806e249-8ef9-46cc-b332-26f5b82e16cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1730659895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1730659895
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1812079697
Short name T343
Test name
Test status
Simulation time 130795133 ps
CPU time 10.42 seconds
Started Mar 19 01:32:59 PM PDT 24
Finished Mar 19 01:33:10 PM PDT 24
Peak memory 236908 kb
Host smart-c066711d-4baa-490d-b210-8cf247860718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812079697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1812079697
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.774833756
Short name T346
Test name
Test status
Simulation time 126199190 ps
CPU time 5.05 seconds
Started Mar 19 01:33:00 PM PDT 24
Finished Mar 19 01:33:05 PM PDT 24
Peak memory 238460 kb
Host smart-b06c606f-fb97-4373-ba39-04ecaf49b5e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=774833756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.774833756
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1539703029
Short name T727
Test name
Test status
Simulation time 9778082 ps
CPU time 1.49 seconds
Started Mar 19 01:33:00 PM PDT 24
Finished Mar 19 01:33:02 PM PDT 24
Peak memory 236640 kb
Host smart-6d51e67c-90b6-4102-898e-20f42d0dc119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1539703029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1539703029
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.869801509
Short name T808
Test name
Test status
Simulation time 1834249121 ps
CPU time 16.63 seconds
Started Mar 19 01:33:02 PM PDT 24
Finished Mar 19 01:33:19 PM PDT 24
Peak memory 240316 kb
Host smart-761e36d4-1ee4-4f20-91b9-9c8f24d1c930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869801509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.869801509
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.353949786
Short name T149
Test name
Test status
Simulation time 2312735314 ps
CPU time 148.32 seconds
Started Mar 19 01:33:04 PM PDT 24
Finished Mar 19 01:35:32 PM PDT 24
Peak memory 256972 kb
Host smart-fe82a424-5c0b-4a5e-835c-7f2ae7489318
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=353949786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.353949786
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1215269019
Short name T773
Test name
Test status
Simulation time 4644304256 ps
CPU time 18.6 seconds
Started Mar 19 01:33:00 PM PDT 24
Finished Mar 19 01:33:19 PM PDT 24
Peak memory 252680 kb
Host smart-932f2f4c-336a-4256-9e00-5500f809891d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1215269019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1215269019
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.724465702
Short name T786
Test name
Test status
Simulation time 10303637 ps
CPU time 1.28 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:34:00 PM PDT 24
Peak memory 234716 kb
Host smart-c4e0c516-b4f7-4648-a563-518f7e8e9b21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=724465702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.724465702
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.765244157
Short name T803
Test name
Test status
Simulation time 9676333 ps
CPU time 1.52 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:34:01 PM PDT 24
Peak memory 234824 kb
Host smart-4ffbd52e-466e-46bf-a8db-e98aec4bdc6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=765244157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.765244157
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4031257322
Short name T745
Test name
Test status
Simulation time 10567262 ps
CPU time 1.4 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:34:00 PM PDT 24
Peak memory 236672 kb
Host smart-b519958d-1e66-4a15-b821-7484a64c4eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4031257322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4031257322
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.709614459
Short name T816
Test name
Test status
Simulation time 7731932 ps
CPU time 1.64 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:34:00 PM PDT 24
Peak memory 234784 kb
Host smart-f8666682-d257-4b54-94cb-f070346a0eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=709614459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.709614459
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2379037486
Short name T826
Test name
Test status
Simulation time 6223135 ps
CPU time 1.33 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:34:00 PM PDT 24
Peak memory 235732 kb
Host smart-dc95a7ea-aac3-4261-a2db-3f04652c1a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2379037486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2379037486
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2435289633
Short name T748
Test name
Test status
Simulation time 22788897 ps
CPU time 1.5 seconds
Started Mar 19 01:34:01 PM PDT 24
Finished Mar 19 01:34:03 PM PDT 24
Peak memory 235692 kb
Host smart-4f31fd80-103e-4959-be19-26b73ea36e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2435289633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2435289633
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.783444353
Short name T337
Test name
Test status
Simulation time 14931956 ps
CPU time 1.57 seconds
Started Mar 19 01:34:01 PM PDT 24
Finished Mar 19 01:34:03 PM PDT 24
Peak memory 235752 kb
Host smart-a4ee538d-892b-4ac6-8a93-e40ed42dec28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=783444353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.783444353
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3594906285
Short name T782
Test name
Test status
Simulation time 22997343 ps
CPU time 1.52 seconds
Started Mar 19 01:33:58 PM PDT 24
Finished Mar 19 01:33:59 PM PDT 24
Peak memory 236640 kb
Host smart-c79f87cb-a2f8-4848-8a02-99d24aa912d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3594906285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3594906285
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2550255241
Short name T765
Test name
Test status
Simulation time 23997069 ps
CPU time 1.54 seconds
Started Mar 19 01:34:01 PM PDT 24
Finished Mar 19 01:34:03 PM PDT 24
Peak memory 236632 kb
Host smart-1f9117d4-ea33-477c-8c47-63b68404fbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2550255241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2550255241
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3377926306
Short name T794
Test name
Test status
Simulation time 7409255 ps
CPU time 1.45 seconds
Started Mar 19 01:33:59 PM PDT 24
Finished Mar 19 01:34:00 PM PDT 24
Peak memory 235792 kb
Host smart-1994c64c-38d3-467b-b8a6-4c7c733234f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3377926306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3377926306
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2373233015
Short name T802
Test name
Test status
Simulation time 15206804965 ps
CPU time 123.87 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:35:12 PM PDT 24
Peak memory 240240 kb
Host smart-8c0f617a-3dbd-4ef4-9b4b-681824b20ad4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2373233015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2373233015
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4041098076
Short name T799
Test name
Test status
Simulation time 19652157935 ps
CPU time 371.8 seconds
Started Mar 19 01:33:09 PM PDT 24
Finished Mar 19 01:39:23 PM PDT 24
Peak memory 240320 kb
Host smart-423278c0-b47a-41e6-93aa-10aaf6440cd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4041098076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4041098076
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2162261818
Short name T793
Test name
Test status
Simulation time 59302938 ps
CPU time 5.8 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:33:16 PM PDT 24
Peak memory 240176 kb
Host smart-a37c1017-f367-4695-8eef-55d681a94d1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2162261818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2162261818
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2768756622
Short name T804
Test name
Test status
Simulation time 133943303 ps
CPU time 11.04 seconds
Started Mar 19 01:33:10 PM PDT 24
Finished Mar 19 01:33:22 PM PDT 24
Peak memory 254936 kb
Host smart-f6f80294-e12e-4982-8df1-ebb4a6a55966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768756622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2768756622
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1282429091
Short name T769
Test name
Test status
Simulation time 248512971 ps
CPU time 5.06 seconds
Started Mar 19 01:33:06 PM PDT 24
Finished Mar 19 01:33:13 PM PDT 24
Peak memory 238452 kb
Host smart-c37ef609-a225-4f52-a2f4-ec2cbc11ef9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1282429091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1282429091
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3108248137
Short name T175
Test name
Test status
Simulation time 10162054 ps
CPU time 1.37 seconds
Started Mar 19 01:33:09 PM PDT 24
Finished Mar 19 01:33:12 PM PDT 24
Peak memory 234844 kb
Host smart-51dee0de-31d9-4d85-b5ec-1301147ea09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3108248137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3108248137
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2404266138
Short name T820
Test name
Test status
Simulation time 660240317 ps
CPU time 24.21 seconds
Started Mar 19 01:33:07 PM PDT 24
Finished Mar 19 01:33:32 PM PDT 24
Peak memory 244004 kb
Host smart-4b46cc25-8fe0-452c-8de1-5cd276779953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2404266138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2404266138
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3147220864
Short name T751
Test name
Test status
Simulation time 42321658 ps
CPU time 6.81 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:33:17 PM PDT 24
Peak memory 252260 kb
Host smart-1f1cbf70-0ab0-4363-8180-d9534b0ca8bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147220864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3147220864
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.121941627
Short name T806
Test name
Test status
Simulation time 13167871 ps
CPU time 1.76 seconds
Started Mar 19 01:34:04 PM PDT 24
Finished Mar 19 01:34:06 PM PDT 24
Peak memory 235804 kb
Host smart-30ef35a9-9e1f-4e1b-bc9b-06a25ecca3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=121941627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.121941627
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3583598857
Short name T340
Test name
Test status
Simulation time 11196832 ps
CPU time 1.68 seconds
Started Mar 19 01:34:09 PM PDT 24
Finished Mar 19 01:34:11 PM PDT 24
Peak memory 236632 kb
Host smart-31c7a874-1705-4d4a-8e29-133749b746e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3583598857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3583598857
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3115033632
Short name T830
Test name
Test status
Simulation time 16049879 ps
CPU time 1.41 seconds
Started Mar 19 01:34:06 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 235752 kb
Host smart-4f85cfe4-bc0c-48b1-98af-b8a9d2671bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3115033632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3115033632
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.597960692
Short name T823
Test name
Test status
Simulation time 12559892 ps
CPU time 1.47 seconds
Started Mar 19 01:34:07 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 236608 kb
Host smart-c2c15629-9743-4d84-8ecf-b3d38ee2ad3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=597960692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.597960692
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2233179966
Short name T722
Test name
Test status
Simulation time 20120301 ps
CPU time 1.34 seconds
Started Mar 19 01:34:03 PM PDT 24
Finished Mar 19 01:34:05 PM PDT 24
Peak memory 236456 kb
Host smart-1ffee562-6854-478c-ba9d-f9d120584058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233179966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2233179966
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4131127407
Short name T338
Test name
Test status
Simulation time 20124195 ps
CPU time 1.5 seconds
Started Mar 19 01:34:06 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 235824 kb
Host smart-2e4b2ea9-3b08-4b16-a585-332672f1c751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4131127407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4131127407
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.27943466
Short name T767
Test name
Test status
Simulation time 8467297 ps
CPU time 1.45 seconds
Started Mar 19 01:34:12 PM PDT 24
Finished Mar 19 01:34:14 PM PDT 24
Peak memory 236676 kb
Host smart-4922537f-ab12-4b9f-8711-2bb4a564135b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=27943466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.27943466
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3086566362
Short name T738
Test name
Test status
Simulation time 7674592 ps
CPU time 1.52 seconds
Started Mar 19 01:34:02 PM PDT 24
Finished Mar 19 01:34:04 PM PDT 24
Peak memory 236648 kb
Host smart-5ba0c873-6d35-45b2-9f1d-68a9969f038e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3086566362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3086566362
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.916658719
Short name T743
Test name
Test status
Simulation time 7560255 ps
CPU time 1.5 seconds
Started Mar 19 01:34:06 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 234792 kb
Host smart-4467fcdf-4efa-4c7d-a933-7e368f84b1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916658719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.916658719
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2586092926
Short name T796
Test name
Test status
Simulation time 24388405 ps
CPU time 1.26 seconds
Started Mar 19 01:34:05 PM PDT 24
Finished Mar 19 01:34:06 PM PDT 24
Peak memory 235736 kb
Host smart-39d98f19-071f-4071-bb59-f34fd6216f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2586092926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2586092926
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1795886994
Short name T209
Test name
Test status
Simulation time 4608138180 ps
CPU time 85.6 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:34:34 PM PDT 24
Peak memory 240268 kb
Host smart-8d390ed7-d7e8-41e8-8e5f-7246747b8f27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1795886994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1795886994
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3948962662
Short name T205
Test name
Test status
Simulation time 1671091667 ps
CPU time 112.98 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:35:04 PM PDT 24
Peak memory 240244 kb
Host smart-ea5d20af-1e5f-4c42-a93b-9fb92d039843
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3948962662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3948962662
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.737658715
Short name T735
Test name
Test status
Simulation time 69034660 ps
CPU time 6.1 seconds
Started Mar 19 01:33:07 PM PDT 24
Finished Mar 19 01:33:14 PM PDT 24
Peak memory 240200 kb
Host smart-96273db1-b8a6-43f1-9829-fab6d8d197cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=737658715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.737658715
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3631406373
Short name T771
Test name
Test status
Simulation time 57353387 ps
CPU time 5.35 seconds
Started Mar 19 01:33:13 PM PDT 24
Finished Mar 19 01:33:19 PM PDT 24
Peak memory 240384 kb
Host smart-3afdb20f-210c-4c7b-a676-ceacce107580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631406373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3631406373
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.472880308
Short name T729
Test name
Test status
Simulation time 227912762 ps
CPU time 9.37 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:33:20 PM PDT 24
Peak memory 240200 kb
Host smart-03dc8997-f620-4717-9b17-e4da29b2ff3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=472880308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.472880308
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4032299450
Short name T734
Test name
Test status
Simulation time 26674278 ps
CPU time 1.56 seconds
Started Mar 19 01:33:08 PM PDT 24
Finished Mar 19 01:33:12 PM PDT 24
Peak memory 236668 kb
Host smart-ed786c4c-45d2-4200-92b0-a5b07aefb9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4032299450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4032299450
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.357589869
Short name T757
Test name
Test status
Simulation time 96994380 ps
CPU time 12.19 seconds
Started Mar 19 01:33:12 PM PDT 24
Finished Mar 19 01:33:26 PM PDT 24
Peak memory 243960 kb
Host smart-a1c64bdd-8ef1-46f8-a798-4461a2c8a758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=357589869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.357589869
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2314553237
Short name T153
Test name
Test status
Simulation time 4090976654 ps
CPU time 212.02 seconds
Started Mar 19 01:33:07 PM PDT 24
Finished Mar 19 01:36:40 PM PDT 24
Peak memory 256924 kb
Host smart-ee524304-ee69-44be-bc31-5f20a6328a58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2314553237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2314553237
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2439594917
Short name T805
Test name
Test status
Simulation time 344554715 ps
CPU time 26.45 seconds
Started Mar 19 01:33:07 PM PDT 24
Finished Mar 19 01:33:34 PM PDT 24
Peak memory 248680 kb
Host smart-6b8a3ecc-5eec-4e34-8882-753971ce0a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2439594917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2439594917
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.34933174
Short name T341
Test name
Test status
Simulation time 6317022 ps
CPU time 1.45 seconds
Started Mar 19 01:34:05 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 235736 kb
Host smart-907e1edf-ba98-4b98-8411-e3c6f3bd6cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34933174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.34933174
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2952546299
Short name T720
Test name
Test status
Simulation time 10532787 ps
CPU time 1.47 seconds
Started Mar 19 01:34:06 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 235816 kb
Host smart-5539404b-1382-4826-925d-bafed5065cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2952546299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2952546299
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3467237983
Short name T815
Test name
Test status
Simulation time 12366843 ps
CPU time 1.76 seconds
Started Mar 19 01:34:07 PM PDT 24
Finished Mar 19 01:34:09 PM PDT 24
Peak memory 235760 kb
Host smart-6cd4a5c9-50e7-48f1-9299-95cd8b7fffb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3467237983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3467237983
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3627737231
Short name T774
Test name
Test status
Simulation time 6058650 ps
CPU time 1.48 seconds
Started Mar 19 01:34:08 PM PDT 24
Finished Mar 19 01:34:10 PM PDT 24
Peak memory 236644 kb
Host smart-e57864a6-0752-4dab-a34e-a15ff0545a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3627737231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3627737231
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1901448749
Short name T785
Test name
Test status
Simulation time 19310480 ps
CPU time 1.84 seconds
Started Mar 19 01:34:05 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 235800 kb
Host smart-e93425aa-036d-4ebd-b936-92e0305bcfe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1901448749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1901448749
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2110907767
Short name T336
Test name
Test status
Simulation time 11041796 ps
CPU time 1.3 seconds
Started Mar 19 01:34:04 PM PDT 24
Finished Mar 19 01:34:05 PM PDT 24
Peak memory 236648 kb
Host smart-ec206c63-8123-4d8a-a070-f8f773e4a4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2110907767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2110907767
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3712660474
Short name T742
Test name
Test status
Simulation time 6396871 ps
CPU time 1.38 seconds
Started Mar 19 01:34:04 PM PDT 24
Finished Mar 19 01:34:06 PM PDT 24
Peak memory 236632 kb
Host smart-73625f85-6aa6-4137-8bc4-dde28715f738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3712660474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3712660474
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2162463462
Short name T788
Test name
Test status
Simulation time 12682284 ps
CPU time 1.26 seconds
Started Mar 19 01:34:07 PM PDT 24
Finished Mar 19 01:34:08 PM PDT 24
Peak memory 235668 kb
Host smart-6e7d880d-3984-4acc-a35b-27368668f292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2162463462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2162463462
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1875351547
Short name T176
Test name
Test status
Simulation time 10585744 ps
CPU time 1.38 seconds
Started Mar 19 01:34:05 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 234832 kb
Host smart-8496e4b7-907d-43d4-95f7-43a4af8a7fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1875351547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1875351547
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.298564438
Short name T797
Test name
Test status
Simulation time 293836670 ps
CPU time 6.19 seconds
Started Mar 19 01:33:14 PM PDT 24
Finished Mar 19 01:33:21 PM PDT 24
Peak memory 239576 kb
Host smart-5eb9a840-bbb1-4c20-87a7-845bc328437c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298564438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.298564438
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1754877004
Short name T756
Test name
Test status
Simulation time 102713312 ps
CPU time 5.8 seconds
Started Mar 19 01:33:14 PM PDT 24
Finished Mar 19 01:33:20 PM PDT 24
Peak memory 236492 kb
Host smart-6c53b1c7-943d-4c6d-a2b0-aedae27305c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1754877004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1754877004
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1998501286
Short name T339
Test name
Test status
Simulation time 8552092 ps
CPU time 1.37 seconds
Started Mar 19 01:33:19 PM PDT 24
Finished Mar 19 01:33:21 PM PDT 24
Peak memory 236640 kb
Host smart-186c7f56-d655-4fd0-a101-fadae9ccee71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1998501286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1998501286
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4005497652
Short name T795
Test name
Test status
Simulation time 1377872336 ps
CPU time 51.98 seconds
Started Mar 19 01:33:14 PM PDT 24
Finished Mar 19 01:34:07 PM PDT 24
Peak memory 244788 kb
Host smart-198f15ad-296d-48a2-8068-dd2dc1fe6ec3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4005497652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4005497652
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1505534754
Short name T150
Test name
Test status
Simulation time 8062923549 ps
CPU time 155.03 seconds
Started Mar 19 01:33:07 PM PDT 24
Finished Mar 19 01:35:43 PM PDT 24
Peak memory 256880 kb
Host smart-b4bd6254-b4c9-4d07-aba0-6d4f3627f19f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1505534754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1505534754
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1574436191
Short name T158
Test name
Test status
Simulation time 23962938247 ps
CPU time 488.87 seconds
Started Mar 19 01:33:11 PM PDT 24
Finished Mar 19 01:41:20 PM PDT 24
Peak memory 265224 kb
Host smart-ce5bf918-c4c0-473e-b6f2-602a5209eb17
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574436191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1574436191
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2636885870
Short name T251
Test name
Test status
Simulation time 440213485 ps
CPU time 8.22 seconds
Started Mar 19 01:33:10 PM PDT 24
Finished Mar 19 01:33:19 PM PDT 24
Peak memory 248616 kb
Host smart-be41f143-6d91-4b8a-8bef-2c7c99c1185e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2636885870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2636885870
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.4111315801
Short name T790
Test name
Test status
Simulation time 291498865 ps
CPU time 7.18 seconds
Started Mar 19 01:33:24 PM PDT 24
Finished Mar 19 01:33:33 PM PDT 24
Peak memory 240520 kb
Host smart-8927ff97-e2f1-4782-a97c-c1c7f7e6ab56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111315801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.4111315801
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3182446770
Short name T781
Test name
Test status
Simulation time 570451303 ps
CPU time 5.17 seconds
Started Mar 19 01:33:21 PM PDT 24
Finished Mar 19 01:33:28 PM PDT 24
Peak memory 238516 kb
Host smart-709a531c-8da3-4d6d-a518-21929b526cb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3182446770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3182446770
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.225357815
Short name T759
Test name
Test status
Simulation time 24192651 ps
CPU time 1.35 seconds
Started Mar 19 01:33:24 PM PDT 24
Finished Mar 19 01:33:27 PM PDT 24
Peak memory 236552 kb
Host smart-27c4196b-9188-4cd4-9ae9-26f8fa28f028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=225357815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.225357815
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3645589569
Short name T776
Test name
Test status
Simulation time 505525420 ps
CPU time 33.26 seconds
Started Mar 19 01:33:22 PM PDT 24
Finished Mar 19 01:33:56 PM PDT 24
Peak memory 248472 kb
Host smart-9d4fab92-4dbf-423b-98b4-f170b27f528c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3645589569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3645589569
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.518475129
Short name T167
Test name
Test status
Simulation time 8935121388 ps
CPU time 132.03 seconds
Started Mar 19 01:33:16 PM PDT 24
Finished Mar 19 01:35:28 PM PDT 24
Peak memory 256304 kb
Host smart-e08c5a83-b8f1-4c4a-ab6f-14681057560b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=518475129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.518475129
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1674585868
Short name T140
Test name
Test status
Simulation time 16117833542 ps
CPU time 1136.08 seconds
Started Mar 19 01:33:18 PM PDT 24
Finished Mar 19 01:52:14 PM PDT 24
Peak memory 265328 kb
Host smart-13af0762-09f4-4455-bce3-101b732c8199
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674585868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1674585868
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2535352057
Short name T780
Test name
Test status
Simulation time 77826871 ps
CPU time 6.42 seconds
Started Mar 19 01:33:19 PM PDT 24
Finished Mar 19 01:33:25 PM PDT 24
Peak memory 248572 kb
Host smart-d60041b9-c177-48df-8b0d-f534aa40ce51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2535352057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2535352057
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4144887959
Short name T755
Test name
Test status
Simulation time 34335742 ps
CPU time 5.83 seconds
Started Mar 19 01:33:27 PM PDT 24
Finished Mar 19 01:33:33 PM PDT 24
Peak memory 248532 kb
Host smart-de9e4338-dc57-44f8-8073-0fda6e4fa39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144887959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.4144887959
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1982247522
Short name T814
Test name
Test status
Simulation time 64805663 ps
CPU time 5.84 seconds
Started Mar 19 01:33:28 PM PDT 24
Finished Mar 19 01:33:34 PM PDT 24
Peak memory 236560 kb
Host smart-8d4eff82-db8e-4983-8bcf-4564e3e3ecb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1982247522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1982247522
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4257055724
Short name T777
Test name
Test status
Simulation time 38073573 ps
CPU time 1.32 seconds
Started Mar 19 01:33:21 PM PDT 24
Finished Mar 19 01:33:24 PM PDT 24
Peak memory 236640 kb
Host smart-3d958343-e49a-43e4-92dc-cee36b553f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4257055724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4257055724
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3602309381
Short name T192
Test name
Test status
Simulation time 172971711 ps
CPU time 27.15 seconds
Started Mar 19 01:33:28 PM PDT 24
Finished Mar 19 01:33:56 PM PDT 24
Peak memory 248524 kb
Host smart-eac107e2-adf3-4082-a42d-4597503f2594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3602309381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3602309381
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1432681184
Short name T144
Test name
Test status
Simulation time 1344817145 ps
CPU time 130.75 seconds
Started Mar 19 01:33:22 PM PDT 24
Finished Mar 19 01:35:34 PM PDT 24
Peak memory 256908 kb
Host smart-9c906e14-aee6-4621-ab17-9fffbd44b236
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1432681184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1432681184
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.235632121
Short name T154
Test name
Test status
Simulation time 2584591696 ps
CPU time 374.67 seconds
Started Mar 19 01:33:24 PM PDT 24
Finished Mar 19 01:39:39 PM PDT 24
Peak memory 265228 kb
Host smart-da800e84-78e2-4738-a3df-69f09b2f3857
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235632121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.235632121
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2712093467
Short name T827
Test name
Test status
Simulation time 195438123 ps
CPU time 6.28 seconds
Started Mar 19 01:33:22 PM PDT 24
Finished Mar 19 01:33:29 PM PDT 24
Peak memory 248600 kb
Host smart-4fefeaa8-0af9-43cc-b020-4d0fd0969e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2712093467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2712093467
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1426052572
Short name T345
Test name
Test status
Simulation time 229195450 ps
CPU time 9.51 seconds
Started Mar 19 01:33:27 PM PDT 24
Finished Mar 19 01:33:36 PM PDT 24
Peak memory 256016 kb
Host smart-bd60fa80-e63f-468d-af6a-f0de5ac1c8ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426052572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1426052572
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.100096586
Short name T207
Test name
Test status
Simulation time 170453194 ps
CPU time 5.39 seconds
Started Mar 19 01:33:29 PM PDT 24
Finished Mar 19 01:33:34 PM PDT 24
Peak memory 240072 kb
Host smart-1947c0fc-a162-4943-92df-0fe379c2263c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=100096586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.100096586
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2692044826
Short name T778
Test name
Test status
Simulation time 6448180 ps
CPU time 1.38 seconds
Started Mar 19 01:33:31 PM PDT 24
Finished Mar 19 01:33:32 PM PDT 24
Peak memory 234612 kb
Host smart-64eb05fe-3784-43f8-a0cd-f030e755e018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2692044826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2692044826
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4215110540
Short name T208
Test name
Test status
Simulation time 671870236 ps
CPU time 47.56 seconds
Started Mar 19 01:33:28 PM PDT 24
Finished Mar 19 01:34:16 PM PDT 24
Peak memory 244820 kb
Host smart-a1a99753-8d70-4270-90fd-fbdef579acd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4215110540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4215110540
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3342979736
Short name T142
Test name
Test status
Simulation time 5189081020 ps
CPU time 334.46 seconds
Started Mar 19 01:33:27 PM PDT 24
Finished Mar 19 01:39:02 PM PDT 24
Peak memory 265144 kb
Host smart-141ab228-d559-48d4-9f60-dbe66afcc60e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3342979736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3342979736
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1026922879
Short name T718
Test name
Test status
Simulation time 93027354 ps
CPU time 6.61 seconds
Started Mar 19 01:33:29 PM PDT 24
Finished Mar 19 01:33:36 PM PDT 24
Peak memory 240356 kb
Host smart-df0e49a1-9521-4f29-a3b4-a109e208c806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1026922879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1026922879
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3642312970
Short name T813
Test name
Test status
Simulation time 35675244 ps
CPU time 2.96 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:33:38 PM PDT 24
Peak memory 236656 kb
Host smart-46e6e08f-ae0a-4380-99c0-52ff965da5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3642312970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3642312970
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1689087891
Short name T829
Test name
Test status
Simulation time 152651256 ps
CPU time 11.24 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:33:46 PM PDT 24
Peak memory 239780 kb
Host smart-174d6a9e-b759-43a7-b168-1de30cd48a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689087891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1689087891
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1000269220
Short name T731
Test name
Test status
Simulation time 130059727 ps
CPU time 9.3 seconds
Started Mar 19 01:33:34 PM PDT 24
Finished Mar 19 01:33:44 PM PDT 24
Peak memory 240224 kb
Host smart-4c7f37a1-bd8e-4ec3-8dfa-dbf75b3fd33c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1000269220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1000269220
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3073834295
Short name T791
Test name
Test status
Simulation time 7297237 ps
CPU time 1.52 seconds
Started Mar 19 01:33:35 PM PDT 24
Finished Mar 19 01:33:40 PM PDT 24
Peak memory 236668 kb
Host smart-102329d9-cd7c-4da2-920f-7920998a59ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3073834295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3073834295
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1763577233
Short name T761
Test name
Test status
Simulation time 254985873 ps
CPU time 19.02 seconds
Started Mar 19 01:33:34 PM PDT 24
Finished Mar 19 01:33:54 PM PDT 24
Peak memory 244836 kb
Host smart-715c408e-cc86-4741-b793-1ce67c2963ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1763577233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1763577233
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1661735334
Short name T151
Test name
Test status
Simulation time 811644826 ps
CPU time 101.82 seconds
Started Mar 19 01:33:28 PM PDT 24
Finished Mar 19 01:35:10 PM PDT 24
Peak memory 256416 kb
Host smart-01e509be-fb00-428f-a3c6-79b1cb744404
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1661735334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1661735334
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2983921660
Short name T766
Test name
Test status
Simulation time 79457916 ps
CPU time 10.71 seconds
Started Mar 19 01:33:30 PM PDT 24
Finished Mar 19 01:33:41 PM PDT 24
Peak memory 248444 kb
Host smart-0b6493af-84a2-4ebe-87cf-19210785687d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2983921660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2983921660
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.4250782102
Short name T129
Test name
Test status
Simulation time 52256766895 ps
CPU time 1388.71 seconds
Started Mar 19 01:58:58 PM PDT 24
Finished Mar 19 02:22:07 PM PDT 24
Peak memory 287864 kb
Host smart-fae9928f-04d1-42d2-8b0c-97d059cf4b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250782102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4250782102
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1053505123
Short name T426
Test name
Test status
Simulation time 2888778542 ps
CPU time 44.32 seconds
Started Mar 19 01:58:58 PM PDT 24
Finished Mar 19 01:59:42 PM PDT 24
Peak memory 240748 kb
Host smart-ea865d47-2663-4838-afd5-9597cd0ddad0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1053505123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1053505123
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1926384668
Short name T676
Test name
Test status
Simulation time 2619026009 ps
CPU time 51.72 seconds
Started Mar 19 01:58:53 PM PDT 24
Finished Mar 19 01:59:45 PM PDT 24
Peak memory 257044 kb
Host smart-4b6bd333-71c1-4098-b073-f411170d6a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19263
84668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1926384668
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2077769740
Short name T672
Test name
Test status
Simulation time 2738196987 ps
CPU time 83.76 seconds
Started Mar 19 01:58:52 PM PDT 24
Finished Mar 19 02:00:15 PM PDT 24
Peak memory 255572 kb
Host smart-163ad39d-0df1-433d-9903-de2adefe9a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20777
69740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2077769740
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3523801121
Short name T678
Test name
Test status
Simulation time 10054376980 ps
CPU time 736.06 seconds
Started Mar 19 01:58:59 PM PDT 24
Finished Mar 19 02:11:16 PM PDT 24
Peak memory 265336 kb
Host smart-2f727585-fa85-454c-a00d-eab6cfaf3f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523801121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3523801121
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2877601778
Short name T545
Test name
Test status
Simulation time 28062872675 ps
CPU time 2056.44 seconds
Started Mar 19 01:58:59 PM PDT 24
Finished Mar 19 02:33:17 PM PDT 24
Peak memory 289088 kb
Host smart-bc41dcc8-ed6d-41e1-ad12-c2e7fa6ed2b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877601778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2877601778
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1162895784
Short name T39
Test name
Test status
Simulation time 297259117 ps
CPU time 18.1 seconds
Started Mar 19 01:58:52 PM PDT 24
Finished Mar 19 01:59:11 PM PDT 24
Peak memory 249196 kb
Host smart-ff698bbd-88a8-4b8d-be44-a8671e41cdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628
95784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1162895784
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3878976504
Short name T49
Test name
Test status
Simulation time 270264660 ps
CPU time 5.07 seconds
Started Mar 19 01:58:58 PM PDT 24
Finished Mar 19 01:59:05 PM PDT 24
Peak memory 239056 kb
Host smart-c91efbb0-f0c2-4019-8d9e-fc5d36b0dde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38789
76504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3878976504
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2894236659
Short name T37
Test name
Test status
Simulation time 528544303 ps
CPU time 24.68 seconds
Started Mar 19 01:58:59 PM PDT 24
Finished Mar 19 01:59:25 PM PDT 24
Peak memory 269812 kb
Host smart-42543028-82d7-4504-89e5-88f33e833850
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2894236659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2894236659
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.532972425
Short name T682
Test name
Test status
Simulation time 451846102 ps
CPU time 8.19 seconds
Started Mar 19 01:58:58 PM PDT 24
Finished Mar 19 01:59:06 PM PDT 24
Peak memory 248892 kb
Host smart-e4cfa956-8faf-48f1-9372-68c05bdca67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53297
2425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.532972425
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3185702727
Short name T369
Test name
Test status
Simulation time 5667925596 ps
CPU time 135.96 seconds
Started Mar 19 01:58:58 PM PDT 24
Finished Mar 19 02:01:14 PM PDT 24
Peak memory 257028 kb
Host smart-86c2482b-af38-43d5-a697-17066051d479
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185702727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3185702727
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3585928945
Short name T466
Test name
Test status
Simulation time 28983603579 ps
CPU time 2056.58 seconds
Started Mar 19 02:02:03 PM PDT 24
Finished Mar 19 02:36:20 PM PDT 24
Peak memory 289596 kb
Host smart-2b9ba6cb-790f-49bf-bccb-d781c652d49f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585928945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3585928945
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1415714188
Short name T656
Test name
Test status
Simulation time 2910941979 ps
CPU time 16.34 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:02:26 PM PDT 24
Peak memory 240696 kb
Host smart-106ce083-06c2-4752-8391-d304e3897c3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1415714188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1415714188
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.466464031
Short name T668
Test name
Test status
Simulation time 3291271751 ps
CPU time 211.8 seconds
Started Mar 19 02:02:38 PM PDT 24
Finished Mar 19 02:06:10 PM PDT 24
Peak memory 256896 kb
Host smart-5b275943-4e8d-4381-aec3-73481ef74132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46646
4031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.466464031
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2049590877
Short name T367
Test name
Test status
Simulation time 328283464 ps
CPU time 31.72 seconds
Started Mar 19 02:02:08 PM PDT 24
Finished Mar 19 02:02:40 PM PDT 24
Peak memory 256032 kb
Host smart-5aa27d5b-a869-43ec-a344-c22378a2a850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495
90877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2049590877
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2095811142
Short name T634
Test name
Test status
Simulation time 9848065628 ps
CPU time 1066.58 seconds
Started Mar 19 02:02:36 PM PDT 24
Finished Mar 19 02:20:23 PM PDT 24
Peak memory 271528 kb
Host smart-72e52f97-fca4-43a6-8128-b0a29158aa50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095811142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2095811142
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1581852709
Short name T276
Test name
Test status
Simulation time 74216640398 ps
CPU time 2445.66 seconds
Started Mar 19 02:02:38 PM PDT 24
Finished Mar 19 02:43:24 PM PDT 24
Peak memory 288864 kb
Host smart-b4175704-be21-4644-a0ce-f937270502ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581852709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1581852709
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2165086280
Short name T314
Test name
Test status
Simulation time 20414644415 ps
CPU time 213.92 seconds
Started Mar 19 02:01:55 PM PDT 24
Finished Mar 19 02:05:29 PM PDT 24
Peak memory 248932 kb
Host smart-b0e491da-b95e-4e77-a324-414238525020
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165086280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2165086280
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1092914494
Short name T643
Test name
Test status
Simulation time 608810434 ps
CPU time 12.07 seconds
Started Mar 19 02:02:17 PM PDT 24
Finished Mar 19 02:02:29 PM PDT 24
Peak memory 248812 kb
Host smart-d647374b-4561-4faa-b913-6fc6cd8ad756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
14494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1092914494
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2373413243
Short name T615
Test name
Test status
Simulation time 981730388 ps
CPU time 15.35 seconds
Started Mar 19 02:02:05 PM PDT 24
Finished Mar 19 02:02:20 PM PDT 24
Peak memory 248680 kb
Host smart-9e26803a-a92f-4e8d-bbee-d06c10a7e30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734
13243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2373413243
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1818149838
Short name T12
Test name
Test status
Simulation time 1576872277 ps
CPU time 22.38 seconds
Started Mar 19 02:02:07 PM PDT 24
Finished Mar 19 02:02:30 PM PDT 24
Peak memory 274484 kb
Host smart-06526878-6ce0-45c7-a34b-246de42d78e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1818149838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1818149838
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2143452174
Short name T259
Test name
Test status
Simulation time 686681807 ps
CPU time 23.16 seconds
Started Mar 19 02:01:55 PM PDT 24
Finished Mar 19 02:02:19 PM PDT 24
Peak memory 255384 kb
Host smart-ce16a2c5-b1b3-4b7f-bdd7-9b3f03625fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
52174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2143452174
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3282503374
Short name T696
Test name
Test status
Simulation time 3906040907 ps
CPU time 56.58 seconds
Started Mar 19 02:02:15 PM PDT 24
Finished Mar 19 02:03:12 PM PDT 24
Peak memory 256508 kb
Host smart-288d821c-d6cd-43c3-a217-69cb728902a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
03374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3282503374
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2830984532
Short name T441
Test name
Test status
Simulation time 16147247369 ps
CPU time 1589.63 seconds
Started Mar 19 02:02:17 PM PDT 24
Finished Mar 19 02:28:46 PM PDT 24
Peak memory 289256 kb
Host smart-75f1cd00-935a-4928-b30d-3f6d8fd245dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830984532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2830984532
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2797883049
Short name T249
Test name
Test status
Simulation time 677288956089 ps
CPU time 7365.06 seconds
Started Mar 19 02:02:06 PM PDT 24
Finished Mar 19 04:04:52 PM PDT 24
Peak memory 306180 kb
Host smart-a5ca4b21-5511-4394-9355-2baf6114ae53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797883049 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2797883049
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1116145117
Short name T230
Test name
Test status
Simulation time 18809467 ps
CPU time 2.48 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:04 PM PDT 24
Peak memory 249056 kb
Host smart-22b5c5eb-bbf2-4770-8168-e555d37396ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1116145117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1116145117
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3925012593
Short name T617
Test name
Test status
Simulation time 224536576326 ps
CPU time 3552.19 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 03:02:14 PM PDT 24
Peak memory 289308 kb
Host smart-75978756-827a-45a1-b49a-3a9fa39ed27b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925012593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3925012593
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2242133102
Short name T523
Test name
Test status
Simulation time 4111786969 ps
CPU time 56.78 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:03:58 PM PDT 24
Peak memory 240732 kb
Host smart-a3c99a60-6c39-49c0-a56e-b6f787e2c07f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2242133102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2242133102
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.387664600
Short name T403
Test name
Test status
Simulation time 4391135056 ps
CPU time 159.28 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:05:41 PM PDT 24
Peak memory 255516 kb
Host smart-3ce5be89-25ff-487d-b292-17cd1bf22211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38766
4600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.387664600
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2608745500
Short name T519
Test name
Test status
Simulation time 991190370 ps
CPU time 64.25 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:04:07 PM PDT 24
Peak memory 255604 kb
Host smart-64628f6e-a39b-49ef-9197-76d37389c420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26087
45500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2608745500
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1724738217
Short name T212
Test name
Test status
Simulation time 19267005201 ps
CPU time 1682.11 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:31:05 PM PDT 24
Peak memory 289108 kb
Host smart-a40cbb9a-c1f9-4d96-b9e4-d0456f9c19be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724738217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1724738217
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1483721186
Short name T43
Test name
Test status
Simulation time 70788993351 ps
CPU time 1364.82 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:25:46 PM PDT 24
Peak memory 285848 kb
Host smart-53a03afe-c411-40c3-8260-b80e52a548a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483721186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1483721186
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2714028102
Short name T308
Test name
Test status
Simulation time 5603757880 ps
CPU time 226.79 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:06:50 PM PDT 24
Peak memory 248144 kb
Host smart-b621b278-cae5-411b-8263-113b0ea430f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714028102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2714028102
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2034371297
Short name T431
Test name
Test status
Simulation time 503215350 ps
CPU time 26.48 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:28 PM PDT 24
Peak memory 256092 kb
Host smart-4f0737e9-bd49-4bfe-8515-2b5dc5697ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20343
71297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2034371297
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.454754303
Short name T657
Test name
Test status
Simulation time 323713286 ps
CPU time 33.17 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:35 PM PDT 24
Peak memory 255616 kb
Host smart-68f6e56a-4b3b-4475-9354-49351bde9bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45475
4303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.454754303
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2039753561
Short name T683
Test name
Test status
Simulation time 602039091 ps
CPU time 30.88 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:03:34 PM PDT 24
Peak memory 248860 kb
Host smart-045b6e87-e59c-4d04-9e83-078a5a8076b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20397
53561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2039753561
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4223664147
Short name T458
Test name
Test status
Simulation time 272400896 ps
CPU time 36.07 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:38 PM PDT 24
Peak memory 256092 kb
Host smart-7dcaa676-13fb-408c-b76f-8ea17126146a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42236
64147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4223664147
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1157213135
Short name T272
Test name
Test status
Simulation time 69668280275 ps
CPU time 1840.81 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:33:43 PM PDT 24
Peak memory 289048 kb
Host smart-d5325c95-eedc-480a-9e06-73067eeb0322
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157213135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1157213135
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2243976836
Short name T232
Test name
Test status
Simulation time 92751756 ps
CPU time 4.06 seconds
Started Mar 19 02:03:11 PM PDT 24
Finished Mar 19 02:03:15 PM PDT 24
Peak memory 248992 kb
Host smart-60263430-0d63-4dd4-9e55-7c2c3a1dc6ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2243976836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2243976836
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3873473077
Short name T525
Test name
Test status
Simulation time 31320603462 ps
CPU time 1748.48 seconds
Started Mar 19 02:02:58 PM PDT 24
Finished Mar 19 02:32:09 PM PDT 24
Peak memory 268392 kb
Host smart-8e4c9cb4-ee83-48eb-8af9-dbab9cb244d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873473077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3873473077
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1106907058
Short name T498
Test name
Test status
Simulation time 519853903 ps
CPU time 8.69 seconds
Started Mar 19 02:03:12 PM PDT 24
Finished Mar 19 02:03:21 PM PDT 24
Peak memory 240572 kb
Host smart-39cfd268-7e8a-47ea-b7bb-52cb6cbec4ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1106907058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1106907058
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3046862854
Short name T359
Test name
Test status
Simulation time 1942460770 ps
CPU time 73.18 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:04:15 PM PDT 24
Peak memory 249220 kb
Host smart-5a3ec1a7-bbd9-43e0-90e9-46f9d84cc7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
62854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3046862854
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1239759313
Short name T566
Test name
Test status
Simulation time 535208329 ps
CPU time 11.76 seconds
Started Mar 19 02:02:42 PM PDT 24
Finished Mar 19 02:02:54 PM PDT 24
Peak memory 253588 kb
Host smart-abae9bb6-766f-4da3-9f95-1fee643d9808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
59313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1239759313
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.210794442
Short name T76
Test name
Test status
Simulation time 13030449467 ps
CPU time 1241.04 seconds
Started Mar 19 02:03:12 PM PDT 24
Finished Mar 19 02:23:54 PM PDT 24
Peak memory 289336 kb
Host smart-55faa372-dfc4-4c6a-9b38-7134e78b89b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210794442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.210794442
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3528717780
Short name T457
Test name
Test status
Simulation time 1069220848 ps
CPU time 61.92 seconds
Started Mar 19 02:03:05 PM PDT 24
Finished Mar 19 02:04:08 PM PDT 24
Peak memory 249132 kb
Host smart-fa71552a-2c71-405e-b2c9-611884278129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35287
17780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3528717780
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3901282966
Short name T131
Test name
Test status
Simulation time 318264660 ps
CPU time 13.88 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:03:16 PM PDT 24
Peak memory 248860 kb
Host smart-91fc4781-0a99-457b-8f62-c15a3e7f8206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
82966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3901282966
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1902508368
Short name T443
Test name
Test status
Simulation time 848766280 ps
CPU time 28.7 seconds
Started Mar 19 02:03:05 PM PDT 24
Finished Mar 19 02:03:35 PM PDT 24
Peak memory 254968 kb
Host smart-85270837-cd15-4c54-af46-d0f39dd622ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19025
08368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1902508368
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3687031383
Short name T660
Test name
Test status
Simulation time 236214892 ps
CPU time 12.58 seconds
Started Mar 19 02:02:58 PM PDT 24
Finished Mar 19 02:03:14 PM PDT 24
Peak memory 254668 kb
Host smart-83a0ffcc-5bea-48ad-8b25-149550357031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
31383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3687031383
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1097564227
Short name T234
Test name
Test status
Simulation time 62419165 ps
CPU time 3.32 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:06 PM PDT 24
Peak memory 249096 kb
Host smart-0d3fe9c2-3264-4342-8fe4-0538d4aa030e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1097564227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1097564227
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1514441619
Short name T375
Test name
Test status
Simulation time 9169090935 ps
CPU time 1140.12 seconds
Started Mar 19 02:03:04 PM PDT 24
Finished Mar 19 02:22:05 PM PDT 24
Peak memory 281712 kb
Host smart-462b7102-0dc7-4eb1-a8fe-12a0f9554399
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514441619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1514441619
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2877510350
Short name T651
Test name
Test status
Simulation time 1147234463 ps
CPU time 26.31 seconds
Started Mar 19 02:03:12 PM PDT 24
Finished Mar 19 02:03:38 PM PDT 24
Peak memory 240524 kb
Host smart-03babc9a-28f4-4eff-8cd3-b056f711d28a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2877510350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2877510350
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.486252705
Short name T395
Test name
Test status
Simulation time 1857356699 ps
CPU time 93.1 seconds
Started Mar 19 02:03:06 PM PDT 24
Finished Mar 19 02:04:39 PM PDT 24
Peak memory 256832 kb
Host smart-773d5189-76de-4234-8c19-a745f4124cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48625
2705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.486252705
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3004799900
Short name T422
Test name
Test status
Simulation time 374421586 ps
CPU time 15.03 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:03:26 PM PDT 24
Peak memory 248888 kb
Host smart-81b99553-b13f-4f9f-a1fa-f4b35615fddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
99900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3004799900
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3737837958
Short name T632
Test name
Test status
Simulation time 264176848070 ps
CPU time 3538.5 seconds
Started Mar 19 02:03:12 PM PDT 24
Finished Mar 19 03:02:11 PM PDT 24
Peak memory 289184 kb
Host smart-2f93b59f-a53a-4062-b880-dc94ac05324b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737837958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3737837958
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.583016813
Short name T631
Test name
Test status
Simulation time 127270094165 ps
CPU time 1990.64 seconds
Started Mar 19 02:03:06 PM PDT 24
Finished Mar 19 02:36:17 PM PDT 24
Peak memory 284128 kb
Host smart-691f11b5-68b1-48e8-9328-3c717716d2fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583016813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.583016813
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2036549911
Short name T317
Test name
Test status
Simulation time 77518430282 ps
CPU time 496.81 seconds
Started Mar 19 02:03:07 PM PDT 24
Finished Mar 19 02:11:24 PM PDT 24
Peak memory 248084 kb
Host smart-beefc5ee-3789-49d8-8d93-ea034d3e98d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036549911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2036549911
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1480854256
Short name T655
Test name
Test status
Simulation time 384083565 ps
CPU time 27.38 seconds
Started Mar 19 02:03:12 PM PDT 24
Finished Mar 19 02:03:40 PM PDT 24
Peak memory 255580 kb
Host smart-d681d5c2-a35a-4303-836b-d62a1059bc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14808
54256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1480854256
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2934848002
Short name T430
Test name
Test status
Simulation time 538859943 ps
CPU time 32.28 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:34 PM PDT 24
Peak memory 255504 kb
Host smart-ef95a533-bb82-43c0-ab7d-81860c8055e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29348
48002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2934848002
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1050048522
Short name T124
Test name
Test status
Simulation time 665323015 ps
CPU time 42.71 seconds
Started Mar 19 02:03:08 PM PDT 24
Finished Mar 19 02:03:51 PM PDT 24
Peak memory 255380 kb
Host smart-e7feb05a-51f7-481d-907e-2b4ca14a0cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10500
48522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1050048522
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1371073001
Short name T542
Test name
Test status
Simulation time 131376112 ps
CPU time 5.61 seconds
Started Mar 19 02:03:03 PM PDT 24
Finished Mar 19 02:03:09 PM PDT 24
Peak memory 240688 kb
Host smart-45eeb917-0d3d-40d7-a431-ab53b858de1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13710
73001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1371073001
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.295481990
Short name T241
Test name
Test status
Simulation time 47519202 ps
CPU time 2.43 seconds
Started Mar 19 02:03:11 PM PDT 24
Finished Mar 19 02:03:13 PM PDT 24
Peak memory 249116 kb
Host smart-c720122a-eedc-4a51-a7a7-18d52542ffd6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=295481990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.295481990
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.315557139
Short name T640
Test name
Test status
Simulation time 24104921932 ps
CPU time 1488.51 seconds
Started Mar 19 02:03:11 PM PDT 24
Finished Mar 19 02:28:00 PM PDT 24
Peak memory 272056 kb
Host smart-c5cd338f-4086-4b7a-a90d-7b6b03afdd4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315557139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.315557139
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1382825244
Short name T588
Test name
Test status
Simulation time 338629026 ps
CPU time 10.84 seconds
Started Mar 19 02:03:13 PM PDT 24
Finished Mar 19 02:03:24 PM PDT 24
Peak memory 248868 kb
Host smart-0b26c1a0-1c6b-4a0c-ba76-16f3bd724f0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1382825244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1382825244
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2039607785
Short name T597
Test name
Test status
Simulation time 4776492076 ps
CPU time 247.92 seconds
Started Mar 19 02:03:13 PM PDT 24
Finished Mar 19 02:07:21 PM PDT 24
Peak memory 250876 kb
Host smart-db7d91fb-4965-45e4-9eb3-ae6bb2fb495c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20396
07785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2039607785
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2491170431
Short name T117
Test name
Test status
Simulation time 8425672894 ps
CPU time 65.85 seconds
Started Mar 19 02:03:05 PM PDT 24
Finished Mar 19 02:04:12 PM PDT 24
Peak memory 255552 kb
Host smart-8dd26700-9d2c-4700-8f78-fb5cfb806406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24911
70431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2491170431
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.742641584
Short name T546
Test name
Test status
Simulation time 266711887658 ps
CPU time 1257.27 seconds
Started Mar 19 02:04:47 PM PDT 24
Finished Mar 19 02:25:45 PM PDT 24
Peak memory 289040 kb
Host smart-0b1af87a-f86c-45e9-b637-06f373d7370e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742641584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.742641584
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3692392337
Short name T387
Test name
Test status
Simulation time 127827075390 ps
CPU time 1818.14 seconds
Started Mar 19 02:03:11 PM PDT 24
Finished Mar 19 02:33:29 PM PDT 24
Peak memory 273044 kb
Host smart-326f48c0-fec2-4cf9-8d7a-e23424bc7733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692392337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3692392337
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.684348544
Short name T297
Test name
Test status
Simulation time 47090857376 ps
CPU time 511.58 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:11:42 PM PDT 24
Peak memory 247832 kb
Host smart-2465d035-0f78-46fc-ab39-1c75c45405e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684348544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.684348544
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2607803351
Short name T289
Test name
Test status
Simulation time 1387156071 ps
CPU time 28.32 seconds
Started Mar 19 02:03:13 PM PDT 24
Finished Mar 19 02:03:41 PM PDT 24
Peak memory 248768 kb
Host smart-8c150552-e9e2-4873-ad99-b0b924c33e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26078
03351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2607803351
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2852944962
Short name T611
Test name
Test status
Simulation time 1208995296 ps
CPU time 30.64 seconds
Started Mar 19 02:03:08 PM PDT 24
Finished Mar 19 02:03:39 PM PDT 24
Peak memory 247516 kb
Host smart-6358a5f7-80e3-4a75-9153-da2c5b316758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529
44962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2852944962
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1104483623
Short name T260
Test name
Test status
Simulation time 1279950252 ps
CPU time 72.4 seconds
Started Mar 19 02:03:14 PM PDT 24
Finished Mar 19 02:04:27 PM PDT 24
Peak memory 254716 kb
Host smart-ff283c34-ce4f-4274-88ff-cc3cd938d5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11044
83623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1104483623
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.430244011
Short name T701
Test name
Test status
Simulation time 177228767 ps
CPU time 22.1 seconds
Started Mar 19 02:04:48 PM PDT 24
Finished Mar 19 02:05:10 PM PDT 24
Peak memory 249080 kb
Host smart-537c8284-ff1d-475c-af23-70a71b547f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43024
4011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.430244011
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.334512900
Short name T635
Test name
Test status
Simulation time 213452531922 ps
CPU time 1362.04 seconds
Started Mar 19 02:03:11 PM PDT 24
Finished Mar 19 02:25:53 PM PDT 24
Peak memory 289424 kb
Host smart-d91cc4c1-844b-4eae-bd2a-12c9565615ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334512900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.334512900
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.213588185
Short name T229
Test name
Test status
Simulation time 31413056 ps
CPU time 2.56 seconds
Started Mar 19 02:03:27 PM PDT 24
Finished Mar 19 02:03:30 PM PDT 24
Peak memory 248980 kb
Host smart-d0809acb-5c6b-443d-a99e-1445e7c6d00d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=213588185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.213588185
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3699236167
Short name T423
Test name
Test status
Simulation time 1448699814 ps
CPU time 14.53 seconds
Started Mar 19 02:03:23 PM PDT 24
Finished Mar 19 02:03:38 PM PDT 24
Peak memory 248852 kb
Host smart-e40ceb82-5919-4594-a565-241c17c14804
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3699236167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3699236167
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3136729607
Short name T520
Test name
Test status
Simulation time 3773685773 ps
CPU time 245.32 seconds
Started Mar 19 02:03:24 PM PDT 24
Finished Mar 19 02:07:29 PM PDT 24
Peak memory 256840 kb
Host smart-7e828cc1-a749-4f3a-b149-c1855471be45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
29607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3136729607
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1230319597
Short name T487
Test name
Test status
Simulation time 341335274 ps
CPU time 22.99 seconds
Started Mar 19 02:03:24 PM PDT 24
Finished Mar 19 02:03:47 PM PDT 24
Peak memory 248904 kb
Host smart-6c776ab9-5078-49a7-a88b-7c4b128e164c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12303
19597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1230319597
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2262621728
Short name T274
Test name
Test status
Simulation time 37144830131 ps
CPU time 758.4 seconds
Started Mar 19 02:03:24 PM PDT 24
Finished Mar 19 02:16:03 PM PDT 24
Peak memory 273068 kb
Host smart-a331d265-84c2-4057-a1d6-70d716935d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262621728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2262621728
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3509131030
Short name T578
Test name
Test status
Simulation time 7598477583 ps
CPU time 149.36 seconds
Started Mar 19 02:03:23 PM PDT 24
Finished Mar 19 02:05:53 PM PDT 24
Peak memory 246896 kb
Host smart-51aa8649-3222-4bdc-b3bf-9f0ff21b199d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509131030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3509131030
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2022672099
Short name T517
Test name
Test status
Simulation time 66117867 ps
CPU time 3.74 seconds
Started Mar 19 02:04:48 PM PDT 24
Finished Mar 19 02:04:52 PM PDT 24
Peak memory 240672 kb
Host smart-f7370ff1-cfdf-442a-b20d-cba452805392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20226
72099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2022672099
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1693540905
Short name T460
Test name
Test status
Simulation time 360975384 ps
CPU time 26.55 seconds
Started Mar 19 02:03:24 PM PDT 24
Finished Mar 19 02:03:51 PM PDT 24
Peak memory 247280 kb
Host smart-3d97c9e4-fc4e-419a-b22a-a63cbdccb9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16935
40905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1693540905
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1103794049
Short name T118
Test name
Test status
Simulation time 1010887623 ps
CPU time 43.08 seconds
Started Mar 19 02:03:23 PM PDT 24
Finished Mar 19 02:04:07 PM PDT 24
Peak memory 248896 kb
Host smart-b56b35f5-2421-48d5-a750-08693b689c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11037
94049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1103794049
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3976144794
Short name T279
Test name
Test status
Simulation time 407910642 ps
CPU time 36.23 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:03:47 PM PDT 24
Peak memory 248860 kb
Host smart-28b60d44-f7e2-43a7-8857-b163ab8fe88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761
44794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3976144794
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2007285860
Short name T667
Test name
Test status
Simulation time 193834943820 ps
CPU time 3074.34 seconds
Started Mar 19 02:03:24 PM PDT 24
Finished Mar 19 02:54:39 PM PDT 24
Peak memory 289484 kb
Host smart-1f1c42aa-8c44-4f55-b115-7a1b74c7efcd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007285860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2007285860
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.979774221
Short name T15
Test name
Test status
Simulation time 20188086076 ps
CPU time 780.52 seconds
Started Mar 19 02:03:52 PM PDT 24
Finished Mar 19 02:16:53 PM PDT 24
Peak memory 267380 kb
Host smart-61eb3a32-781d-4d03-ac15-9e88f3058b13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979774221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.979774221
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1045776839
Short name T511
Test name
Test status
Simulation time 238771647 ps
CPU time 12.43 seconds
Started Mar 19 02:03:45 PM PDT 24
Finished Mar 19 02:03:58 PM PDT 24
Peak memory 248888 kb
Host smart-6d47da94-991e-494e-af07-b15ab16d0878
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1045776839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1045776839
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2349860638
Short name T246
Test name
Test status
Simulation time 92023257 ps
CPU time 9.8 seconds
Started Mar 19 02:03:33 PM PDT 24
Finished Mar 19 02:03:43 PM PDT 24
Peak memory 255080 kb
Host smart-c8a9969e-f5d5-4ca7-a530-608f767b5e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23498
60638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2349860638
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2789490377
Short name T94
Test name
Test status
Simulation time 1026026828 ps
CPU time 32.68 seconds
Started Mar 19 02:03:32 PM PDT 24
Finished Mar 19 02:04:06 PM PDT 24
Peak memory 248848 kb
Host smart-90365b53-6f9f-461e-8070-cc85c579fd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
90377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2789490377
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3231149087
Short name T681
Test name
Test status
Simulation time 44319364239 ps
CPU time 1063.55 seconds
Started Mar 19 02:03:44 PM PDT 24
Finished Mar 19 02:21:28 PM PDT 24
Peak memory 281712 kb
Host smart-a924778f-f83f-4f71-9b97-1187c3ec9392
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231149087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3231149087
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.165298634
Short name T220
Test name
Test status
Simulation time 28914811054 ps
CPU time 2039.79 seconds
Started Mar 19 02:03:45 PM PDT 24
Finished Mar 19 02:37:45 PM PDT 24
Peak memory 288640 kb
Host smart-4e1947ea-811a-4f35-a195-653751d134a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165298634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.165298634
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3113742395
Short name T130
Test name
Test status
Simulation time 2767759492 ps
CPU time 54.15 seconds
Started Mar 19 02:04:52 PM PDT 24
Finished Mar 19 02:05:47 PM PDT 24
Peak memory 249096 kb
Host smart-f7c12067-5d6b-42d3-841d-96159d77d77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31137
42395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3113742395
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3701978378
Short name T514
Test name
Test status
Simulation time 607971131 ps
CPU time 10.23 seconds
Started Mar 19 02:04:48 PM PDT 24
Finished Mar 19 02:04:58 PM PDT 24
Peak memory 251780 kb
Host smart-e30d41c9-4b38-4ea4-b90d-5d08b683ad3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019
78378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3701978378
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1223757680
Short name T462
Test name
Test status
Simulation time 69172157 ps
CPU time 5.08 seconds
Started Mar 19 02:03:33 PM PDT 24
Finished Mar 19 02:03:39 PM PDT 24
Peak memory 247388 kb
Host smart-322fa04a-5781-4ce2-b8e2-3e8a3d89a0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12237
57680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1223757680
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1831522669
Short name T437
Test name
Test status
Simulation time 2715178899 ps
CPU time 19.9 seconds
Started Mar 19 02:03:29 PM PDT 24
Finished Mar 19 02:03:49 PM PDT 24
Peak memory 248944 kb
Host smart-76be9ff5-a12b-490b-972f-15e88a41c865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18315
22669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1831522669
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4211367143
Short name T575
Test name
Test status
Simulation time 109568072833 ps
CPU time 1561.07 seconds
Started Mar 19 02:03:46 PM PDT 24
Finished Mar 19 02:29:48 PM PDT 24
Peak memory 273492 kb
Host smart-12d43177-8baa-4b87-9938-dd866abf657d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211367143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4211367143
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3010561665
Short name T233
Test name
Test status
Simulation time 30666867 ps
CPU time 3.14 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:02 PM PDT 24
Peak memory 249032 kb
Host smart-67388d53-1b56-4415-bb73-ecfbfb5d6c17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3010561665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3010561665
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2777301158
Short name T45
Test name
Test status
Simulation time 148615720870 ps
CPU time 1554.47 seconds
Started Mar 19 02:04:52 PM PDT 24
Finished Mar 19 02:30:46 PM PDT 24
Peak memory 271688 kb
Host smart-fd576246-333f-4048-bd12-5009d95d64a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777301158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2777301158
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.80464121
Short name T645
Test name
Test status
Simulation time 1630419636 ps
CPU time 13.26 seconds
Started Mar 19 02:03:59 PM PDT 24
Finished Mar 19 02:04:13 PM PDT 24
Peak memory 248804 kb
Host smart-8049394b-9fb4-40a7-8587-8fd976cc7b2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=80464121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.80464121
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.623318246
Short name T283
Test name
Test status
Simulation time 19061240650 ps
CPU time 242.74 seconds
Started Mar 19 02:03:59 PM PDT 24
Finished Mar 19 02:08:02 PM PDT 24
Peak memory 257076 kb
Host smart-5d9fb620-8408-4736-82b4-1838b0b51170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62331
8246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.623318246
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4053134623
Short name T90
Test name
Test status
Simulation time 1426944430 ps
CPU time 51.37 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:49 PM PDT 24
Peak memory 255908 kb
Host smart-5bdc86db-631f-4a14-8012-b832a99bf0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40531
34623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4053134623
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3091018309
Short name T658
Test name
Test status
Simulation time 36632481008 ps
CPU time 2192.08 seconds
Started Mar 19 02:04:00 PM PDT 24
Finished Mar 19 02:40:32 PM PDT 24
Peak memory 289432 kb
Host smart-e27cec30-2522-415a-8733-9aebd2fd0529
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091018309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3091018309
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.242369947
Short name T547
Test name
Test status
Simulation time 4588987360 ps
CPU time 106.33 seconds
Started Mar 19 02:03:59 PM PDT 24
Finished Mar 19 02:05:46 PM PDT 24
Peak memory 246996 kb
Host smart-caa970f9-bfce-4db7-afbd-01a4a42f3026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242369947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.242369947
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1147862207
Short name T363
Test name
Test status
Simulation time 823015434 ps
CPU time 45.65 seconds
Started Mar 19 02:03:57 PM PDT 24
Finished Mar 19 02:04:43 PM PDT 24
Peak memory 248760 kb
Host smart-e3ef2624-e74c-45c6-afc3-22f7dec01a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
62207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1147862207
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2471313570
Short name T84
Test name
Test status
Simulation time 853404570 ps
CPU time 20.85 seconds
Started Mar 19 02:03:57 PM PDT 24
Finished Mar 19 02:04:18 PM PDT 24
Peak memory 256000 kb
Host smart-79bf59c0-ec62-417d-a17a-073f8b3b6e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24713
13570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2471313570
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.72223747
Short name T704
Test name
Test status
Simulation time 1080999532 ps
CPU time 21.2 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:19 PM PDT 24
Peak memory 256032 kb
Host smart-e238bf50-dce2-464f-bd38-460f2e58c011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72223
747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.72223747
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2452168768
Short name T483
Test name
Test status
Simulation time 1384858128 ps
CPU time 42.82 seconds
Started Mar 19 02:03:44 PM PDT 24
Finished Mar 19 02:04:27 PM PDT 24
Peak memory 249040 kb
Host smart-286e470a-fcc8-40ab-90d9-4e6ad0bfd374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
68768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2452168768
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3583361427
Short name T242
Test name
Test status
Simulation time 155194399 ps
CPU time 3.43 seconds
Started Mar 19 02:04:09 PM PDT 24
Finished Mar 19 02:04:13 PM PDT 24
Peak memory 249132 kb
Host smart-54860a46-ac27-489d-b642-6d594a3b70ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3583361427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3583361427
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3041894922
Short name T673
Test name
Test status
Simulation time 21567175642 ps
CPU time 1452.39 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:28:11 PM PDT 24
Peak memory 267284 kb
Host smart-a8bf89dc-4be9-4812-b651-3339c3299d6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041894922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3041894922
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3503281195
Short name T530
Test name
Test status
Simulation time 9689763083 ps
CPU time 43.82 seconds
Started Mar 19 02:04:47 PM PDT 24
Finished Mar 19 02:05:32 PM PDT 24
Peak memory 240744 kb
Host smart-27a2e59c-3b88-4992-8501-59743a9950f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3503281195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3503281195
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2794028421
Short name T628
Test name
Test status
Simulation time 4387030672 ps
CPU time 249.9 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:08:08 PM PDT 24
Peak memory 256880 kb
Host smart-da7e83a3-66e1-4d23-8b07-aa456a6b72ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27940
28421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2794028421
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.257587051
Short name T551
Test name
Test status
Simulation time 310039711 ps
CPU time 27.2 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:26 PM PDT 24
Peak memory 254668 kb
Host smart-7da72a0c-e866-434c-8c02-469eea9777ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25758
7051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.257587051
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4090967180
Short name T219
Test name
Test status
Simulation time 48099170579 ps
CPU time 2243.42 seconds
Started Mar 19 02:04:08 PM PDT 24
Finished Mar 19 02:41:31 PM PDT 24
Peak memory 283888 kb
Host smart-03b637d6-8fee-4dbf-8acd-53eb49270638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090967180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4090967180
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3663112182
Short name T301
Test name
Test status
Simulation time 6611661910 ps
CPU time 287.29 seconds
Started Mar 19 02:04:49 PM PDT 24
Finished Mar 19 02:09:36 PM PDT 24
Peak memory 248104 kb
Host smart-c29bc126-32b7-413d-889a-a73d95c12cad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663112182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3663112182
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4243215922
Short name T389
Test name
Test status
Simulation time 111136879 ps
CPU time 4.27 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:02 PM PDT 24
Peak memory 240696 kb
Host smart-9505acd7-2619-41e4-a5de-fe82b9cb4f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42432
15922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4243215922
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3542226136
Short name T703
Test name
Test status
Simulation time 271458139 ps
CPU time 31.18 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:29 PM PDT 24
Peak memory 248872 kb
Host smart-0c755b53-1e56-4b80-85ae-f26d23f490ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35422
26136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3542226136
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3608073866
Short name T292
Test name
Test status
Simulation time 360498482 ps
CPU time 25.93 seconds
Started Mar 19 02:03:58 PM PDT 24
Finished Mar 19 02:04:24 PM PDT 24
Peak memory 255368 kb
Host smart-2a42b3bb-adcb-457f-87aa-bd9eaa5e5cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
73866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3608073866
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2389177522
Short name T503
Test name
Test status
Simulation time 3100111901 ps
CPU time 41.54 seconds
Started Mar 19 02:04:00 PM PDT 24
Finished Mar 19 02:04:42 PM PDT 24
Peak memory 256008 kb
Host smart-1bc28e80-bfbd-4cab-a715-17cc69aba4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23891
77522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2389177522
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.871622315
Short name T268
Test name
Test status
Simulation time 151529448219 ps
CPU time 2622.27 seconds
Started Mar 19 02:04:10 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 289316 kb
Host smart-3884697a-a739-4ad1-b26a-da0b6e3d2480
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871622315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.871622315
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.489325570
Short name T536
Test name
Test status
Simulation time 14746710598 ps
CPU time 1182.78 seconds
Started Mar 19 02:04:08 PM PDT 24
Finished Mar 19 02:23:51 PM PDT 24
Peak memory 287244 kb
Host smart-ecd66a68-7ee8-44a9-a1dd-c59ab49f3bb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489325570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.489325570
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2627561936
Short name T414
Test name
Test status
Simulation time 359911308 ps
CPU time 18.69 seconds
Started Mar 19 02:04:52 PM PDT 24
Finished Mar 19 02:05:11 PM PDT 24
Peak memory 240632 kb
Host smart-b199437b-f54b-4b27-b293-0297b9091788
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2627561936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2627561936
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1016312951
Short name T700
Test name
Test status
Simulation time 2338443308 ps
CPU time 158.49 seconds
Started Mar 19 02:04:09 PM PDT 24
Finished Mar 19 02:06:47 PM PDT 24
Peak memory 256656 kb
Host smart-b11a15ad-d2fd-491f-a856-d075aa385eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10163
12951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1016312951
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2115484491
Short name T675
Test name
Test status
Simulation time 153898351 ps
CPU time 6.2 seconds
Started Mar 19 02:04:11 PM PDT 24
Finished Mar 19 02:04:17 PM PDT 24
Peak memory 250900 kb
Host smart-0b1edca3-2d52-47b1-9434-b32b7e8dec08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21154
84491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2115484491
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2550484095
Short name T334
Test name
Test status
Simulation time 215561633126 ps
CPU time 3220.94 seconds
Started Mar 19 02:04:08 PM PDT 24
Finished Mar 19 02:57:49 PM PDT 24
Peak memory 289360 kb
Host smart-6b287fab-83cf-4ca1-9772-af5c819cd576
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550484095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2550484095
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.815189415
Short name T629
Test name
Test status
Simulation time 40421885580 ps
CPU time 2723.56 seconds
Started Mar 19 02:04:07 PM PDT 24
Finished Mar 19 02:49:31 PM PDT 24
Peak memory 289432 kb
Host smart-0a76bd3c-c7ac-4313-b232-ce3507c63e46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815189415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.815189415
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4124385778
Short name T400
Test name
Test status
Simulation time 4700726264 ps
CPU time 110.46 seconds
Started Mar 19 02:04:09 PM PDT 24
Finished Mar 19 02:06:00 PM PDT 24
Peak memory 248884 kb
Host smart-ecaa7edd-7149-4904-968e-3d254bc96604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124385778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4124385778
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.11656217
Short name T446
Test name
Test status
Simulation time 1441280649 ps
CPU time 43.97 seconds
Started Mar 19 02:04:11 PM PDT 24
Finished Mar 19 02:04:55 PM PDT 24
Peak memory 248856 kb
Host smart-88a674aa-bb42-4890-9baa-462862b742d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.11656217
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4028098462
Short name T535
Test name
Test status
Simulation time 233636064 ps
CPU time 23.31 seconds
Started Mar 19 02:04:09 PM PDT 24
Finished Mar 19 02:04:32 PM PDT 24
Peak memory 255640 kb
Host smart-09acbd0a-c306-440b-be81-13f4e85386c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
98462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4028098462
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.244582069
Short name T3
Test name
Test status
Simulation time 116940272 ps
CPU time 17.31 seconds
Started Mar 19 02:04:46 PM PDT 24
Finished Mar 19 02:05:03 PM PDT 24
Peak memory 254972 kb
Host smart-b486d8b4-07f7-459f-9254-6ad9eacdeda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24458
2069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.244582069
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3300331790
Short name T461
Test name
Test status
Simulation time 157131543 ps
CPU time 9.1 seconds
Started Mar 19 02:04:08 PM PDT 24
Finished Mar 19 02:04:18 PM PDT 24
Peak memory 256920 kb
Host smart-5844b019-82d6-479c-9e17-c2e35178ab9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33003
31790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3300331790
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1512736783
Short name T22
Test name
Test status
Simulation time 75482229368 ps
CPU time 2727.35 seconds
Started Mar 19 02:04:09 PM PDT 24
Finished Mar 19 02:49:36 PM PDT 24
Peak memory 289356 kb
Host smart-16d2b860-1dfe-421f-b959-6229ad4caa51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512736783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1512736783
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3842567357
Short name T243
Test name
Test status
Simulation time 94799280 ps
CPU time 3.68 seconds
Started Mar 19 02:04:20 PM PDT 24
Finished Mar 19 02:04:24 PM PDT 24
Peak memory 249112 kb
Host smart-7d8e2203-44bf-405b-ab01-47509a9b3ac0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3842567357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3842567357
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.4154621910
Short name T679
Test name
Test status
Simulation time 37318695998 ps
CPU time 1404.33 seconds
Started Mar 19 02:04:48 PM PDT 24
Finished Mar 19 02:28:12 PM PDT 24
Peak memory 284568 kb
Host smart-13a95863-3de4-46eb-a4f0-36c374fe1539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154621910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4154621910
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2275861653
Short name T451
Test name
Test status
Simulation time 16879122483 ps
CPU time 71.05 seconds
Started Mar 19 02:04:48 PM PDT 24
Finished Mar 19 02:05:59 PM PDT 24
Peak memory 240712 kb
Host smart-1b6fe8c4-f213-4e75-a084-01bc86b48c2f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2275861653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2275861653
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.931313295
Short name T444
Test name
Test status
Simulation time 4512677834 ps
CPU time 282.61 seconds
Started Mar 19 02:04:21 PM PDT 24
Finished Mar 19 02:09:04 PM PDT 24
Peak memory 251008 kb
Host smart-b2668448-9807-4186-b98e-100c1484bf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93131
3295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.931313295
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1860153418
Short name T610
Test name
Test status
Simulation time 5640580083 ps
CPU time 22.85 seconds
Started Mar 19 02:04:20 PM PDT 24
Finished Mar 19 02:04:43 PM PDT 24
Peak memory 255004 kb
Host smart-a88f1135-fd21-4a15-8e62-de50d2993f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18601
53418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1860153418
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.897511005
Short name T522
Test name
Test status
Simulation time 58027685087 ps
CPU time 1232.82 seconds
Started Mar 19 02:04:20 PM PDT 24
Finished Mar 19 02:24:53 PM PDT 24
Peak memory 273316 kb
Host smart-a70fd7a6-b254-4f16-98aa-d50b90b7bc4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897511005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.897511005
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4171617376
Short name T224
Test name
Test status
Simulation time 128356312173 ps
CPU time 1607.34 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 02:31:39 PM PDT 24
Peak memory 288908 kb
Host smart-585523ad-72d2-4954-8004-e2bf04264c3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171617376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4171617376
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.318427272
Short name T521
Test name
Test status
Simulation time 6726062600 ps
CPU time 214.27 seconds
Started Mar 19 02:04:20 PM PDT 24
Finished Mar 19 02:07:55 PM PDT 24
Peak memory 247040 kb
Host smart-602e60ed-3bd9-4738-919f-032a298503ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318427272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.318427272
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1070513956
Short name T355
Test name
Test status
Simulation time 1661894092 ps
CPU time 52.29 seconds
Started Mar 19 02:04:19 PM PDT 24
Finished Mar 19 02:05:11 PM PDT 24
Peak memory 255956 kb
Host smart-77017d92-d07d-4687-bab0-a7be82ab82b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
13956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1070513956
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1946613834
Short name T421
Test name
Test status
Simulation time 139998326 ps
CPU time 9.59 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 02:05:01 PM PDT 24
Peak memory 249164 kb
Host smart-dd1e07e5-1719-43dc-9e18-305342074f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19466
13834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1946613834
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2545135417
Short name T88
Test name
Test status
Simulation time 364421511 ps
CPU time 12.33 seconds
Started Mar 19 02:04:46 PM PDT 24
Finished Mar 19 02:04:58 PM PDT 24
Peak memory 255940 kb
Host smart-bc4b3794-542c-427b-8dde-1b110ea20561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
35417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2545135417
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3463366411
Short name T558
Test name
Test status
Simulation time 680487777 ps
CPU time 46.06 seconds
Started Mar 19 02:04:19 PM PDT 24
Finished Mar 19 02:05:06 PM PDT 24
Peak memory 256208 kb
Host smart-09893aaa-389f-400d-9c62-072c9ebeaabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34633
66411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3463366411
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.574749024
Short name T484
Test name
Test status
Simulation time 13687614559 ps
CPU time 1224.9 seconds
Started Mar 19 02:04:19 PM PDT 24
Finished Mar 19 02:24:45 PM PDT 24
Peak memory 284284 kb
Host smart-b2083269-2b09-4439-b031-21257f916a18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574749024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.574749024
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3769995322
Short name T62
Test name
Test status
Simulation time 225343816011 ps
CPU time 4173.94 seconds
Started Mar 19 02:04:47 PM PDT 24
Finished Mar 19 03:14:22 PM PDT 24
Peak memory 305620 kb
Host smart-7a086489-dfdb-4651-a18c-d1808a7a17b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769995322 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3769995322
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3995644926
Short name T238
Test name
Test status
Simulation time 41541219 ps
CPU time 2.92 seconds
Started Mar 19 02:02:01 PM PDT 24
Finished Mar 19 02:02:04 PM PDT 24
Peak memory 249104 kb
Host smart-c906f892-1ae9-42b2-96b8-82215fe7e8a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3995644926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3995644926
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1604185786
Short name T198
Test name
Test status
Simulation time 10498288202 ps
CPU time 944 seconds
Started Mar 19 02:02:02 PM PDT 24
Finished Mar 19 02:17:46 PM PDT 24
Peak memory 284544 kb
Host smart-54287449-af43-4c8c-a0fe-961f99e1fe44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604185786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1604185786
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1072327975
Short name T417
Test name
Test status
Simulation time 140324877 ps
CPU time 8.98 seconds
Started Mar 19 02:02:27 PM PDT 24
Finished Mar 19 02:02:36 PM PDT 24
Peak memory 240596 kb
Host smart-50106cbf-9bdf-401b-8b39-d06c3fafa012
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1072327975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1072327975
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1797709567
Short name T420
Test name
Test status
Simulation time 13368311727 ps
CPU time 65.64 seconds
Started Mar 19 02:02:20 PM PDT 24
Finished Mar 19 02:03:26 PM PDT 24
Peak memory 255100 kb
Host smart-e8a0e3c6-edef-4cf1-bdce-c541387691b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977
09567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1797709567
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3278186214
Short name T376
Test name
Test status
Simulation time 758697313 ps
CPU time 15.46 seconds
Started Mar 19 02:02:14 PM PDT 24
Finished Mar 19 02:02:30 PM PDT 24
Peak memory 254892 kb
Host smart-9e626bad-fcd7-47d6-b153-76e7ccb3ccd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32781
86214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3278186214
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3515080708
Short name T619
Test name
Test status
Simulation time 39589583123 ps
CPU time 2176.02 seconds
Started Mar 19 02:02:14 PM PDT 24
Finished Mar 19 02:38:30 PM PDT 24
Peak memory 284556 kb
Host smart-8b1faf4f-c634-49ca-bc22-2cc1d7c4c34c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515080708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3515080708
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3312975725
Short name T659
Test name
Test status
Simulation time 26056615453 ps
CPU time 893.25 seconds
Started Mar 19 02:02:07 PM PDT 24
Finished Mar 19 02:17:01 PM PDT 24
Peak memory 273500 kb
Host smart-36981efc-7841-4272-aa6b-a6fd3c5f79c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312975725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3312975725
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2065396329
Short name T42
Test name
Test status
Simulation time 21096759615 ps
CPU time 233.91 seconds
Started Mar 19 02:01:36 PM PDT 24
Finished Mar 19 02:05:30 PM PDT 24
Peak memory 247852 kb
Host smart-f749af8e-915e-4742-933b-c46c54d0d06f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065396329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2065396329
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2316411112
Short name T386
Test name
Test status
Simulation time 1656219275 ps
CPU time 36.28 seconds
Started Mar 19 02:02:40 PM PDT 24
Finished Mar 19 02:03:17 PM PDT 24
Peak memory 256020 kb
Host smart-357fdf2c-f6cd-4837-be58-c38662309a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23164
11112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2316411112
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.469196514
Short name T697
Test name
Test status
Simulation time 4188319245 ps
CPU time 71.32 seconds
Started Mar 19 02:02:20 PM PDT 24
Finished Mar 19 02:03:31 PM PDT 24
Peak memory 248916 kb
Host smart-2cf1cf36-2a01-4eed-9e0f-a735af5bc310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46919
6514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.469196514
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2715423882
Short name T38
Test name
Test status
Simulation time 416204339 ps
CPU time 24.97 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:02:35 PM PDT 24
Peak memory 265260 kb
Host smart-793c5959-3cf2-4bfe-a80c-3617d351c212
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2715423882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2715423882
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1751190864
Short name T509
Test name
Test status
Simulation time 689065658 ps
CPU time 12.36 seconds
Started Mar 19 02:02:09 PM PDT 24
Finished Mar 19 02:02:21 PM PDT 24
Peak memory 247328 kb
Host smart-daa41761-26e7-426a-b5e5-23fe173d61a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17511
90864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1751190864
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1253510233
Short name T499
Test name
Test status
Simulation time 3109623255 ps
CPU time 40.12 seconds
Started Mar 19 02:02:37 PM PDT 24
Finished Mar 19 02:03:18 PM PDT 24
Peak memory 248928 kb
Host smart-d17fa59a-fa6e-47f4-bc6f-7751a50d1917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12535
10233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1253510233
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.113278310
Short name T107
Test name
Test status
Simulation time 28231721400 ps
CPU time 1546.53 seconds
Started Mar 19 02:02:36 PM PDT 24
Finished Mar 19 02:28:23 PM PDT 24
Peak memory 289424 kb
Host smart-4d9e6e7e-ecfa-4016-a912-79bc8da56917
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113278310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.113278310
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3037923553
Short name T83
Test name
Test status
Simulation time 21818224124 ps
CPU time 1440.65 seconds
Started Mar 19 02:04:33 PM PDT 24
Finished Mar 19 02:28:34 PM PDT 24
Peak memory 289336 kb
Host smart-301508fa-5093-483e-954d-6720c327aec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037923553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3037923553
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1954897411
Short name T473
Test name
Test status
Simulation time 3250368244 ps
CPU time 251.8 seconds
Started Mar 19 02:04:32 PM PDT 24
Finished Mar 19 02:08:44 PM PDT 24
Peak memory 256656 kb
Host smart-74aebbf4-5b98-4ca8-8f8c-a9054822040a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19548
97411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1954897411
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1969194695
Short name T506
Test name
Test status
Simulation time 786710011 ps
CPU time 47 seconds
Started Mar 19 02:04:48 PM PDT 24
Finished Mar 19 02:05:35 PM PDT 24
Peak memory 254784 kb
Host smart-7630f803-535f-4158-aa85-639c4d9ce17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19691
94695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1969194695
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2457829647
Short name T565
Test name
Test status
Simulation time 21171338316 ps
CPU time 1275.92 seconds
Started Mar 19 02:04:41 PM PDT 24
Finished Mar 19 02:25:58 PM PDT 24
Peak memory 272228 kb
Host smart-a85e145c-402d-4041-a51a-9d8ba26ca88a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457829647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2457829647
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2999477962
Short name T553
Test name
Test status
Simulation time 8449875439 ps
CPU time 181.24 seconds
Started Mar 19 02:04:32 PM PDT 24
Finished Mar 19 02:07:33 PM PDT 24
Peak memory 248920 kb
Host smart-d3d6fa9b-59c5-4cb1-86bd-0e7a851f77b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999477962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2999477962
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.4288727693
Short name T102
Test name
Test status
Simulation time 849048393 ps
CPU time 58.48 seconds
Started Mar 19 02:04:33 PM PDT 24
Finished Mar 19 02:05:31 PM PDT 24
Peak memory 256740 kb
Host smart-7b877c0a-fdc4-4cc0-be0e-bc74ec8c7954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
27693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.4288727693
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2114986361
Short name T533
Test name
Test status
Simulation time 1420562231 ps
CPU time 37.67 seconds
Started Mar 19 02:04:32 PM PDT 24
Finished Mar 19 02:05:09 PM PDT 24
Peak memory 255580 kb
Host smart-706374c5-8f0f-4cfa-8939-56240afdd9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21149
86361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2114986361
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.270246179
Short name T125
Test name
Test status
Simulation time 389832622 ps
CPU time 49.08 seconds
Started Mar 19 02:04:31 PM PDT 24
Finished Mar 19 02:05:21 PM PDT 24
Peak memory 247888 kb
Host smart-676fad0b-9b8a-459c-a713-0289b6718392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27024
6179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.270246179
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1607282822
Short name T493
Test name
Test status
Simulation time 330136458 ps
CPU time 11.84 seconds
Started Mar 19 02:04:20 PM PDT 24
Finished Mar 19 02:04:32 PM PDT 24
Peak memory 249012 kb
Host smart-c217e2e6-ed51-4cdd-bdc0-3c6e6df4e5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16072
82822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1607282822
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2228013957
Short name T539
Test name
Test status
Simulation time 49433027110 ps
CPU time 2693.84 seconds
Started Mar 19 02:04:47 PM PDT 24
Finished Mar 19 02:49:42 PM PDT 24
Peak memory 289084 kb
Host smart-c8be2fb0-1944-4117-a5a8-dbfe45779c7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228013957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2228013957
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2769857291
Short name T584
Test name
Test status
Simulation time 18150718842 ps
CPU time 257.89 seconds
Started Mar 19 02:04:45 PM PDT 24
Finished Mar 19 02:09:04 PM PDT 24
Peak memory 250940 kb
Host smart-3314b884-d99a-4070-9506-be0a9b19eeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27698
57291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2769857291
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.965094306
Short name T695
Test name
Test status
Simulation time 72876876 ps
CPU time 7.6 seconds
Started Mar 19 02:04:43 PM PDT 24
Finished Mar 19 02:04:51 PM PDT 24
Peak memory 251648 kb
Host smart-d23c9c32-ab40-4b38-98e6-43e59226ae7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96509
4306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.965094306
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1726157570
Short name T312
Test name
Test status
Simulation time 33502310123 ps
CPU time 2287.42 seconds
Started Mar 19 02:04:41 PM PDT 24
Finished Mar 19 02:42:50 PM PDT 24
Peak memory 288524 kb
Host smart-59577ef1-e464-4e80-8a09-8c8256c22df3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726157570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1726157570
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3854058737
Short name T377
Test name
Test status
Simulation time 17984878471 ps
CPU time 1302.28 seconds
Started Mar 19 02:04:41 PM PDT 24
Finished Mar 19 02:26:25 PM PDT 24
Peak memory 288744 kb
Host smart-5042ddec-2073-4745-9c06-77c51ce7e546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854058737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3854058737
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2874984843
Short name T306
Test name
Test status
Simulation time 65074367626 ps
CPU time 608.06 seconds
Started Mar 19 02:04:49 PM PDT 24
Finished Mar 19 02:14:57 PM PDT 24
Peak memory 247792 kb
Host smart-47414898-9b10-4c09-a284-a220aebad404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874984843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2874984843
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1433050881
Short name T469
Test name
Test status
Simulation time 53353094 ps
CPU time 4.66 seconds
Started Mar 19 02:04:30 PM PDT 24
Finished Mar 19 02:04:35 PM PDT 24
Peak memory 240668 kb
Host smart-2e226740-657c-4b19-bf06-2e6f1b364c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
50881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1433050881
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2697972227
Short name T609
Test name
Test status
Simulation time 236248158 ps
CPU time 18.98 seconds
Started Mar 19 02:04:33 PM PDT 24
Finished Mar 19 02:04:52 PM PDT 24
Peak memory 255204 kb
Host smart-5258d186-3897-4084-94e9-ec2bb9ab3637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26979
72227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2697972227
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1245626081
Short name T398
Test name
Test status
Simulation time 866869667 ps
CPU time 31.87 seconds
Started Mar 19 02:04:40 PM PDT 24
Finished Mar 19 02:05:14 PM PDT 24
Peak memory 255460 kb
Host smart-4a02202a-9663-44cf-bb72-23f95806a653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12456
26081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1245626081
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2211186640
Short name T468
Test name
Test status
Simulation time 1382769884 ps
CPU time 22.49 seconds
Started Mar 19 02:04:32 PM PDT 24
Finished Mar 19 02:04:54 PM PDT 24
Peak memory 257044 kb
Host smart-a28939cc-b2ee-45ab-8764-c6372153b407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22111
86640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2211186640
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1261211754
Short name T101
Test name
Test status
Simulation time 327992717585 ps
CPU time 4657.71 seconds
Started Mar 19 02:04:39 PM PDT 24
Finished Mar 19 03:22:18 PM PDT 24
Peak memory 297376 kb
Host smart-2944b456-8cc4-4f76-9ea2-32184724fcec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261211754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1261211754
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1291803445
Short name T114
Test name
Test status
Simulation time 32413415225 ps
CPU time 1625.71 seconds
Started Mar 19 02:04:42 PM PDT 24
Finished Mar 19 02:31:48 PM PDT 24
Peak memory 282848 kb
Host smart-d6e5fd7b-10a7-4285-8aef-02ffb60932e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291803445 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1291803445
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3527203927
Short name T216
Test name
Test status
Simulation time 6049258298 ps
CPU time 526.03 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 02:13:37 PM PDT 24
Peak memory 265312 kb
Host smart-8ce4cbbf-f364-4599-8c16-b2def969eb65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527203927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3527203927
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1316326822
Short name T416
Test name
Test status
Simulation time 6267393781 ps
CPU time 336.8 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 02:10:28 PM PDT 24
Peak memory 250944 kb
Host smart-d2dc5583-2e4a-4ab1-96eb-afc561a383c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13163
26822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1316326822
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3462877140
Short name T693
Test name
Test status
Simulation time 118757526 ps
CPU time 8.98 seconds
Started Mar 19 02:04:54 PM PDT 24
Finished Mar 19 02:05:03 PM PDT 24
Peak memory 248868 kb
Host smart-b1e06b35-80a5-4807-b04e-f9a42e57e08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34628
77140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3462877140
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2451743070
Short name T329
Test name
Test status
Simulation time 86535562331 ps
CPU time 2697.37 seconds
Started Mar 19 02:04:50 PM PDT 24
Finished Mar 19 02:49:49 PM PDT 24
Peak memory 289032 kb
Host smart-deeecd95-4928-43fb-a503-c90c863633c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451743070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2451743070
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3044716676
Short name T69
Test name
Test status
Simulation time 98482511740 ps
CPU time 2937.47 seconds
Started Mar 19 02:04:50 PM PDT 24
Finished Mar 19 02:53:49 PM PDT 24
Peak memory 286828 kb
Host smart-2a64e509-78df-43de-a21b-87cb4e76c557
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044716676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3044716676
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.984989831
Short name T318
Test name
Test status
Simulation time 34471037842 ps
CPU time 491.38 seconds
Started Mar 19 02:04:53 PM PDT 24
Finished Mar 19 02:13:05 PM PDT 24
Peak memory 247836 kb
Host smart-e94c69e3-a3e7-407f-ac60-69e349328762
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984989831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.984989831
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3473348993
Short name T589
Test name
Test status
Simulation time 45324539 ps
CPU time 4.54 seconds
Started Mar 19 02:04:41 PM PDT 24
Finished Mar 19 02:04:47 PM PDT 24
Peak memory 240640 kb
Host smart-b61f1c47-d4ec-4ca7-90a2-d91e9d0c5e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34733
48993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3473348993
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3635983744
Short name T576
Test name
Test status
Simulation time 391974519 ps
CPU time 9.86 seconds
Started Mar 19 02:04:40 PM PDT 24
Finished Mar 19 02:04:49 PM PDT 24
Peak memory 252656 kb
Host smart-f5bc8db4-ab40-46ee-ae11-dd9f6a7979db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36359
83744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3635983744
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.362758468
Short name T557
Test name
Test status
Simulation time 875560831 ps
CPU time 61.34 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 02:05:53 PM PDT 24
Peak memory 255380 kb
Host smart-b0d3f2dc-4dea-4eae-92bf-18936bd265d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36275
8468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.362758468
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1648934721
Short name T464
Test name
Test status
Simulation time 375200441 ps
CPU time 37.03 seconds
Started Mar 19 02:04:41 PM PDT 24
Finished Mar 19 02:05:19 PM PDT 24
Peak memory 255792 kb
Host smart-fad3c6a3-a5ab-447e-9907-60623fe551f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16489
34721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1648934721
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1789645001
Short name T55
Test name
Test status
Simulation time 6504214350 ps
CPU time 245.54 seconds
Started Mar 19 02:04:54 PM PDT 24
Finished Mar 19 02:09:00 PM PDT 24
Peak memory 257108 kb
Host smart-e8d4881d-9ae3-4186-8c6b-72dd6f0662fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789645001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1789645001
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4216405494
Short name T29
Test name
Test status
Simulation time 29295691350 ps
CPU time 2539.17 seconds
Started Mar 19 02:04:50 PM PDT 24
Finished Mar 19 02:47:10 PM PDT 24
Peak memory 289952 kb
Host smart-98b70bde-2ba6-4551-9bc6-fa0864158bae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216405494 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4216405494
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1587246083
Short name T67
Test name
Test status
Simulation time 9050028286 ps
CPU time 866.48 seconds
Started Mar 19 02:05:01 PM PDT 24
Finished Mar 19 02:19:29 PM PDT 24
Peak memory 267384 kb
Host smart-6cb49606-384f-4a33-b91e-8b64e9580455
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587246083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1587246083
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3698764217
Short name T606
Test name
Test status
Simulation time 16223457098 ps
CPU time 229.74 seconds
Started Mar 19 02:05:02 PM PDT 24
Finished Mar 19 02:08:54 PM PDT 24
Peak memory 256596 kb
Host smart-2f9e8e8b-0d38-4c73-a08c-cf85f962fafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36987
64217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3698764217
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.595184254
Short name T563
Test name
Test status
Simulation time 725554801 ps
CPU time 46.6 seconds
Started Mar 19 02:05:01 PM PDT 24
Finished Mar 19 02:05:49 PM PDT 24
Peak memory 249160 kb
Host smart-fb356ba6-25fa-4d5c-9381-23440dddd42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59518
4254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.595184254
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.539161739
Short name T637
Test name
Test status
Simulation time 175426335832 ps
CPU time 2761.95 seconds
Started Mar 19 02:05:01 PM PDT 24
Finished Mar 19 02:51:05 PM PDT 24
Peak memory 281128 kb
Host smart-6d7ece7c-8587-4445-8887-b389eb92bf15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539161739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.539161739
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1452177625
Short name T488
Test name
Test status
Simulation time 897823238 ps
CPU time 56.67 seconds
Started Mar 19 02:04:54 PM PDT 24
Finished Mar 19 02:05:51 PM PDT 24
Peak memory 255700 kb
Host smart-cd033602-8913-4b4d-a571-d6b8475e8411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14521
77625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1452177625
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.56119659
Short name T583
Test name
Test status
Simulation time 237960429 ps
CPU time 21.95 seconds
Started Mar 19 02:05:02 PM PDT 24
Finished Mar 19 02:05:25 PM PDT 24
Peak memory 247420 kb
Host smart-1e3cf953-8e4b-43e3-bab4-27949f0b9dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56119
659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.56119659
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2865932483
Short name T89
Test name
Test status
Simulation time 107950134 ps
CPU time 11.47 seconds
Started Mar 19 02:05:02 PM PDT 24
Finished Mar 19 02:05:15 PM PDT 24
Peak memory 254948 kb
Host smart-e110d44f-1bd7-4193-82d4-fb1d72a04434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28659
32483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2865932483
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.533586305
Short name T357
Test name
Test status
Simulation time 452277088 ps
CPU time 22.18 seconds
Started Mar 19 02:04:51 PM PDT 24
Finished Mar 19 02:05:13 PM PDT 24
Peak memory 256484 kb
Host smart-bcafa60a-4dcb-47bb-a1eb-3448df686c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53358
6305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.533586305
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2688137199
Short name T93
Test name
Test status
Simulation time 15602116571 ps
CPU time 317.04 seconds
Started Mar 19 02:05:12 PM PDT 24
Finished Mar 19 02:10:29 PM PDT 24
Peak memory 265328 kb
Host smart-78cd1ef1-3fd9-4917-99f3-c4f0617136bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688137199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2688137199
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.996702220
Short name T674
Test name
Test status
Simulation time 42476554507 ps
CPU time 4306.85 seconds
Started Mar 19 02:05:12 PM PDT 24
Finished Mar 19 03:17:00 PM PDT 24
Peak memory 338636 kb
Host smart-941ce3ba-860c-4505-8072-c748d3040d92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996702220 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.996702220
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3641309695
Short name T475
Test name
Test status
Simulation time 2019653169 ps
CPU time 97.38 seconds
Started Mar 19 02:05:14 PM PDT 24
Finished Mar 19 02:06:51 PM PDT 24
Peak memory 248804 kb
Host smart-7bd486de-c0ec-4a1a-91ba-fb3be2b2f3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36413
09695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3641309695
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3237975096
Short name T373
Test name
Test status
Simulation time 1715908900 ps
CPU time 25.77 seconds
Started Mar 19 02:05:14 PM PDT 24
Finished Mar 19 02:05:40 PM PDT 24
Peak memory 255576 kb
Host smart-81138b0d-a850-4f59-847d-0e1c274fc7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32379
75096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3237975096
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1593958640
Short name T330
Test name
Test status
Simulation time 20435742297 ps
CPU time 1261.32 seconds
Started Mar 19 02:05:21 PM PDT 24
Finished Mar 19 02:26:22 PM PDT 24
Peak memory 265316 kb
Host smart-3b3691ac-e7fe-4fb2-92db-a7713c4a35a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593958640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1593958640
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.714004807
Short name T223
Test name
Test status
Simulation time 9360367333 ps
CPU time 1419.44 seconds
Started Mar 19 02:05:22 PM PDT 24
Finished Mar 19 02:29:01 PM PDT 24
Peak memory 289312 kb
Host smart-0ac710e8-eb42-4db5-9761-dea374f4cc5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714004807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.714004807
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1072564062
Short name T538
Test name
Test status
Simulation time 10551168904 ps
CPU time 427.13 seconds
Started Mar 19 02:05:22 PM PDT 24
Finished Mar 19 02:12:29 PM PDT 24
Peak memory 256352 kb
Host smart-0d52d8b8-47fd-4d1c-8a3f-ee88476a632c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072564062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1072564062
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3432158249
Short name T408
Test name
Test status
Simulation time 341511333 ps
CPU time 7.4 seconds
Started Mar 19 02:05:12 PM PDT 24
Finished Mar 19 02:05:20 PM PDT 24
Peak memory 248800 kb
Host smart-48179416-d5e3-49d8-9f4f-0db4db6edb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321
58249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3432158249
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1077021049
Short name T109
Test name
Test status
Simulation time 63760702 ps
CPU time 8.47 seconds
Started Mar 19 02:05:13 PM PDT 24
Finished Mar 19 02:05:21 PM PDT 24
Peak memory 240620 kb
Host smart-f51e2917-197d-4157-b0ab-1de3e5728ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10770
21049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1077021049
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3334004441
Short name T438
Test name
Test status
Simulation time 1040972561 ps
CPU time 22.99 seconds
Started Mar 19 02:05:14 PM PDT 24
Finished Mar 19 02:05:37 PM PDT 24
Peak memory 248876 kb
Host smart-2305e3d3-751a-4670-84eb-dc00385346b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
04441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3334004441
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2798018982
Short name T677
Test name
Test status
Simulation time 115061193 ps
CPU time 6.34 seconds
Started Mar 19 02:05:12 PM PDT 24
Finished Mar 19 02:05:18 PM PDT 24
Peak memory 250920 kb
Host smart-48e8754a-e013-4163-8819-ed4e4eee07f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27980
18982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2798018982
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1835445234
Short name T226
Test name
Test status
Simulation time 48751993950 ps
CPU time 2728.52 seconds
Started Mar 19 02:05:30 PM PDT 24
Finished Mar 19 02:51:00 PM PDT 24
Peak memory 289192 kb
Host smart-6ca74db7-c5ae-475b-adfd-90cfc6c023a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835445234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1835445234
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1740443696
Short name T562
Test name
Test status
Simulation time 83273326004 ps
CPU time 2852.7 seconds
Started Mar 19 02:05:34 PM PDT 24
Finished Mar 19 02:53:07 PM PDT 24
Peak memory 289284 kb
Host smart-717a4373-5749-4995-b149-2122f5947d95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740443696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1740443696
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1278371902
Short name T508
Test name
Test status
Simulation time 3175591473 ps
CPU time 83.45 seconds
Started Mar 19 02:05:31 PM PDT 24
Finished Mar 19 02:06:55 PM PDT 24
Peak memory 257104 kb
Host smart-2e447056-1b4c-4a8d-b274-d7ba89bd93d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783
71902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1278371902
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1735969496
Short name T641
Test name
Test status
Simulation time 6206269399 ps
CPU time 66.09 seconds
Started Mar 19 02:05:33 PM PDT 24
Finished Mar 19 02:06:39 PM PDT 24
Peak memory 256392 kb
Host smart-a61dc0f1-3a0c-4686-b268-c37a67c7eeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17359
69496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1735969496
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.719504004
Short name T315
Test name
Test status
Simulation time 81272506945 ps
CPU time 1497.02 seconds
Started Mar 19 02:05:33 PM PDT 24
Finished Mar 19 02:30:30 PM PDT 24
Peak memory 267368 kb
Host smart-7d2efe81-b6ce-4b06-a1ca-c4666e6987b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719504004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.719504004
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2185383912
Short name T665
Test name
Test status
Simulation time 100283821009 ps
CPU time 3036.35 seconds
Started Mar 19 02:05:32 PM PDT 24
Finished Mar 19 02:56:08 PM PDT 24
Peak memory 289444 kb
Host smart-cdf0ba11-265e-4ebc-bdad-2ec06bb74fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185383912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2185383912
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1554985035
Short name T307
Test name
Test status
Simulation time 85938953190 ps
CPU time 250.29 seconds
Started Mar 19 02:05:33 PM PDT 24
Finished Mar 19 02:09:43 PM PDT 24
Peak memory 247120 kb
Host smart-1af3e8b6-2a51-492c-bb39-41c286e2992b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554985035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1554985035
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1292773003
Short name T556
Test name
Test status
Simulation time 167724955 ps
CPU time 19.29 seconds
Started Mar 19 02:05:22 PM PDT 24
Finished Mar 19 02:05:41 PM PDT 24
Peak memory 248836 kb
Host smart-7c189480-f39a-46f0-8654-12b1fd379d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12927
73003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1292773003
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.377021207
Short name T278
Test name
Test status
Simulation time 1898997921 ps
CPU time 34.61 seconds
Started Mar 19 02:05:21 PM PDT 24
Finished Mar 19 02:05:56 PM PDT 24
Peak memory 254704 kb
Host smart-6560cb71-c981-406a-8cdb-123311ab9e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37702
1207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.377021207
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1156681904
Short name T419
Test name
Test status
Simulation time 257626808 ps
CPU time 26.16 seconds
Started Mar 19 02:05:32 PM PDT 24
Finished Mar 19 02:05:58 PM PDT 24
Peak memory 247540 kb
Host smart-1193d1b5-2103-49cb-9040-9679eda6ef62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11566
81904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1156681904
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.934292998
Short name T384
Test name
Test status
Simulation time 181205542 ps
CPU time 7.61 seconds
Started Mar 19 02:05:22 PM PDT 24
Finished Mar 19 02:05:29 PM PDT 24
Peak memory 248816 kb
Host smart-8378120f-5257-40df-b3d6-ddf5f12794ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93429
2998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.934292998
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3855824503
Short name T368
Test name
Test status
Simulation time 8751160127 ps
CPU time 567.58 seconds
Started Mar 19 02:05:32 PM PDT 24
Finished Mar 19 02:14:59 PM PDT 24
Peak memory 257104 kb
Host smart-5a01163f-6df8-4565-9f8a-37db4efb1390
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855824503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3855824503
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2280543145
Short name T449
Test name
Test status
Simulation time 11004773365 ps
CPU time 1021.27 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:22:44 PM PDT 24
Peak memory 271804 kb
Host smart-186ab304-ac09-4480-a782-aea6770f92af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280543145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2280543145
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3896762969
Short name T424
Test name
Test status
Simulation time 977546227 ps
CPU time 76.31 seconds
Started Mar 19 02:05:41 PM PDT 24
Finished Mar 19 02:06:57 PM PDT 24
Peak memory 256468 kb
Host smart-9138e538-4a92-447c-8200-874bf3155461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38967
62969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3896762969
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1580635002
Short name T492
Test name
Test status
Simulation time 1002428875 ps
CPU time 54.49 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:06:37 PM PDT 24
Peak memory 248876 kb
Host smart-4c80cec6-c466-4c24-97f5-7221ae92eca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806
35002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1580635002
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.777742705
Short name T331
Test name
Test status
Simulation time 112293038046 ps
CPU time 1702.72 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:34:05 PM PDT 24
Peak memory 267380 kb
Host smart-1c2f6a90-6559-404c-8483-503ab51752f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777742705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.777742705
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3706876993
Short name T225
Test name
Test status
Simulation time 12546994085 ps
CPU time 1030.4 seconds
Started Mar 19 02:05:54 PM PDT 24
Finished Mar 19 02:23:04 PM PDT 24
Peak memory 269588 kb
Host smart-5c3a5b59-de3e-46ef-81fe-b12848c0903b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706876993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3706876993
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.593236109
Short name T309
Test name
Test status
Simulation time 28676959962 ps
CPU time 325.4 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:11:07 PM PDT 24
Peak memory 254648 kb
Host smart-608714c4-f76d-4f0b-a3ee-d7b3c67a8c6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593236109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.593236109
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1027022484
Short name T455
Test name
Test status
Simulation time 2445947368 ps
CPU time 44.34 seconds
Started Mar 19 02:05:49 PM PDT 24
Finished Mar 19 02:06:34 PM PDT 24
Peak memory 257060 kb
Host smart-02870b4c-dda8-488c-859b-d059329f56fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
22484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1027022484
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2077736651
Short name T587
Test name
Test status
Simulation time 2001358489 ps
CPU time 66.83 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:06:49 PM PDT 24
Peak memory 255936 kb
Host smart-61bca837-a2a4-4fee-bae5-12cfa098bb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20777
36651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2077736651
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2800403537
Short name T397
Test name
Test status
Simulation time 152874327 ps
CPU time 16.44 seconds
Started Mar 19 02:05:42 PM PDT 24
Finished Mar 19 02:05:58 PM PDT 24
Peak memory 247396 kb
Host smart-292d72db-7357-4b8b-a9e6-763ec2b030ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28004
03537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2800403537
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1137372994
Short name T516
Test name
Test status
Simulation time 560585404 ps
CPU time 39.29 seconds
Started Mar 19 02:05:41 PM PDT 24
Finished Mar 19 02:06:21 PM PDT 24
Peak memory 255524 kb
Host smart-b4b5286b-8cad-43b5-9d58-5f1d000ed059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
72994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1137372994
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2548044938
Short name T257
Test name
Test status
Simulation time 14211326480 ps
CPU time 1213 seconds
Started Mar 19 02:05:55 PM PDT 24
Finished Mar 19 02:26:09 PM PDT 24
Peak memory 288400 kb
Host smart-cd606a7a-e3c4-473d-a6bb-1fb1507caf3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548044938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2548044938
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1464628456
Short name T624
Test name
Test status
Simulation time 180858002991 ps
CPU time 2350.53 seconds
Started Mar 19 02:05:53 PM PDT 24
Finished Mar 19 02:45:05 PM PDT 24
Peak memory 281708 kb
Host smart-de9aee58-5a43-4109-9171-167c74281229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464628456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1464628456
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3418788116
Short name T200
Test name
Test status
Simulation time 443297886 ps
CPU time 14.59 seconds
Started Mar 19 02:05:53 PM PDT 24
Finished Mar 19 02:06:08 PM PDT 24
Peak memory 252940 kb
Host smart-56df3614-6d3f-4341-ad9b-52ecc2c2baff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
88116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3418788116
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.314177134
Short name T604
Test name
Test status
Simulation time 1524509174 ps
CPU time 31.2 seconds
Started Mar 19 02:05:55 PM PDT 24
Finished Mar 19 02:06:27 PM PDT 24
Peak memory 248888 kb
Host smart-b085fb7b-5faa-4568-a89a-b67d31d56e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417
7134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.314177134
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1341856479
Short name T320
Test name
Test status
Simulation time 26514553382 ps
CPU time 1349.73 seconds
Started Mar 19 02:06:08 PM PDT 24
Finished Mar 19 02:28:39 PM PDT 24
Peak memory 271412 kb
Host smart-27fbf604-524b-4980-b8ae-ca3c0b7b1dfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341856479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1341856479
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3991148402
Short name T630
Test name
Test status
Simulation time 18569280866 ps
CPU time 1391.41 seconds
Started Mar 19 02:06:09 PM PDT 24
Finished Mar 19 02:29:21 PM PDT 24
Peak memory 273364 kb
Host smart-0f1d307a-5fdb-4ed5-a689-0d4674c3b34a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991148402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3991148402
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2054742812
Short name T310
Test name
Test status
Simulation time 5485492459 ps
CPU time 249.1 seconds
Started Mar 19 02:05:56 PM PDT 24
Finished Mar 19 02:10:06 PM PDT 24
Peak memory 247148 kb
Host smart-594cc4df-d671-49e0-bf71-05a93e859bd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054742812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2054742812
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.903200941
Short name T277
Test name
Test status
Simulation time 2854253939 ps
CPU time 50.37 seconds
Started Mar 19 02:05:53 PM PDT 24
Finished Mar 19 02:06:44 PM PDT 24
Peak memory 248840 kb
Host smart-c8328256-d649-4c46-b891-4b66be10a535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90320
0941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.903200941
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3594312945
Short name T1
Test name
Test status
Simulation time 156257144 ps
CPU time 6.86 seconds
Started Mar 19 02:05:55 PM PDT 24
Finished Mar 19 02:06:01 PM PDT 24
Peak memory 252976 kb
Host smart-8986f502-0013-4003-93e2-569a54387cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35943
12945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3594312945
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1903779455
Short name T470
Test name
Test status
Simulation time 514869372 ps
CPU time 9.08 seconds
Started Mar 19 02:05:55 PM PDT 24
Finished Mar 19 02:06:04 PM PDT 24
Peak memory 248884 kb
Host smart-c3e65718-63e1-451d-828f-85ffaedf7ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
79455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1903779455
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1787728491
Short name T616
Test name
Test status
Simulation time 501817389 ps
CPU time 12.3 seconds
Started Mar 19 02:05:56 PM PDT 24
Finished Mar 19 02:06:08 PM PDT 24
Peak memory 248948 kb
Host smart-cbfde9c8-d5d4-4428-82f6-e95e718f054a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17877
28491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1787728491
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3282037652
Short name T59
Test name
Test status
Simulation time 4619881352 ps
CPU time 560.01 seconds
Started Mar 19 02:06:20 PM PDT 24
Finished Mar 19 02:15:40 PM PDT 24
Peak memory 272876 kb
Host smart-8c24d9ed-96f3-4f6d-afb8-539da88ae55f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282037652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3282037652
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1595681410
Short name T378
Test name
Test status
Simulation time 4646873006 ps
CPU time 286.97 seconds
Started Mar 19 02:06:21 PM PDT 24
Finished Mar 19 02:11:08 PM PDT 24
Peak memory 257072 kb
Host smart-59a86d32-7c39-4e5d-b2b1-62fc60bed79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15956
81410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1595681410
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.4237222711
Short name T456
Test name
Test status
Simulation time 1345368589 ps
CPU time 33.34 seconds
Started Mar 19 02:06:11 PM PDT 24
Finished Mar 19 02:06:44 PM PDT 24
Peak memory 255600 kb
Host smart-6326dfad-2627-4fb8-8e65-e3a3ac56ce48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
22711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4237222711
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.328595649
Short name T524
Test name
Test status
Simulation time 231817222489 ps
CPU time 3543.72 seconds
Started Mar 19 02:06:23 PM PDT 24
Finished Mar 19 03:05:27 PM PDT 24
Peak memory 288796 kb
Host smart-f77ab4e1-e118-4868-b00b-e30078b9bd64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328595649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.328595649
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.4065268371
Short name T435
Test name
Test status
Simulation time 54286642640 ps
CPU time 2022.79 seconds
Started Mar 19 02:06:19 PM PDT 24
Finished Mar 19 02:40:02 PM PDT 24
Peak memory 288780 kb
Host smart-656c0bb7-2fc6-4618-94f3-2e277c1ce0b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065268371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4065268371
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.299026627
Short name T374
Test name
Test status
Simulation time 407307092 ps
CPU time 35.29 seconds
Started Mar 19 02:06:09 PM PDT 24
Finished Mar 19 02:06:45 PM PDT 24
Peak memory 255736 kb
Host smart-2286f9e6-142d-4554-af21-ed3426327ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
6627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.299026627
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1585774070
Short name T480
Test name
Test status
Simulation time 3782447152 ps
CPU time 58.4 seconds
Started Mar 19 02:06:08 PM PDT 24
Finished Mar 19 02:07:06 PM PDT 24
Peak memory 248612 kb
Host smart-e3bb3400-dbb7-4a57-b5e4-d2083db2d57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
74070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1585774070
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2907951508
Short name T273
Test name
Test status
Simulation time 56398509 ps
CPU time 8.44 seconds
Started Mar 19 02:06:20 PM PDT 24
Finished Mar 19 02:06:29 PM PDT 24
Peak memory 247336 kb
Host smart-5dc8a9ce-c792-4af6-b32c-d0dc3cf5d6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079
51508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2907951508
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.176377546
Short name T74
Test name
Test status
Simulation time 415189475 ps
CPU time 31.95 seconds
Started Mar 19 02:06:10 PM PDT 24
Finished Mar 19 02:06:42 PM PDT 24
Peak memory 255548 kb
Host smart-283cbc8b-4d56-4505-9bd8-063c26ffed10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
7546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.176377546
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3278750579
Short name T199
Test name
Test status
Simulation time 1528142525 ps
CPU time 41.28 seconds
Started Mar 19 02:06:19 PM PDT 24
Finished Mar 19 02:07:01 PM PDT 24
Peak memory 256184 kb
Host smart-59c7b5bb-acd9-48ce-90c9-2a2f098997e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278750579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3278750579
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2606057595
Short name T405
Test name
Test status
Simulation time 95282693190 ps
CPU time 1516.35 seconds
Started Mar 19 02:06:33 PM PDT 24
Finished Mar 19 02:31:50 PM PDT 24
Peak memory 265420 kb
Host smart-39390093-a765-43cf-ba79-927692706b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606057595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2606057595
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1652328989
Short name T202
Test name
Test status
Simulation time 8278295654 ps
CPU time 231.91 seconds
Started Mar 19 02:06:19 PM PDT 24
Finished Mar 19 02:10:11 PM PDT 24
Peak memory 257108 kb
Host smart-c7e90c98-221b-4341-b266-7455ffab2726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16523
28989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1652328989
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4089771927
Short name T284
Test name
Test status
Simulation time 8751011505 ps
CPU time 60.6 seconds
Started Mar 19 02:06:22 PM PDT 24
Finished Mar 19 02:07:23 PM PDT 24
Peak memory 249240 kb
Host smart-de5983c5-1bbf-4d2e-9999-dea2b9a1660e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40897
71927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4089771927
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1309169609
Short name T322
Test name
Test status
Simulation time 131833120720 ps
CPU time 1880.35 seconds
Started Mar 19 02:06:33 PM PDT 24
Finished Mar 19 02:37:54 PM PDT 24
Peak memory 271984 kb
Host smart-d7e9235e-b29d-4259-b8f8-ee7041b05875
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309169609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1309169609
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1320384981
Short name T671
Test name
Test status
Simulation time 131533560576 ps
CPU time 2809.08 seconds
Started Mar 19 02:06:32 PM PDT 24
Finished Mar 19 02:53:21 PM PDT 24
Peak memory 281580 kb
Host smart-cb1785e1-fa4a-415c-a907-8ea3eca30495
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320384981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1320384981
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2971797250
Short name T607
Test name
Test status
Simulation time 4894667198 ps
CPU time 156.41 seconds
Started Mar 19 02:06:33 PM PDT 24
Finished Mar 19 02:09:10 PM PDT 24
Peak memory 246984 kb
Host smart-e649250d-9d05-40b8-b1fd-846eb26a36bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971797250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2971797250
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2989671010
Short name T716
Test name
Test status
Simulation time 4447867205 ps
CPU time 57.64 seconds
Started Mar 19 02:06:20 PM PDT 24
Finished Mar 19 02:07:18 PM PDT 24
Peak memory 256028 kb
Host smart-454e8e32-518e-4702-b6e9-544bd6385319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29896
71010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2989671010
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.693904386
Short name T600
Test name
Test status
Simulation time 208304984 ps
CPU time 4.87 seconds
Started Mar 19 02:06:20 PM PDT 24
Finished Mar 19 02:06:25 PM PDT 24
Peak memory 240636 kb
Host smart-c909cea4-cc66-4fff-b0eb-90ce58c1b29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69390
4386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.693904386
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2410106674
Short name T111
Test name
Test status
Simulation time 837537245 ps
CPU time 38.6 seconds
Started Mar 19 02:06:34 PM PDT 24
Finished Mar 19 02:07:13 PM PDT 24
Peak memory 247292 kb
Host smart-229737b1-0c60-49ed-bbac-7589751e9f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24101
06674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2410106674
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.837083098
Short name T354
Test name
Test status
Simulation time 1004279961 ps
CPU time 5.7 seconds
Started Mar 19 02:06:21 PM PDT 24
Finished Mar 19 02:06:28 PM PDT 24
Peak memory 240680 kb
Host smart-12d53dee-fe69-4f4e-8c89-eb8b17c53418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83708
3098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.837083098
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1258454193
Short name T100
Test name
Test status
Simulation time 43717091 ps
CPU time 2.63 seconds
Started Mar 19 02:02:07 PM PDT 24
Finished Mar 19 02:02:10 PM PDT 24
Peak memory 257264 kb
Host smart-5df941fb-3998-4b39-b629-18b3526fa630
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1258454193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1258454193
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3357130062
Short name T32
Test name
Test status
Simulation time 15755099141 ps
CPU time 1416.29 seconds
Started Mar 19 02:02:21 PM PDT 24
Finished Mar 19 02:25:57 PM PDT 24
Peak memory 288728 kb
Host smart-1d02e7fa-52a8-4cac-b136-1a25b455b7c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357130062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3357130062
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2299824190
Short name T505
Test name
Test status
Simulation time 2884617783 ps
CPU time 18.65 seconds
Started Mar 19 02:02:45 PM PDT 24
Finished Mar 19 02:03:03 PM PDT 24
Peak memory 240668 kb
Host smart-a478a601-038a-467a-9b17-1b1a487c2503
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2299824190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2299824190
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2401283816
Short name T48
Test name
Test status
Simulation time 287191910 ps
CPU time 30 seconds
Started Mar 19 02:02:40 PM PDT 24
Finished Mar 19 02:03:11 PM PDT 24
Peak memory 255888 kb
Host smart-74b6d615-d81a-4d64-a64f-47ad40c56f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24012
83816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2401283816
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3505272468
Short name T427
Test name
Test status
Simulation time 1005032188 ps
CPU time 15.95 seconds
Started Mar 19 02:02:07 PM PDT 24
Finished Mar 19 02:02:23 PM PDT 24
Peak memory 249100 kb
Host smart-1b2f0f1d-0239-4438-b1d9-12d9bf942987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35052
72468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3505272468
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3292402011
Short name T326
Test name
Test status
Simulation time 113041592420 ps
CPU time 2178.6 seconds
Started Mar 19 02:02:09 PM PDT 24
Finished Mar 19 02:38:28 PM PDT 24
Peak memory 273488 kb
Host smart-10e3ac74-1c07-441c-bbd7-fd4f08884977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292402011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3292402011
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1358938556
Short name T391
Test name
Test status
Simulation time 204802980241 ps
CPU time 2752.49 seconds
Started Mar 19 02:01:48 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 289396 kb
Host smart-1acfa7ba-6c4a-4507-a09b-84979b6bfa66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358938556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1358938556
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.4012776572
Short name T712
Test name
Test status
Simulation time 26638401823 ps
CPU time 268.12 seconds
Started Mar 19 02:02:20 PM PDT 24
Finished Mar 19 02:06:48 PM PDT 24
Peak memory 248828 kb
Host smart-e8a753be-a9c4-4828-93ec-8f6cdca318a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012776572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.4012776572
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2309147438
Short name T383
Test name
Test status
Simulation time 576348220 ps
CPU time 32.52 seconds
Started Mar 19 02:02:40 PM PDT 24
Finished Mar 19 02:03:14 PM PDT 24
Peak memory 248856 kb
Host smart-5ee25506-5711-4295-861c-545742ac1744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23091
47438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2309147438
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.708909281
Short name T10
Test name
Test status
Simulation time 1548157682 ps
CPU time 14.94 seconds
Started Mar 19 02:02:41 PM PDT 24
Finished Mar 19 02:02:56 PM PDT 24
Peak memory 265328 kb
Host smart-f2847875-9b9b-4819-ad4e-c4ed788a6e1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=708909281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.708909281
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2301677361
Short name T270
Test name
Test status
Simulation time 1099962289 ps
CPU time 19.81 seconds
Started Mar 19 02:02:41 PM PDT 24
Finished Mar 19 02:03:01 PM PDT 24
Peak memory 248852 kb
Host smart-f615069f-ed55-4192-9e09-6312a5cdb94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23016
77361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2301677361
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1141046589
Short name T413
Test name
Test status
Simulation time 354600667 ps
CPU time 12.08 seconds
Started Mar 19 02:02:40 PM PDT 24
Finished Mar 19 02:02:53 PM PDT 24
Peak memory 248848 kb
Host smart-4faf82ee-1cfd-4544-8309-f04809573764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11410
46589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1141046589
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.983742885
Short name T603
Test name
Test status
Simulation time 45778454879 ps
CPU time 1368.39 seconds
Started Mar 19 02:02:06 PM PDT 24
Finished Mar 19 02:24:55 PM PDT 24
Peak memory 289196 kb
Host smart-17d621fc-843e-4705-a9a5-ca7a8c2f825b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983742885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.983742885
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.423010886
Short name T66
Test name
Test status
Simulation time 24952130920 ps
CPU time 1593.05 seconds
Started Mar 19 02:02:20 PM PDT 24
Finished Mar 19 02:28:53 PM PDT 24
Peak memory 289560 kb
Host smart-8264a90b-ade7-430f-a96d-5c642c38fa3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423010886 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.423010886
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3448430534
Short name T592
Test name
Test status
Simulation time 143575386527 ps
CPU time 2672.78 seconds
Started Mar 19 02:06:43 PM PDT 24
Finished Mar 19 02:51:16 PM PDT 24
Peak memory 289528 kb
Host smart-83bfd959-c240-4b17-b541-c7c148870445
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448430534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3448430534
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.587629446
Short name T510
Test name
Test status
Simulation time 7353627575 ps
CPU time 230.32 seconds
Started Mar 19 02:06:44 PM PDT 24
Finished Mar 19 02:10:34 PM PDT 24
Peak memory 256780 kb
Host smart-47ed1813-b150-4918-82b2-694c72ec680f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58762
9446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.587629446
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.4250113473
Short name T663
Test name
Test status
Simulation time 373557382 ps
CPU time 28.27 seconds
Started Mar 19 02:06:46 PM PDT 24
Finished Mar 19 02:07:15 PM PDT 24
Peak memory 254716 kb
Host smart-dc639cbd-fcec-4263-bdfa-04fbd89c917d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
13473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4250113473
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.319316381
Short name T646
Test name
Test status
Simulation time 171149631464 ps
CPU time 2559.97 seconds
Started Mar 19 02:06:46 PM PDT 24
Finished Mar 19 02:49:26 PM PDT 24
Peak memory 272892 kb
Host smart-0bd0c169-6f0a-4dec-b02a-e67c64c98a12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319316381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.319316381
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2279914243
Short name T390
Test name
Test status
Simulation time 54658295226 ps
CPU time 3298.15 seconds
Started Mar 19 02:06:43 PM PDT 24
Finished Mar 19 03:01:42 PM PDT 24
Peak memory 281696 kb
Host smart-2721412a-7747-4ea1-bf18-8bf372765195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279914243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2279914243
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2214453365
Short name T561
Test name
Test status
Simulation time 53021960 ps
CPU time 4.8 seconds
Started Mar 19 02:06:34 PM PDT 24
Finished Mar 19 02:06:39 PM PDT 24
Peak memory 240608 kb
Host smart-39fc8b6a-3cae-43cf-9296-502169e7db1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22144
53365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2214453365
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3153390620
Short name T550
Test name
Test status
Simulation time 146172478 ps
CPU time 9.16 seconds
Started Mar 19 02:06:46 PM PDT 24
Finished Mar 19 02:06:55 PM PDT 24
Peak memory 247420 kb
Host smart-acceeddd-dcf3-4bf3-96f2-c4acc7490879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31533
90620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3153390620
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.323002759
Short name T605
Test name
Test status
Simulation time 222861952 ps
CPU time 15.22 seconds
Started Mar 19 02:06:46 PM PDT 24
Finished Mar 19 02:07:01 PM PDT 24
Peak memory 248872 kb
Host smart-b3f40ddc-ac0e-4ac4-8bce-5fc012517631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
2759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.323002759
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.209416406
Short name T661
Test name
Test status
Simulation time 1778202919 ps
CPU time 34.96 seconds
Started Mar 19 02:06:34 PM PDT 24
Finished Mar 19 02:07:09 PM PDT 24
Peak memory 256224 kb
Host smart-e14d125e-9b21-4a1d-8fff-959998701d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20941
6406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.209416406
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2348630755
Short name T669
Test name
Test status
Simulation time 62915296229 ps
CPU time 3089.28 seconds
Started Mar 19 02:06:42 PM PDT 24
Finished Mar 19 02:58:12 PM PDT 24
Peak memory 298832 kb
Host smart-002dc9a3-f977-4598-8dc4-3012ce6212a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348630755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2348630755
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2340990931
Short name T412
Test name
Test status
Simulation time 21335897779 ps
CPU time 799.02 seconds
Started Mar 19 02:06:53 PM PDT 24
Finished Mar 19 02:20:14 PM PDT 24
Peak memory 265336 kb
Host smart-1f11439b-3411-42de-a1e9-423bb16a9ee3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340990931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2340990931
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1887987359
Short name T450
Test name
Test status
Simulation time 2091301603 ps
CPU time 118.3 seconds
Started Mar 19 02:06:54 PM PDT 24
Finished Mar 19 02:08:53 PM PDT 24
Peak memory 256852 kb
Host smart-5910e96d-5d24-4684-8764-b47c5deacc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18879
87359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1887987359
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1540122072
Short name T388
Test name
Test status
Simulation time 5078609650 ps
CPU time 54.37 seconds
Started Mar 19 02:07:00 PM PDT 24
Finished Mar 19 02:07:55 PM PDT 24
Peak memory 255672 kb
Host smart-f8b3cc10-ab54-4f53-8164-8a0bf8e46daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15401
22072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1540122072
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3979422852
Short name T574
Test name
Test status
Simulation time 11261948122 ps
CPU time 997.17 seconds
Started Mar 19 02:07:01 PM PDT 24
Finished Mar 19 02:23:40 PM PDT 24
Peak memory 268400 kb
Host smart-64bf22d0-fe33-4499-9138-e62929ce9bcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979422852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3979422852
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3601265591
Short name T571
Test name
Test status
Simulation time 181214688345 ps
CPU time 1529.19 seconds
Started Mar 19 02:07:05 PM PDT 24
Finished Mar 19 02:32:35 PM PDT 24
Peak memory 288960 kb
Host smart-e7787432-5c9d-46c5-82bc-a9c33aab3d4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601265591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3601265591
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1041598021
Short name T295
Test name
Test status
Simulation time 9159369383 ps
CPU time 186.04 seconds
Started Mar 19 02:07:01 PM PDT 24
Finished Mar 19 02:10:08 PM PDT 24
Peak memory 247704 kb
Host smart-d4937a6f-b20f-4b56-ba5b-d3f53e23696f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041598021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1041598021
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.916382692
Short name T715
Test name
Test status
Simulation time 55465054 ps
CPU time 6.88 seconds
Started Mar 19 02:06:44 PM PDT 24
Finished Mar 19 02:06:51 PM PDT 24
Peak memory 248840 kb
Host smart-ed30cb71-c632-4746-a548-da47bde4eaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91638
2692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.916382692
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4276700971
Short name T78
Test name
Test status
Simulation time 908145642 ps
CPU time 53.67 seconds
Started Mar 19 02:06:45 PM PDT 24
Finished Mar 19 02:07:38 PM PDT 24
Peak memory 254868 kb
Host smart-217bc9ff-2ad6-470b-875d-d31e167b414c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42767
00971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4276700971
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2724839933
Short name T291
Test name
Test status
Simulation time 214299669 ps
CPU time 23.43 seconds
Started Mar 19 02:06:53 PM PDT 24
Finished Mar 19 02:07:18 PM PDT 24
Peak memory 248904 kb
Host smart-68e7020b-a0ac-4af2-8d16-50796a99c8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27248
39933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2724839933
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1956723028
Short name T91
Test name
Test status
Simulation time 1977544855 ps
CPU time 70.95 seconds
Started Mar 19 02:06:43 PM PDT 24
Finished Mar 19 02:07:54 PM PDT 24
Peak memory 256032 kb
Host smart-87f5e873-7728-4bca-b683-4aa6aa98f626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567
23028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1956723028
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2455917013
Short name T534
Test name
Test status
Simulation time 10996798635 ps
CPU time 1342.31 seconds
Started Mar 19 02:07:19 PM PDT 24
Finished Mar 19 02:29:42 PM PDT 24
Peak memory 281648 kb
Host smart-9d8d0169-9cbd-4e82-a2e7-61acbf44852c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455917013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2455917013
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2344024748
Short name T452
Test name
Test status
Simulation time 3702915243 ps
CPU time 229.65 seconds
Started Mar 19 02:07:17 PM PDT 24
Finished Mar 19 02:11:07 PM PDT 24
Peak memory 257080 kb
Host smart-debc4103-7913-45a9-89a8-f0e2b02c8d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23440
24748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2344024748
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4160135379
Short name T404
Test name
Test status
Simulation time 907527235 ps
CPU time 28.2 seconds
Started Mar 19 02:07:17 PM PDT 24
Finished Mar 19 02:07:45 PM PDT 24
Peak memory 255872 kb
Host smart-f66d6f93-e4b6-40f8-884e-378ed29606c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41601
35379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4160135379
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.849338005
Short name T290
Test name
Test status
Simulation time 143948544733 ps
CPU time 2153.96 seconds
Started Mar 19 02:07:18 PM PDT 24
Finished Mar 19 02:43:13 PM PDT 24
Peak memory 288944 kb
Host smart-a3447140-b7b3-4350-ad5e-a7bcc7c1c0e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849338005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.849338005
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.395864956
Short name T625
Test name
Test status
Simulation time 59209575500 ps
CPU time 2092.74 seconds
Started Mar 19 02:07:25 PM PDT 24
Finished Mar 19 02:42:18 PM PDT 24
Peak memory 288820 kb
Host smart-49cf882a-1170-4d24-8c18-7ffbcbb63d31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395864956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.395864956
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1172236694
Short name T709
Test name
Test status
Simulation time 3510552943 ps
CPU time 146.9 seconds
Started Mar 19 02:07:16 PM PDT 24
Finished Mar 19 02:09:44 PM PDT 24
Peak memory 248112 kb
Host smart-22c05e1e-e1fa-4d46-8cda-0924124111ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172236694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1172236694
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2584601522
Short name T364
Test name
Test status
Simulation time 184685077 ps
CPU time 22.76 seconds
Started Mar 19 02:07:05 PM PDT 24
Finished Mar 19 02:07:28 PM PDT 24
Peak memory 248888 kb
Host smart-23eab4ba-bf08-4391-bad6-132340229f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25846
01522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2584601522
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3755696485
Short name T644
Test name
Test status
Simulation time 161568669 ps
CPU time 9.87 seconds
Started Mar 19 02:07:12 PM PDT 24
Finished Mar 19 02:07:23 PM PDT 24
Peak memory 250936 kb
Host smart-a11d9480-b46c-43bf-9e71-cb0198c858b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
96485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3755696485
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2982960925
Short name T358
Test name
Test status
Simulation time 166410417 ps
CPU time 7.63 seconds
Started Mar 19 02:07:18 PM PDT 24
Finished Mar 19 02:07:27 PM PDT 24
Peak memory 250936 kb
Host smart-1d155887-6807-4ce8-b0c6-f969802146e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29829
60925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2982960925
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2470267746
Short name T82
Test name
Test status
Simulation time 435024449 ps
CPU time 28.13 seconds
Started Mar 19 02:07:05 PM PDT 24
Finished Mar 19 02:07:34 PM PDT 24
Peak memory 248832 kb
Host smart-ea5d7e4c-9ee6-4acb-af25-7a15825a27d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24702
67746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2470267746
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3512212615
Short name T256
Test name
Test status
Simulation time 258937882288 ps
CPU time 3811.9 seconds
Started Mar 19 02:07:25 PM PDT 24
Finished Mar 19 03:10:58 PM PDT 24
Peak memory 299672 kb
Host smart-dcc49388-a5c1-4a82-b18d-0dc39be85939
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512212615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3512212615
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2714514559
Short name T60
Test name
Test status
Simulation time 34439047922 ps
CPU time 1260.63 seconds
Started Mar 19 02:07:25 PM PDT 24
Finished Mar 19 02:28:26 PM PDT 24
Peak memory 272856 kb
Host smart-1b38f120-a6d7-4b57-892a-f3f0c1d0cabd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714514559 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2714514559
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2637819535
Short name T454
Test name
Test status
Simulation time 6925342782 ps
CPU time 781.76 seconds
Started Mar 19 02:07:26 PM PDT 24
Finished Mar 19 02:20:28 PM PDT 24
Peak memory 273380 kb
Host smart-e564d824-ee57-4d6d-b1d3-4e8e9333d361
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637819535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2637819535
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.338139685
Short name T560
Test name
Test status
Simulation time 20212310060 ps
CPU time 232.83 seconds
Started Mar 19 02:07:25 PM PDT 24
Finished Mar 19 02:11:18 PM PDT 24
Peak memory 256804 kb
Host smart-bd23ef06-ea80-4d89-90ba-c7882319f3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
9685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.338139685
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1045356719
Short name T515
Test name
Test status
Simulation time 42931558 ps
CPU time 4.42 seconds
Started Mar 19 02:07:25 PM PDT 24
Finished Mar 19 02:07:30 PM PDT 24
Peak memory 239232 kb
Host smart-c8cf7fe0-1510-439e-88f7-e46996eac6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10453
56719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1045356719
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2838317051
Short name T316
Test name
Test status
Simulation time 7574896818 ps
CPU time 86.58 seconds
Started Mar 19 02:07:25 PM PDT 24
Finished Mar 19 02:08:52 PM PDT 24
Peak memory 248904 kb
Host smart-5557a028-6e2e-4081-8e1f-752d80fa6b3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838317051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2838317051
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4119732575
Short name T26
Test name
Test status
Simulation time 2212288751 ps
CPU time 46.6 seconds
Started Mar 19 02:07:27 PM PDT 24
Finished Mar 19 02:08:14 PM PDT 24
Peak memory 256156 kb
Host smart-a9a31dd7-c2ea-4475-b84f-78c23e5e2574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41197
32575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4119732575
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.955376736
Short name T686
Test name
Test status
Simulation time 448108678 ps
CPU time 8.19 seconds
Started Mar 19 02:07:27 PM PDT 24
Finished Mar 19 02:07:35 PM PDT 24
Peak memory 251160 kb
Host smart-b81f8977-e703-451c-8403-5d66ef2c69de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95537
6736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.955376736
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.4271407655
Short name T64
Test name
Test status
Simulation time 614985636 ps
CPU time 39.58 seconds
Started Mar 19 02:07:26 PM PDT 24
Finished Mar 19 02:08:06 PM PDT 24
Peak memory 247468 kb
Host smart-0255ac10-df61-45f3-abdd-cd1c307b98aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
07655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.4271407655
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3035242107
Short name T577
Test name
Test status
Simulation time 493482478 ps
CPU time 38.05 seconds
Started Mar 19 02:07:26 PM PDT 24
Finished Mar 19 02:08:04 PM PDT 24
Peak memory 248876 kb
Host smart-6b744891-76b2-4022-bb9f-c5260aa05550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
42107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3035242107
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3552517234
Short name T222
Test name
Test status
Simulation time 216346983357 ps
CPU time 3437.76 seconds
Started Mar 19 02:07:35 PM PDT 24
Finished Mar 19 03:04:53 PM PDT 24
Peak memory 289688 kb
Host smart-2b694348-507f-4e30-a2d4-dce8e9f57a14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552517234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3552517234
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2577916971
Short name T213
Test name
Test status
Simulation time 1279025235 ps
CPU time 53.11 seconds
Started Mar 19 02:07:37 PM PDT 24
Finished Mar 19 02:08:30 PM PDT 24
Peak memory 256484 kb
Host smart-cae789a1-2c09-4658-bc20-83998a39132a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
16971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2577916971
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3873203172
Short name T478
Test name
Test status
Simulation time 512412655 ps
CPU time 33.59 seconds
Started Mar 19 02:07:37 PM PDT 24
Finished Mar 19 02:08:11 PM PDT 24
Peak memory 255828 kb
Host smart-461149b5-a20a-4dbf-b9de-a78c3a064cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732
03172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3873203172
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.364691598
Short name T537
Test name
Test status
Simulation time 15125866769 ps
CPU time 1441.35 seconds
Started Mar 19 02:07:48 PM PDT 24
Finished Mar 19 02:31:49 PM PDT 24
Peak memory 289464 kb
Host smart-95188c81-840b-4aec-b25c-188c36d5d530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364691598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.364691598
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.567268203
Short name T513
Test name
Test status
Simulation time 44521972443 ps
CPU time 1303.26 seconds
Started Mar 19 02:07:48 PM PDT 24
Finished Mar 19 02:29:31 PM PDT 24
Peak memory 289356 kb
Host smart-454edeed-4480-4a85-98a1-b1b26cb5d195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567268203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.567268203
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.580890701
Short name T714
Test name
Test status
Simulation time 40939054589 ps
CPU time 383.42 seconds
Started Mar 19 02:07:47 PM PDT 24
Finished Mar 19 02:14:11 PM PDT 24
Peak memory 247772 kb
Host smart-17f6d951-2636-4dad-85b2-2cdae0e205ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580890701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.580890701
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2751019681
Short name T570
Test name
Test status
Simulation time 427282157 ps
CPU time 31.76 seconds
Started Mar 19 02:07:37 PM PDT 24
Finished Mar 19 02:08:09 PM PDT 24
Peak memory 256860 kb
Host smart-8876d309-8297-42f5-9a0d-5620a610fe96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27510
19681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2751019681
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.4170557240
Short name T564
Test name
Test status
Simulation time 760303628 ps
CPU time 42.26 seconds
Started Mar 19 02:07:36 PM PDT 24
Finished Mar 19 02:08:19 PM PDT 24
Peak memory 248728 kb
Host smart-ec576579-d072-48b7-99b5-e1a914433a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41705
57240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.4170557240
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1304265959
Short name T494
Test name
Test status
Simulation time 154023874 ps
CPU time 10.14 seconds
Started Mar 19 02:07:48 PM PDT 24
Finished Mar 19 02:07:58 PM PDT 24
Peak memory 248860 kb
Host smart-2690a138-6b18-42a0-914a-1230f2e5d828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042
65959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1304265959
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.830415788
Short name T44
Test name
Test status
Simulation time 930660418 ps
CPU time 15.48 seconds
Started Mar 19 02:07:36 PM PDT 24
Finished Mar 19 02:07:51 PM PDT 24
Peak memory 248840 kb
Host smart-8b9a2373-f27d-445d-8bc6-09817f1106d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83041
5788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.830415788
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2621059803
Short name T57
Test name
Test status
Simulation time 62568909832 ps
CPU time 952.65 seconds
Started Mar 19 02:07:48 PM PDT 24
Finished Mar 19 02:23:41 PM PDT 24
Peak memory 273436 kb
Host smart-2c34eb30-e69e-458c-b908-98f189b6aa1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621059803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2621059803
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3735281400
Short name T601
Test name
Test status
Simulation time 58940570982 ps
CPU time 1032.8 seconds
Started Mar 19 02:07:48 PM PDT 24
Finished Mar 19 02:25:01 PM PDT 24
Peak memory 281760 kb
Host smart-18ed1dd5-29df-4c45-9883-c2c6e470bdd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735281400 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3735281400
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.662992506
Short name T120
Test name
Test status
Simulation time 97599986177 ps
CPU time 2925.57 seconds
Started Mar 19 02:07:57 PM PDT 24
Finished Mar 19 02:56:44 PM PDT 24
Peak memory 289608 kb
Host smart-6e2a6996-4f41-41a7-8b63-bcc5e880c4e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662992506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.662992506
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.710042352
Short name T552
Test name
Test status
Simulation time 2367120842 ps
CPU time 39.08 seconds
Started Mar 19 02:07:57 PM PDT 24
Finished Mar 19 02:08:36 PM PDT 24
Peak memory 248624 kb
Host smart-38e308b2-0093-4a3d-b3bb-61ba30b8c13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71004
2352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.710042352
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1470191151
Short name T327
Test name
Test status
Simulation time 143182047195 ps
CPU time 2197.79 seconds
Started Mar 19 02:08:08 PM PDT 24
Finished Mar 19 02:44:47 PM PDT 24
Peak memory 289064 kb
Host smart-1e8fd3d7-7409-43e1-9bf6-cdd1c050e00c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470191151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1470191151
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.498253001
Short name T406
Test name
Test status
Simulation time 265614214302 ps
CPU time 2293.59 seconds
Started Mar 19 02:08:08 PM PDT 24
Finished Mar 19 02:46:23 PM PDT 24
Peak memory 286980 kb
Host smart-3bea9a1d-ba22-4ff4-a850-461593d676f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498253001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.498253001
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.922865709
Short name T590
Test name
Test status
Simulation time 407228199 ps
CPU time 21.9 seconds
Started Mar 19 02:07:58 PM PDT 24
Finished Mar 19 02:08:20 PM PDT 24
Peak memory 249112 kb
Host smart-12ba1eab-45be-4147-bb01-6b7a6e28fa5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92286
5709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.922865709
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3052922519
Short name T381
Test name
Test status
Simulation time 749388838 ps
CPU time 36.75 seconds
Started Mar 19 02:07:58 PM PDT 24
Finished Mar 19 02:08:35 PM PDT 24
Peak memory 256808 kb
Host smart-4e18f691-75e3-4723-b496-40a22960b4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30529
22519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3052922519
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1549601178
Short name T448
Test name
Test status
Simulation time 4539738804 ps
CPU time 56.36 seconds
Started Mar 19 02:07:48 PM PDT 24
Finished Mar 19 02:08:44 PM PDT 24
Peak memory 248860 kb
Host smart-631708b8-9791-4f32-9c3f-3cdabdc635ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15496
01178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1549601178
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2477692258
Short name T653
Test name
Test status
Simulation time 9995463740 ps
CPU time 78.23 seconds
Started Mar 19 02:08:06 PM PDT 24
Finished Mar 19 02:09:25 PM PDT 24
Peak memory 248872 kb
Host smart-09d57fce-8d15-443f-9234-82e56f827617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24776
92258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2477692258
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.502084445
Short name T526
Test name
Test status
Simulation time 136368174 ps
CPU time 9.7 seconds
Started Mar 19 02:08:07 PM PDT 24
Finished Mar 19 02:08:16 PM PDT 24
Peak memory 248884 kb
Host smart-d3ec69e5-c33a-48c6-8a25-9062b36b16c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50208
4445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.502084445
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.145404882
Short name T705
Test name
Test status
Simulation time 167059252942 ps
CPU time 2635.39 seconds
Started Mar 19 02:08:22 PM PDT 24
Finished Mar 19 02:52:17 PM PDT 24
Peak memory 288332 kb
Host smart-975f0a00-f53c-46ce-b37b-ace8b7dafc3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145404882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.145404882
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1269238204
Short name T702
Test name
Test status
Simulation time 11613997717 ps
CPU time 106.93 seconds
Started Mar 19 02:08:22 PM PDT 24
Finished Mar 19 02:10:09 PM PDT 24
Peak memory 248168 kb
Host smart-9f7ccfb6-bbac-444a-9399-6e7d773b80df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269238204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1269238204
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1128041602
Short name T53
Test name
Test status
Simulation time 168963498 ps
CPU time 14.63 seconds
Started Mar 19 02:08:09 PM PDT 24
Finished Mar 19 02:08:24 PM PDT 24
Peak memory 254824 kb
Host smart-8b311a07-b646-4e07-829d-f1f4f36d81de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11280
41602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1128041602
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2699627012
Short name T544
Test name
Test status
Simulation time 1504670257 ps
CPU time 31.05 seconds
Started Mar 19 02:08:07 PM PDT 24
Finished Mar 19 02:08:39 PM PDT 24
Peak memory 255868 kb
Host smart-334e430b-3e45-4b44-b69f-f62c0dac438a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26996
27012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2699627012
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3098357538
Short name T434
Test name
Test status
Simulation time 3051980764 ps
CPU time 49.6 seconds
Started Mar 19 02:08:21 PM PDT 24
Finished Mar 19 02:09:11 PM PDT 24
Peak memory 248920 kb
Host smart-c5abf941-18bf-4f86-86b4-1d5d67a667d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
57538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3098357538
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4147634154
Short name T652
Test name
Test status
Simulation time 780076937 ps
CPU time 48.64 seconds
Started Mar 19 02:08:09 PM PDT 24
Finished Mar 19 02:08:58 PM PDT 24
Peak memory 256028 kb
Host smart-60b924aa-84f4-4339-92a6-c18af9cd2c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41476
34154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4147634154
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3625964086
Short name T432
Test name
Test status
Simulation time 60663052139 ps
CPU time 814.18 seconds
Started Mar 19 02:08:20 PM PDT 24
Finished Mar 19 02:21:54 PM PDT 24
Peak memory 265304 kb
Host smart-deb1d676-c836-4d8f-a087-0c1419bebbfb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625964086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3625964086
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1069429846
Short name T688
Test name
Test status
Simulation time 39698055919 ps
CPU time 636.19 seconds
Started Mar 19 02:08:42 PM PDT 24
Finished Mar 19 02:19:19 PM PDT 24
Peak memory 265224 kb
Host smart-ee6e4fdd-4e84-445f-afaa-30b5f26557e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069429846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1069429846
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3534689994
Short name T549
Test name
Test status
Simulation time 4950094850 ps
CPU time 176.02 seconds
Started Mar 19 02:08:42 PM PDT 24
Finished Mar 19 02:11:39 PM PDT 24
Peak memory 257080 kb
Host smart-1788a29b-e484-418b-b752-dd2735c7adbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346
89994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3534689994
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2335199974
Short name T518
Test name
Test status
Simulation time 786177793 ps
CPU time 53.13 seconds
Started Mar 19 02:08:32 PM PDT 24
Finished Mar 19 02:09:25 PM PDT 24
Peak memory 255828 kb
Host smart-b9a83fee-5788-403a-8d5d-b4ce5506077b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23351
99974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2335199974
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1266278597
Short name T585
Test name
Test status
Simulation time 28334157967 ps
CPU time 1898.42 seconds
Started Mar 19 02:08:43 PM PDT 24
Finished Mar 19 02:40:21 PM PDT 24
Peak memory 282368 kb
Host smart-bdf9fd6e-fb71-468b-94b4-d724dd86dd68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266278597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1266278597
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.10415726
Short name T622
Test name
Test status
Simulation time 92812781962 ps
CPU time 1852.43 seconds
Started Mar 19 02:08:41 PM PDT 24
Finished Mar 19 02:39:34 PM PDT 24
Peak memory 273480 kb
Host smart-9aac0598-64c1-4c90-b418-7433ff02b797
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10415726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.10415726
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4272589152
Short name T296
Test name
Test status
Simulation time 4434257770 ps
CPU time 184.06 seconds
Started Mar 19 02:08:42 PM PDT 24
Finished Mar 19 02:11:46 PM PDT 24
Peak memory 247808 kb
Host smart-33272fc2-0ed3-4a9e-bc0d-855977a0ba12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272589152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4272589152
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1010346782
Short name T393
Test name
Test status
Simulation time 86087316 ps
CPU time 7.54 seconds
Started Mar 19 02:08:31 PM PDT 24
Finished Mar 19 02:08:39 PM PDT 24
Peak memory 240664 kb
Host smart-92865c04-145f-4213-bd19-cc7d0c08a89f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10103
46782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1010346782
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3907644473
Short name T636
Test name
Test status
Simulation time 320372924 ps
CPU time 4.63 seconds
Started Mar 19 02:08:32 PM PDT 24
Finished Mar 19 02:08:37 PM PDT 24
Peak memory 249864 kb
Host smart-02bf799c-840b-4726-b384-2f1cfc019db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39076
44473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3907644473
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.381735725
Short name T293
Test name
Test status
Simulation time 54867435 ps
CPU time 4.71 seconds
Started Mar 19 02:08:43 PM PDT 24
Finished Mar 19 02:08:48 PM PDT 24
Peak memory 240660 kb
Host smart-33d3ad4d-0285-4a78-b4c1-520f2aa617ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38173
5725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.381735725
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.5086300
Short name T548
Test name
Test status
Simulation time 849307029 ps
CPU time 18.17 seconds
Started Mar 19 02:08:32 PM PDT 24
Finished Mar 19 02:08:50 PM PDT 24
Peak memory 248796 kb
Host smart-e0975aa2-3922-4707-9c94-18ddc62524b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50863
00 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.5086300
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3163647712
Short name T540
Test name
Test status
Simulation time 36480463239 ps
CPU time 906.8 seconds
Started Mar 19 02:08:41 PM PDT 24
Finished Mar 19 02:23:48 PM PDT 24
Peak memory 273444 kb
Host smart-f0e5d7e3-d82b-4958-99fe-25d4b1a493d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163647712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3163647712
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.756562498
Short name T439
Test name
Test status
Simulation time 36450150943 ps
CPU time 1197.58 seconds
Started Mar 19 02:08:53 PM PDT 24
Finished Mar 19 02:28:51 PM PDT 24
Peak memory 272220 kb
Host smart-a0fef8bb-4e68-4e68-82ab-791529b300a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756562498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.756562498
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3168572878
Short name T626
Test name
Test status
Simulation time 3404828111 ps
CPU time 222.15 seconds
Started Mar 19 02:08:53 PM PDT 24
Finished Mar 19 02:12:36 PM PDT 24
Peak memory 249904 kb
Host smart-f02691e9-ba70-4912-b8dd-2ae415a73bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31685
72878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3168572878
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3323445470
Short name T620
Test name
Test status
Simulation time 1480405292 ps
CPU time 45.23 seconds
Started Mar 19 02:08:55 PM PDT 24
Finished Mar 19 02:09:40 PM PDT 24
Peak memory 254892 kb
Host smart-b02887d1-cf8c-4f1e-8906-b228aef0586a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
45470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3323445470
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2083221757
Short name T121
Test name
Test status
Simulation time 31241075803 ps
CPU time 2045.23 seconds
Started Mar 19 02:08:57 PM PDT 24
Finished Mar 19 02:43:03 PM PDT 24
Peak memory 272472 kb
Host smart-c8f82b78-8182-436d-b084-bf41fb4f24c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083221757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2083221757
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1146128220
Short name T385
Test name
Test status
Simulation time 25998023306 ps
CPU time 1730.93 seconds
Started Mar 19 02:08:53 PM PDT 24
Finished Mar 19 02:37:44 PM PDT 24
Peak memory 281712 kb
Host smart-6e976e25-a8e4-4000-b6dc-304abdc1d5ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146128220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1146128220
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1968391552
Short name T559
Test name
Test status
Simulation time 243986661 ps
CPU time 29.25 seconds
Started Mar 19 02:08:54 PM PDT 24
Finished Mar 19 02:09:24 PM PDT 24
Peak memory 249036 kb
Host smart-275f2487-4ec7-43ad-ae7f-bd57f876714e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
91552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1968391552
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4257850524
Short name T713
Test name
Test status
Simulation time 833048786 ps
CPU time 21.25 seconds
Started Mar 19 02:08:53 PM PDT 24
Finished Mar 19 02:09:15 PM PDT 24
Peak memory 254704 kb
Host smart-0fce69b1-d107-45c5-9045-83aeeae7e7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
50524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4257850524
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1763721126
Short name T394
Test name
Test status
Simulation time 884058628 ps
CPU time 31.32 seconds
Started Mar 19 02:08:57 PM PDT 24
Finished Mar 19 02:09:29 PM PDT 24
Peak memory 255964 kb
Host smart-76bf07e6-a5c5-4e4d-bcfc-321d00271f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
21126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1763721126
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2226353585
Short name T465
Test name
Test status
Simulation time 249164144 ps
CPU time 26.29 seconds
Started Mar 19 02:08:55 PM PDT 24
Finished Mar 19 02:09:22 PM PDT 24
Peak memory 248860 kb
Host smart-4b7c5a33-f9d9-43bb-b72a-88b4684e645a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22263
53585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2226353585
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3743372607
Short name T497
Test name
Test status
Simulation time 5739792602 ps
CPU time 832.87 seconds
Started Mar 19 02:09:05 PM PDT 24
Finished Mar 19 02:22:58 PM PDT 24
Peak memory 273420 kb
Host smart-a0c41cc0-c976-4fcd-b346-9a63904f25fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743372607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3743372607
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1834883044
Short name T269
Test name
Test status
Simulation time 172338851653 ps
CPU time 4108.12 seconds
Started Mar 19 02:09:06 PM PDT 24
Finished Mar 19 03:17:35 PM PDT 24
Peak memory 314540 kb
Host smart-bb2b3324-9ecd-4319-aba8-9f4b37364a06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834883044 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1834883044
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4143826991
Short name T648
Test name
Test status
Simulation time 40535926131 ps
CPU time 2455.98 seconds
Started Mar 19 02:09:13 PM PDT 24
Finished Mar 19 02:50:09 PM PDT 24
Peak memory 284804 kb
Host smart-90341821-b0c0-4998-b3b7-09a940eb5324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143826991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4143826991
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2673269485
Short name T582
Test name
Test status
Simulation time 2470187212 ps
CPU time 145.35 seconds
Started Mar 19 02:09:13 PM PDT 24
Finished Mar 19 02:11:38 PM PDT 24
Peak memory 256924 kb
Host smart-38e6b069-ceb7-4c8c-903d-9367b26f99f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26732
69485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2673269485
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3383273339
Short name T87
Test name
Test status
Simulation time 191020836 ps
CPU time 7.65 seconds
Started Mar 19 02:09:06 PM PDT 24
Finished Mar 19 02:09:14 PM PDT 24
Peak memory 257072 kb
Host smart-661a92b4-6e12-4285-904a-6c09b0ce3888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33832
73339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3383273339
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4209350032
Short name T13
Test name
Test status
Simulation time 152020872040 ps
CPU time 1554.27 seconds
Started Mar 19 02:09:25 PM PDT 24
Finished Mar 19 02:35:20 PM PDT 24
Peak memory 273232 kb
Host smart-8a48bbfb-157d-4ee9-b45e-dc0937691f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209350032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4209350032
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2735158562
Short name T16
Test name
Test status
Simulation time 38011255848 ps
CPU time 2332.66 seconds
Started Mar 19 02:09:24 PM PDT 24
Finished Mar 19 02:48:17 PM PDT 24
Peak memory 272788 kb
Host smart-963c549c-16b2-4ae3-9d49-8a1dca7040e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735158562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2735158562
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3630050364
Short name T41
Test name
Test status
Simulation time 5438871147 ps
CPU time 230.87 seconds
Started Mar 19 02:09:14 PM PDT 24
Finished Mar 19 02:13:05 PM PDT 24
Peak memory 247972 kb
Host smart-8b39852b-daa8-4606-8691-43ab1b05253b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630050364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3630050364
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3293695111
Short name T474
Test name
Test status
Simulation time 10638745831 ps
CPU time 41.6 seconds
Started Mar 19 02:09:05 PM PDT 24
Finished Mar 19 02:09:47 PM PDT 24
Peak memory 256164 kb
Host smart-2825f7c4-be97-47dc-afee-c7e18ef7f559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
95111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3293695111
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3473096903
Short name T58
Test name
Test status
Simulation time 955319902 ps
CPU time 65.99 seconds
Started Mar 19 02:09:05 PM PDT 24
Finished Mar 19 02:10:11 PM PDT 24
Peak memory 248800 kb
Host smart-669257e8-104e-4660-bcad-5e50526a5011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34730
96903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3473096903
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1445339122
Short name T489
Test name
Test status
Simulation time 73051047 ps
CPU time 11.76 seconds
Started Mar 19 02:09:13 PM PDT 24
Finished Mar 19 02:09:25 PM PDT 24
Peak memory 248780 kb
Host smart-81bccc24-be58-4a15-a6e4-2308988abe98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14453
39122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1445339122
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3123091427
Short name T356
Test name
Test status
Simulation time 365313103 ps
CPU time 24.26 seconds
Started Mar 19 02:09:04 PM PDT 24
Finished Mar 19 02:09:28 PM PDT 24
Peak memory 254948 kb
Host smart-0927e49c-a144-4915-9df4-1e7bd0bae8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31230
91427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3123091427
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4280828413
Short name T31
Test name
Test status
Simulation time 132555930632 ps
CPU time 1333.13 seconds
Started Mar 19 02:09:24 PM PDT 24
Finished Mar 19 02:31:38 PM PDT 24
Peak memory 272804 kb
Host smart-0744b25f-e705-4e35-b8f1-6f95545a447e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280828413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4280828413
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2703301963
Short name T231
Test name
Test status
Simulation time 66496969 ps
CPU time 3.1 seconds
Started Mar 19 02:02:08 PM PDT 24
Finished Mar 19 02:02:11 PM PDT 24
Peak memory 249040 kb
Host smart-d1497eb7-c5f1-44a6-bd6b-1fd28646d04f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2703301963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2703301963
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1722120016
Short name T482
Test name
Test status
Simulation time 114422919293 ps
CPU time 1755.01 seconds
Started Mar 19 02:02:39 PM PDT 24
Finished Mar 19 02:31:55 PM PDT 24
Peak memory 283964 kb
Host smart-fd0fd3e2-7bca-4303-8eeb-32b2231c8da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722120016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1722120016
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.44784846
Short name T407
Test name
Test status
Simulation time 2548958255 ps
CPU time 29.44 seconds
Started Mar 19 02:04:42 PM PDT 24
Finished Mar 19 02:05:12 PM PDT 24
Peak memory 240724 kb
Host smart-9666dc75-f143-427d-bec5-86467a5e9b21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=44784846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.44784846
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3477271870
Short name T245
Test name
Test status
Simulation time 1494787817 ps
CPU time 28.49 seconds
Started Mar 19 02:02:40 PM PDT 24
Finished Mar 19 02:03:09 PM PDT 24
Peak memory 248476 kb
Host smart-7e15ccbf-2647-4e77-93ae-a0e24a9edf5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34772
71870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3477271870
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3755611488
Short name T594
Test name
Test status
Simulation time 797669895 ps
CPU time 27.99 seconds
Started Mar 19 02:02:12 PM PDT 24
Finished Mar 19 02:02:40 PM PDT 24
Peak memory 249020 kb
Host smart-3c569120-26bb-42c5-84af-65ee4aa29958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37556
11488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3755611488
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4038422638
Short name T324
Test name
Test status
Simulation time 17210739112 ps
CPU time 1553.18 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:28:03 PM PDT 24
Peak memory 289004 kb
Host smart-bb50bb5e-dbcb-4b25-b4a2-108da4cd49c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038422638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4038422638
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1084313698
Short name T599
Test name
Test status
Simulation time 13510185676 ps
CPU time 1325.92 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:24:16 PM PDT 24
Peak memory 287016 kb
Host smart-ec9ef60c-4ece-44c8-a23d-3f0a6103c7e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084313698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1084313698
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2057630588
Short name T512
Test name
Test status
Simulation time 15621410361 ps
CPU time 171.28 seconds
Started Mar 19 02:02:14 PM PDT 24
Finished Mar 19 02:05:05 PM PDT 24
Peak memory 247996 kb
Host smart-f7db6c8b-c726-4fc7-a2ec-891a50a9761b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057630588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2057630588
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.190618441
Short name T401
Test name
Test status
Simulation time 356901509 ps
CPU time 31.21 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:02:41 PM PDT 24
Peak memory 256036 kb
Host smart-6f9fd0fa-f97f-4c3f-87e5-1457d3b651d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19061
8441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.190618441
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.75408544
Short name T122
Test name
Test status
Simulation time 992895260 ps
CPU time 32.39 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:02:43 PM PDT 24
Peak memory 255396 kb
Host smart-f31b0d5f-c796-42e8-8987-a74228da0304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75408
544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.75408544
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2248746436
Short name T371
Test name
Test status
Simulation time 3504392101 ps
CPU time 28.84 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:02:39 PM PDT 24
Peak memory 248940 kb
Host smart-bb78a8e5-b2b3-4482-8d1e-7a044426f136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
46436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2248746436
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3882666371
Short name T479
Test name
Test status
Simulation time 359927727 ps
CPU time 30.93 seconds
Started Mar 19 02:02:13 PM PDT 24
Finished Mar 19 02:02:44 PM PDT 24
Peak memory 248808 kb
Host smart-32149782-b19e-42d7-abf3-90a858e6439e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38826
66371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3882666371
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2931898283
Short name T692
Test name
Test status
Simulation time 72304780609 ps
CPU time 1978.81 seconds
Started Mar 19 02:02:14 PM PDT 24
Finished Mar 19 02:35:13 PM PDT 24
Peak memory 281620 kb
Host smart-8e6f8a13-0603-4d6d-a077-d7ba796acddd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931898283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2931898283
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2392757206
Short name T447
Test name
Test status
Simulation time 45434667550 ps
CPU time 1040.71 seconds
Started Mar 19 02:09:25 PM PDT 24
Finished Mar 19 02:26:46 PM PDT 24
Peak memory 273416 kb
Host smart-f8034f8d-0e46-4687-bb1b-631c4ac7689b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392757206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2392757206
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.705714624
Short name T691
Test name
Test status
Simulation time 35617992 ps
CPU time 2.88 seconds
Started Mar 19 02:09:23 PM PDT 24
Finished Mar 19 02:09:26 PM PDT 24
Peak memory 239028 kb
Host smart-84f954c0-f64c-476b-a47a-7d1918a7395f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70571
4624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.705714624
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1273601733
Short name T472
Test name
Test status
Simulation time 2998429283 ps
CPU time 46.9 seconds
Started Mar 19 02:09:24 PM PDT 24
Finished Mar 19 02:10:11 PM PDT 24
Peak memory 254976 kb
Host smart-644f9669-531e-420e-9b27-926eea3a7dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12736
01733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1273601733
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.161394725
Short name T332
Test name
Test status
Simulation time 48763811112 ps
CPU time 1070.82 seconds
Started Mar 19 02:11:28 PM PDT 24
Finished Mar 19 02:29:20 PM PDT 24
Peak memory 268412 kb
Host smart-332575f4-4fb3-4d2d-b8ee-831535f4bfe3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161394725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.161394725
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4195002101
Short name T14
Test name
Test status
Simulation time 38841165352 ps
CPU time 1477.4 seconds
Started Mar 19 02:12:14 PM PDT 24
Finished Mar 19 02:36:52 PM PDT 24
Peak memory 273324 kb
Host smart-2f45281b-f40f-4190-a25f-6333a4add573
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195002101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4195002101
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3136826558
Short name T70
Test name
Test status
Simulation time 12057519734 ps
CPU time 275.53 seconds
Started Mar 19 02:12:00 PM PDT 24
Finished Mar 19 02:16:36 PM PDT 24
Peak memory 248080 kb
Host smart-805c1707-d368-44fe-b076-a193d2dab9f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136826558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3136826558
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3450071503
Short name T20
Test name
Test status
Simulation time 728709747 ps
CPU time 12.81 seconds
Started Mar 19 02:09:23 PM PDT 24
Finished Mar 19 02:09:36 PM PDT 24
Peak memory 248860 kb
Host smart-ffe16f83-e245-45ae-8f3a-285fc8970c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34500
71503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3450071503
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1547894265
Short name T30
Test name
Test status
Simulation time 98283286 ps
CPU time 10.79 seconds
Started Mar 19 02:09:24 PM PDT 24
Finished Mar 19 02:09:35 PM PDT 24
Peak memory 248852 kb
Host smart-bced6a8a-0c37-4f60-b08c-e0606b2b68a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15478
94265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1547894265
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1340191425
Short name T621
Test name
Test status
Simulation time 711950693 ps
CPU time 51.18 seconds
Started Mar 19 02:09:25 PM PDT 24
Finished Mar 19 02:10:16 PM PDT 24
Peak memory 255976 kb
Host smart-363c94b5-927e-4025-b6d2-a8e27d3e84cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13401
91425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1340191425
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2717626027
Short name T79
Test name
Test status
Simulation time 29679642913 ps
CPU time 2118.75 seconds
Started Mar 19 02:12:08 PM PDT 24
Finished Mar 19 02:47:27 PM PDT 24
Peak memory 281748 kb
Host smart-bef5104e-a980-4646-a6e8-0c088aec8cc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717626027 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2717626027
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3368825460
Short name T108
Test name
Test status
Simulation time 361036732595 ps
CPU time 3201.61 seconds
Started Mar 19 02:12:10 PM PDT 24
Finished Mar 19 03:05:32 PM PDT 24
Peak memory 289200 kb
Host smart-fb6446df-7c2e-4d5a-a079-6e6b5c3e824c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368825460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3368825460
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.4019548400
Short name T496
Test name
Test status
Simulation time 4236947800 ps
CPU time 107.25 seconds
Started Mar 19 02:12:20 PM PDT 24
Finished Mar 19 02:14:09 PM PDT 24
Peak memory 256644 kb
Host smart-59121a91-8dc4-49ce-999d-55e9fdecc428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
48400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.4019548400
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.536629463
Short name T685
Test name
Test status
Simulation time 1700202933 ps
CPU time 28.61 seconds
Started Mar 19 02:11:38 PM PDT 24
Finished Mar 19 02:12:08 PM PDT 24
Peak memory 255424 kb
Host smart-0d8826e6-9734-4a94-8abb-900cf949ae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53662
9463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.536629463
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1365461495
Short name T321
Test name
Test status
Simulation time 28057176207 ps
CPU time 1640.65 seconds
Started Mar 19 02:12:18 PM PDT 24
Finished Mar 19 02:39:42 PM PDT 24
Peak memory 273320 kb
Host smart-6ddeafa8-9a05-4e20-8a59-1c617d6403b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365461495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1365461495
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1590222927
Short name T302
Test name
Test status
Simulation time 9355849437 ps
CPU time 395.65 seconds
Started Mar 19 02:11:44 PM PDT 24
Finished Mar 19 02:18:21 PM PDT 24
Peak memory 247736 kb
Host smart-ee65ca96-8576-4ce9-8b24-d417d34c1df4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590222927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1590222927
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2384633250
Short name T353
Test name
Test status
Simulation time 2284819875 ps
CPU time 33.97 seconds
Started Mar 19 02:12:03 PM PDT 24
Finished Mar 19 02:12:37 PM PDT 24
Peak memory 256104 kb
Host smart-a39b4484-3992-40cd-87b6-b56df8babd74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23846
33250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2384633250
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4129869697
Short name T528
Test name
Test status
Simulation time 425016672 ps
CPU time 7.28 seconds
Started Mar 19 02:12:13 PM PDT 24
Finished Mar 19 02:12:20 PM PDT 24
Peak memory 248852 kb
Host smart-5731ec77-f9f5-4634-bc55-5915b26c13b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41298
69697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4129869697
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3606680625
Short name T255
Test name
Test status
Simulation time 3224544306 ps
CPU time 56.23 seconds
Started Mar 19 02:12:14 PM PDT 24
Finished Mar 19 02:13:11 PM PDT 24
Peak memory 255672 kb
Host smart-662209ee-b2a1-4b07-a413-a2f157f64a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
80625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3606680625
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2683924071
Short name T433
Test name
Test status
Simulation time 1083008877 ps
CPU time 53.25 seconds
Started Mar 19 02:11:51 PM PDT 24
Finished Mar 19 02:12:44 PM PDT 24
Peak memory 248876 kb
Host smart-217c4621-f918-4c1d-9b97-d3dcdfd66e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26839
24071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2683924071
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.689967842
Short name T123
Test name
Test status
Simulation time 25775103989 ps
CPU time 336.65 seconds
Started Mar 19 02:12:19 PM PDT 24
Finished Mar 19 02:17:58 PM PDT 24
Peak memory 256992 kb
Host smart-495046ce-ff49-49bf-a5ce-bedf8f9732ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689967842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.689967842
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3983442003
Short name T65
Test name
Test status
Simulation time 53901399256 ps
CPU time 6098.62 seconds
Started Mar 19 02:12:15 PM PDT 24
Finished Mar 19 03:53:55 PM PDT 24
Peak memory 338456 kb
Host smart-b951e9bb-65db-4b6b-8624-ff405fb9fe25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983442003 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3983442003
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4279198831
Short name T647
Test name
Test status
Simulation time 14875809228 ps
CPU time 957.19 seconds
Started Mar 19 02:12:16 PM PDT 24
Finished Mar 19 02:28:14 PM PDT 24
Peak memory 273444 kb
Host smart-c6f1ea16-7ee0-499f-82ff-cd6875d2683b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279198831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4279198831
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1990276997
Short name T527
Test name
Test status
Simulation time 4754037048 ps
CPU time 304.83 seconds
Started Mar 19 02:11:55 PM PDT 24
Finished Mar 19 02:17:01 PM PDT 24
Peak memory 250976 kb
Host smart-b12b592f-4c1e-4623-be3b-a347ae5076b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19902
76997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1990276997
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3316347822
Short name T264
Test name
Test status
Simulation time 6557792765 ps
CPU time 33.62 seconds
Started Mar 19 02:11:56 PM PDT 24
Finished Mar 19 02:12:30 PM PDT 24
Peak memory 254880 kb
Host smart-ebc46376-1358-4c94-b845-bc950e11a1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33163
47822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3316347822
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4020168959
Short name T351
Test name
Test status
Simulation time 40478969722 ps
CPU time 1002.53 seconds
Started Mar 19 02:12:08 PM PDT 24
Finished Mar 19 02:28:50 PM PDT 24
Peak memory 273356 kb
Host smart-94614a5b-0dc3-4472-b21d-a77724cc617d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020168959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4020168959
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1124375279
Short name T706
Test name
Test status
Simulation time 38169206903 ps
CPU time 1199.88 seconds
Started Mar 19 02:12:11 PM PDT 24
Finished Mar 19 02:32:11 PM PDT 24
Peak memory 272804 kb
Host smart-fc7de253-942a-40ce-bdec-752a654de65b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124375279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1124375279
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3623458964
Short name T72
Test name
Test status
Simulation time 8530667908 ps
CPU time 328.87 seconds
Started Mar 19 02:12:06 PM PDT 24
Finished Mar 19 02:17:35 PM PDT 24
Peak memory 248144 kb
Host smart-a5f82452-dd02-4456-ad2f-09fd13471bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623458964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3623458964
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2791397515
Short name T453
Test name
Test status
Simulation time 359841865 ps
CPU time 16.35 seconds
Started Mar 19 02:12:17 PM PDT 24
Finished Mar 19 02:12:34 PM PDT 24
Peak memory 248800 kb
Host smart-e5bae8c5-5d92-4d1c-8906-1544c55e68ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27913
97515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2791397515
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.409744441
Short name T618
Test name
Test status
Simulation time 1564677563 ps
CPU time 57.33 seconds
Started Mar 19 02:11:35 PM PDT 24
Finished Mar 19 02:12:33 PM PDT 24
Peak memory 255392 kb
Host smart-4335889e-3d52-4b2d-91a4-d9b8e4e99356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974
4441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.409744441
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1581413474
Short name T698
Test name
Test status
Simulation time 164710391 ps
CPU time 7.19 seconds
Started Mar 19 02:11:59 PM PDT 24
Finished Mar 19 02:12:06 PM PDT 24
Peak memory 251912 kb
Host smart-448f1448-736b-4204-af9f-29a3ca534f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
13474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1581413474
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1092736494
Short name T197
Test name
Test status
Simulation time 3769622407 ps
CPU time 52.03 seconds
Started Mar 19 02:12:18 PM PDT 24
Finished Mar 19 02:13:13 PM PDT 24
Peak memory 256052 kb
Host smart-10cd78dc-65b4-4ca1-bb16-5daf3ba33067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10927
36494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1092736494
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.409589539
Short name T116
Test name
Test status
Simulation time 34566602596 ps
CPU time 2208.2 seconds
Started Mar 19 02:12:02 PM PDT 24
Finished Mar 19 02:48:51 PM PDT 24
Peak memory 286840 kb
Host smart-273004f2-34c4-4865-a1d0-cdfaafb7fc51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409589539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.409589539
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3382791453
Short name T54
Test name
Test status
Simulation time 234991404130 ps
CPU time 2898.13 seconds
Started Mar 19 02:12:20 PM PDT 24
Finished Mar 19 03:00:40 PM PDT 24
Peak memory 321992 kb
Host smart-0bd3a766-ff5f-4407-93ab-0d3a45881452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382791453 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3382791453
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1783289485
Short name T654
Test name
Test status
Simulation time 107816201239 ps
CPU time 3202.82 seconds
Started Mar 19 02:12:01 PM PDT 24
Finished Mar 19 03:05:24 PM PDT 24
Peak memory 289148 kb
Host smart-dcc4c441-f957-4674-8e5e-34292cf105bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783289485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1783289485
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.4126889260
Short name T689
Test name
Test status
Simulation time 20165421395 ps
CPU time 240.36 seconds
Started Mar 19 02:12:06 PM PDT 24
Finished Mar 19 02:16:06 PM PDT 24
Peak memory 249944 kb
Host smart-c51ddf3e-2e5f-4061-92ec-5fdfb2911da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41268
89260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4126889260
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3717467154
Short name T699
Test name
Test status
Simulation time 2731397493 ps
CPU time 52.61 seconds
Started Mar 19 02:12:17 PM PDT 24
Finished Mar 19 02:13:10 PM PDT 24
Peak memory 249116 kb
Host smart-d8a2252d-3a13-4739-b679-ee37ecd3a0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37174
67154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3717467154
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2607921154
Short name T98
Test name
Test status
Simulation time 72636349996 ps
CPU time 1799.57 seconds
Started Mar 19 02:11:25 PM PDT 24
Finished Mar 19 02:41:25 PM PDT 24
Peak memory 289596 kb
Host smart-834ef01d-69fe-4c9e-a97a-98ead4934aa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607921154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2607921154
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1755026377
Short name T51
Test name
Test status
Simulation time 102652281822 ps
CPU time 946.64 seconds
Started Mar 19 02:12:17 PM PDT 24
Finished Mar 19 02:28:04 PM PDT 24
Peak memory 272908 kb
Host smart-89f45245-59f4-42ca-891b-fd6ef4562be6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755026377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1755026377
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.547343084
Short name T305
Test name
Test status
Simulation time 11442616370 ps
CPU time 201.94 seconds
Started Mar 19 02:12:01 PM PDT 24
Finished Mar 19 02:15:23 PM PDT 24
Peak memory 248064 kb
Host smart-447c3ab6-3550-45d9-b69f-09432661a0a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547343084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.547343084
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3846519474
Short name T77
Test name
Test status
Simulation time 1557640850 ps
CPU time 20.44 seconds
Started Mar 19 02:12:18 PM PDT 24
Finished Mar 19 02:12:41 PM PDT 24
Peak memory 248704 kb
Host smart-1dd84f63-85ce-429a-a6cd-75dd7c633189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38465
19474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3846519474
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.953029966
Short name T481
Test name
Test status
Simulation time 79426049 ps
CPU time 6.26 seconds
Started Mar 19 02:12:07 PM PDT 24
Finished Mar 19 02:12:13 PM PDT 24
Peak memory 239208 kb
Host smart-5210879b-95a3-4106-9040-e310685c3cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95302
9966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.953029966
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1293752905
Short name T215
Test name
Test status
Simulation time 847321215 ps
CPU time 66.35 seconds
Started Mar 19 02:11:58 PM PDT 24
Finished Mar 19 02:13:05 PM PDT 24
Peak memory 248584 kb
Host smart-c1d2f691-ff28-465b-8efc-d0148ee4c524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12937
52905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1293752905
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.925801179
Short name T490
Test name
Test status
Simulation time 258473618 ps
CPU time 19.17 seconds
Started Mar 19 02:12:16 PM PDT 24
Finished Mar 19 02:12:35 PM PDT 24
Peak memory 254152 kb
Host smart-a8c3f478-69f3-486c-9489-4f249ca8d11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92580
1179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.925801179
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3340035184
Short name T399
Test name
Test status
Simulation time 44720393737 ps
CPU time 1079.4 seconds
Started Mar 19 02:12:12 PM PDT 24
Finished Mar 19 02:30:12 PM PDT 24
Peak memory 273504 kb
Host smart-e7a03017-3e79-46d4-a2be-0960aaab8ba1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340035184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3340035184
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1812015176
Short name T541
Test name
Test status
Simulation time 179375658888 ps
CPU time 9304.77 seconds
Started Mar 19 02:12:12 PM PDT 24
Finished Mar 19 04:47:18 PM PDT 24
Peak memory 371776 kb
Host smart-89faac5b-14b3-4432-acaf-53cf5991888d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812015176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1812015176
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3269900407
Short name T613
Test name
Test status
Simulation time 38581913587 ps
CPU time 2165.4 seconds
Started Mar 19 02:12:07 PM PDT 24
Finished Mar 19 02:48:13 PM PDT 24
Peak memory 272900 kb
Host smart-b31119b4-08a6-4f25-9381-b0c65e8e95b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269900407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3269900407
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.986348157
Short name T366
Test name
Test status
Simulation time 5024678797 ps
CPU time 125.35 seconds
Started Mar 19 02:12:01 PM PDT 24
Finished Mar 19 02:14:07 PM PDT 24
Peak memory 257084 kb
Host smart-879ad7cb-4ea6-4c3c-8348-75d4c21d7167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98634
8157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.986348157
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1573445324
Short name T81
Test name
Test status
Simulation time 1643125158 ps
CPU time 48.6 seconds
Started Mar 19 02:12:18 PM PDT 24
Finished Mar 19 02:13:10 PM PDT 24
Peak memory 248680 kb
Host smart-b6e12b1d-59d8-40e3-ae4f-f2d6fcfa9fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15734
45324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1573445324
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.778707291
Short name T708
Test name
Test status
Simulation time 50134781200 ps
CPU time 2695.74 seconds
Started Mar 19 02:12:20 PM PDT 24
Finished Mar 19 02:57:17 PM PDT 24
Peak memory 289352 kb
Host smart-3880c440-41d1-40f9-9199-a57c6d166ee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778707291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.778707291
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.33054780
Short name T507
Test name
Test status
Simulation time 91312295088 ps
CPU time 1838.46 seconds
Started Mar 19 02:12:11 PM PDT 24
Finished Mar 19 02:42:49 PM PDT 24
Peak memory 288004 kb
Host smart-29decb0f-c364-431c-a84a-109018ae9f50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33054780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.33054780
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1519519688
Short name T313
Test name
Test status
Simulation time 7492263931 ps
CPU time 315.15 seconds
Started Mar 19 02:12:18 PM PDT 24
Finished Mar 19 02:17:36 PM PDT 24
Peak memory 255220 kb
Host smart-269669de-223d-44c2-9eb4-470c5d058a1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519519688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1519519688
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3485331691
Short name T612
Test name
Test status
Simulation time 286937600 ps
CPU time 30.93 seconds
Started Mar 19 02:12:18 PM PDT 24
Finished Mar 19 02:12:49 PM PDT 24
Peak memory 248804 kb
Host smart-dc9ed32c-366e-4e61-b75f-91764065662e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34853
31691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3485331691
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3981881356
Short name T370
Test name
Test status
Simulation time 844114596 ps
CPU time 8.49 seconds
Started Mar 19 02:12:01 PM PDT 24
Finished Mar 19 02:12:10 PM PDT 24
Peak memory 251896 kb
Host smart-69b11e86-bbb1-46c3-97fb-2f5f23d2db76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
81356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3981881356
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2473200773
Short name T95
Test name
Test status
Simulation time 3304198693 ps
CPU time 28.19 seconds
Started Mar 19 02:12:04 PM PDT 24
Finished Mar 19 02:12:32 PM PDT 24
Peak memory 247916 kb
Host smart-01c860ab-9ae2-4e22-a4fb-d3da4f4fac0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24732
00773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2473200773
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1021335334
Short name T467
Test name
Test status
Simulation time 948812992 ps
CPU time 43.48 seconds
Started Mar 19 02:12:04 PM PDT 24
Finished Mar 19 02:12:47 PM PDT 24
Peak memory 249092 kb
Host smart-0d091f62-4166-40dc-a60f-4eb6d43dda72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10213
35334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1021335334
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1776032380
Short name T254
Test name
Test status
Simulation time 18900145771 ps
CPU time 2057.49 seconds
Started Mar 19 02:11:23 PM PDT 24
Finished Mar 19 02:45:42 PM PDT 24
Peak memory 300480 kb
Host smart-8d888fbf-6050-4f18-ac6e-94bf5a995fb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776032380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1776032380
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3684931881
Short name T221
Test name
Test status
Simulation time 51499502496 ps
CPU time 2857.55 seconds
Started Mar 19 02:12:09 PM PDT 24
Finished Mar 19 02:59:47 PM PDT 24
Peak memory 287232 kb
Host smart-2969049b-758e-4aa4-8a69-6406c43fe6be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684931881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3684931881
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.915564306
Short name T501
Test name
Test status
Simulation time 14649192851 ps
CPU time 146.48 seconds
Started Mar 19 02:12:06 PM PDT 24
Finished Mar 19 02:14:33 PM PDT 24
Peak memory 257064 kb
Host smart-ed1e5b13-1efe-4ad0-a848-9e6656234135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91556
4306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.915564306
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.606562807
Short name T593
Test name
Test status
Simulation time 222946369 ps
CPU time 20.62 seconds
Started Mar 19 02:12:02 PM PDT 24
Finished Mar 19 02:12:23 PM PDT 24
Peak memory 255576 kb
Host smart-db7eb2fb-4f3b-471b-9db5-2095dd5c248b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60656
2807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.606562807
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3495979794
Short name T670
Test name
Test status
Simulation time 36618986317 ps
CPU time 1071.17 seconds
Started Mar 19 02:12:08 PM PDT 24
Finished Mar 19 02:30:00 PM PDT 24
Peak memory 273516 kb
Host smart-765ea86d-71e6-442f-bacd-52dc39f68a9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495979794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3495979794
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1896173613
Short name T36
Test name
Test status
Simulation time 41999401993 ps
CPU time 1242.44 seconds
Started Mar 19 02:12:16 PM PDT 24
Finished Mar 19 02:32:59 PM PDT 24
Peak memory 284576 kb
Host smart-0dce34dc-97d9-4f5b-92ee-ce384755e944
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896173613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1896173613
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3004250493
Short name T608
Test name
Test status
Simulation time 1813055454 ps
CPU time 63.65 seconds
Started Mar 19 02:11:33 PM PDT 24
Finished Mar 19 02:12:37 PM PDT 24
Peak memory 248776 kb
Host smart-1c2a3284-71a8-49da-9b96-b139656c77a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30042
50493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3004250493
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3005299168
Short name T46
Test name
Test status
Simulation time 166996098 ps
CPU time 16.63 seconds
Started Mar 19 02:12:12 PM PDT 24
Finished Mar 19 02:12:28 PM PDT 24
Peak memory 255592 kb
Host smart-0427e6c2-56a2-4f34-b7ac-af96bd0afcc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30052
99168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3005299168
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2046340202
Short name T680
Test name
Test status
Simulation time 552139709 ps
CPU time 18.93 seconds
Started Mar 19 02:11:56 PM PDT 24
Finished Mar 19 02:12:15 PM PDT 24
Peak memory 249144 kb
Host smart-23592017-2d46-4bdd-998f-4877e72d446b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463
40202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2046340202
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.435226160
Short name T382
Test name
Test status
Simulation time 586209216 ps
CPU time 12.52 seconds
Started Mar 19 02:12:14 PM PDT 24
Finished Mar 19 02:12:27 PM PDT 24
Peak memory 254108 kb
Host smart-d9b29769-6aab-4ce9-a1a6-3940bb925647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43522
6160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.435226160
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2237175853
Short name T285
Test name
Test status
Simulation time 36673777935 ps
CPU time 2513.51 seconds
Started Mar 19 02:12:16 PM PDT 24
Finished Mar 19 02:54:10 PM PDT 24
Peak memory 289560 kb
Host smart-6fcb8c14-49d8-4a87-8811-a31626aa8c47
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237175853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2237175853
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.553822735
Short name T415
Test name
Test status
Simulation time 17331930967 ps
CPU time 1225.45 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:32:53 PM PDT 24
Peak memory 265260 kb
Host smart-cd5bf4b2-e70e-4f41-a1db-7321e84de96c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553822735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.553822735
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1683000350
Short name T392
Test name
Test status
Simulation time 4452881511 ps
CPU time 136.91 seconds
Started Mar 19 02:12:25 PM PDT 24
Finished Mar 19 02:14:43 PM PDT 24
Peak memory 256464 kb
Host smart-1a2a9311-2132-4a50-b8e5-228c5e419dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16830
00350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1683000350
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2191064948
Short name T362
Test name
Test status
Simulation time 27946316 ps
CPU time 3.14 seconds
Started Mar 19 02:12:25 PM PDT 24
Finished Mar 19 02:12:29 PM PDT 24
Peak memory 239236 kb
Host smart-7ee8636a-503b-4d4e-8b02-3d078791b4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21910
64948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2191064948
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1069701860
Short name T333
Test name
Test status
Simulation time 93754223309 ps
CPU time 2102.03 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:47:33 PM PDT 24
Peak memory 284724 kb
Host smart-2cabd1f9-731d-4795-9226-dbe59dcf7163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069701860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1069701860
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1921440335
Short name T581
Test name
Test status
Simulation time 30046889779 ps
CPU time 1979.1 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:45:30 PM PDT 24
Peak memory 285716 kb
Host smart-098f45a0-93f7-4f5b-956b-8bc32a52b7bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921440335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1921440335
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1111106392
Short name T8
Test name
Test status
Simulation time 33159962023 ps
CPU time 343.35 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:18:14 PM PDT 24
Peak memory 247940 kb
Host smart-a2578a3a-1526-46b9-a07c-fa5c1d3d931d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111106392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1111106392
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2326147359
Short name T555
Test name
Test status
Simulation time 1931666121 ps
CPU time 34.02 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:13:01 PM PDT 24
Peak memory 256788 kb
Host smart-611b57e8-31c0-47bd-b2b3-d295727b7cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23261
47359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2326147359
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2109034126
Short name T567
Test name
Test status
Simulation time 61296103 ps
CPU time 5.48 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:12:32 PM PDT 24
Peak memory 239024 kb
Host smart-a1e3f430-296a-42ab-9008-29f269c0aaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
34126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2109034126
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.17017512
Short name T253
Test name
Test status
Simulation time 281844353 ps
CPU time 22.39 seconds
Started Mar 19 02:12:25 PM PDT 24
Finished Mar 19 02:12:48 PM PDT 24
Peak memory 255344 kb
Host smart-9a267af3-9597-4599-ab86-9b776ff6a000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017
512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.17017512
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.168085216
Short name T572
Test name
Test status
Simulation time 1139845877 ps
CPU time 25.43 seconds
Started Mar 19 02:12:27 PM PDT 24
Finished Mar 19 02:12:55 PM PDT 24
Peak memory 255064 kb
Host smart-331d1bcf-92f2-4205-a769-be79b6f81dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
5216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.168085216
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1792725260
Short name T666
Test name
Test status
Simulation time 5742865581 ps
CPU time 315.56 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:17:46 PM PDT 24
Peak memory 253340 kb
Host smart-76ec9192-43e2-4ccf-8a02-8567d11a94b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792725260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1792725260
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1590980042
Short name T61
Test name
Test status
Simulation time 159905219327 ps
CPU time 4428.52 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 03:26:20 PM PDT 24
Peak memory 354100 kb
Host smart-e844b00c-1ac2-4987-a6f6-9fe3d0f4fab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590980042 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1590980042
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.668107266
Short name T63
Test name
Test status
Simulation time 36403152123 ps
CPU time 1030.74 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:29:41 PM PDT 24
Peak memory 268488 kb
Host smart-50713c81-413b-4f16-89c5-7603c089e5a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668107266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.668107266
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2952139154
Short name T595
Test name
Test status
Simulation time 284014112 ps
CPU time 18.76 seconds
Started Mar 19 02:12:30 PM PDT 24
Finished Mar 19 02:12:50 PM PDT 24
Peak memory 248648 kb
Host smart-58e6a307-0e21-4957-8d66-4b1321f80013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29521
39154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2952139154
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.465144036
Short name T115
Test name
Test status
Simulation time 431221302 ps
CPU time 35.39 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:13:04 PM PDT 24
Peak memory 256476 kb
Host smart-fc310797-5059-4659-84de-04ae30de7bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46514
4036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.465144036
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.773907634
Short name T633
Test name
Test status
Simulation time 108609510515 ps
CPU time 1065.44 seconds
Started Mar 19 02:12:32 PM PDT 24
Finished Mar 19 02:30:18 PM PDT 24
Peak memory 268380 kb
Host smart-7c9eec90-1f34-471e-b5aa-b9455c5f6e8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773907634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.773907634
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2887910535
Short name T380
Test name
Test status
Simulation time 71772525393 ps
CPU time 1195.07 seconds
Started Mar 19 02:12:32 PM PDT 24
Finished Mar 19 02:32:27 PM PDT 24
Peak memory 272300 kb
Host smart-b97d76cf-c91a-4482-9e5b-230f56c4fd09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887910535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2887910535
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3669086499
Short name T491
Test name
Test status
Simulation time 60567284486 ps
CPU time 514.39 seconds
Started Mar 19 02:12:30 PM PDT 24
Finished Mar 19 02:21:06 PM PDT 24
Peak memory 248244 kb
Host smart-2c6a496f-08fe-4c60-8897-8cd4cfe0c1b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669086499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3669086499
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4119184276
Short name T598
Test name
Test status
Simulation time 142834874 ps
CPU time 16.67 seconds
Started Mar 19 02:12:27 PM PDT 24
Finished Mar 19 02:12:46 PM PDT 24
Peak memory 248968 kb
Host smart-3c70675b-7d27-4c7c-b5d5-25e5644a4853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41191
84276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4119184276
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.367238252
Short name T627
Test name
Test status
Simulation time 551258417 ps
CPU time 43.99 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:13:14 PM PDT 24
Peak memory 255568 kb
Host smart-2c181196-687c-41d2-80ec-807d36e6a3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36723
8252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.367238252
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4096912827
Short name T410
Test name
Test status
Simulation time 233547089 ps
CPU time 18.15 seconds
Started Mar 19 02:12:32 PM PDT 24
Finished Mar 19 02:12:50 PM PDT 24
Peak memory 248860 kb
Host smart-d7346548-961c-4bf2-8d90-81f62628fb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40969
12827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4096912827
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3682850565
Short name T442
Test name
Test status
Simulation time 8213365047 ps
CPU time 69.29 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:13:36 PM PDT 24
Peak memory 248884 kb
Host smart-0d840259-daa5-4072-b00f-3b675de0d709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36828
50565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3682850565
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.4229860465
Short name T486
Test name
Test status
Simulation time 411673273052 ps
CPU time 2055.45 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:46:45 PM PDT 24
Peak memory 273492 kb
Host smart-dcbfce20-4038-4c4e-a29b-6def71791ef6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229860465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.4229860465
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1161707733
Short name T248
Test name
Test status
Simulation time 22321051757 ps
CPU time 1537.81 seconds
Started Mar 19 02:12:31 PM PDT 24
Finished Mar 19 02:38:10 PM PDT 24
Peak memory 272428 kb
Host smart-4007ee28-54dd-4e14-b672-c5919114ef9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161707733 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1161707733
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1203134418
Short name T649
Test name
Test status
Simulation time 36205560570 ps
CPU time 2166.59 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:48:38 PM PDT 24
Peak memory 286856 kb
Host smart-d4406eb3-534f-443a-a42d-f1c6b9e92da4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203134418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1203134418
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2326903129
Short name T99
Test name
Test status
Simulation time 11352836200 ps
CPU time 161.49 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:15:11 PM PDT 24
Peak memory 257116 kb
Host smart-d4c5e609-828d-46f7-ba8d-b5f993fa927a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
03129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2326903129
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3288303226
Short name T352
Test name
Test status
Simulation time 276210724 ps
CPU time 17.52 seconds
Started Mar 19 02:12:27 PM PDT 24
Finished Mar 19 02:12:45 PM PDT 24
Peak memory 253040 kb
Host smart-becb67a8-23d6-4792-bf67-bb8050099157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32883
03226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3288303226
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2365491430
Short name T402
Test name
Test status
Simulation time 34799990275 ps
CPU time 2480.76 seconds
Started Mar 19 02:12:33 PM PDT 24
Finished Mar 19 02:53:54 PM PDT 24
Peak memory 289292 kb
Host smart-f288e066-a07e-4aa6-8eb4-6f191bcd3a41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365491430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2365491430
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2590848692
Short name T602
Test name
Test status
Simulation time 5463170110 ps
CPU time 231.68 seconds
Started Mar 19 02:12:32 PM PDT 24
Finished Mar 19 02:16:24 PM PDT 24
Peak memory 247828 kb
Host smart-eeb18c04-60ba-454d-a003-588d6538afcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590848692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2590848692
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3467260314
Short name T379
Test name
Test status
Simulation time 3712839689 ps
CPU time 36.55 seconds
Started Mar 19 02:12:25 PM PDT 24
Finished Mar 19 02:13:02 PM PDT 24
Peak memory 248952 kb
Host smart-919c79ee-db56-4916-989f-e194f60a9537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34672
60314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3467260314
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.639363392
Short name T106
Test name
Test status
Simulation time 957350824 ps
CPU time 51.75 seconds
Started Mar 19 02:12:30 PM PDT 24
Finished Mar 19 02:13:23 PM PDT 24
Peak memory 247628 kb
Host smart-58d4922c-756b-4265-9b81-3778d5332578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63936
3392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.639363392
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1754778679
Short name T128
Test name
Test status
Simulation time 691968882 ps
CPU time 25.17 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:12:56 PM PDT 24
Peak memory 247448 kb
Host smart-2f05cde4-b440-464e-a6cd-f73125234530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17547
78679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1754778679
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2058225579
Short name T459
Test name
Test status
Simulation time 239681593 ps
CPU time 15.9 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:12:43 PM PDT 24
Peak memory 248928 kb
Host smart-37e9bf07-6c4f-4932-ac4d-d3e2198ac239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
25579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2058225579
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1923139937
Short name T86
Test name
Test status
Simulation time 84469178921 ps
CPU time 2428.36 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:52:58 PM PDT 24
Peak memory 289848 kb
Host smart-76ba4653-fbce-4f48-92e9-e18908e9507d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923139937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1923139937
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3472127158
Short name T85
Test name
Test status
Simulation time 78220474123 ps
CPU time 2756.7 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:58:27 PM PDT 24
Peak memory 289604 kb
Host smart-45f6e7db-6336-44ac-9b3e-37eb2edd83da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472127158 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3472127158
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2989314865
Short name T287
Test name
Test status
Simulation time 28203255764 ps
CPU time 1500.19 seconds
Started Mar 19 02:12:29 PM PDT 24
Finished Mar 19 02:37:31 PM PDT 24
Peak memory 272840 kb
Host smart-9f4db55d-fc59-4c94-8857-b541725e0a07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989314865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2989314865
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2131394148
Short name T642
Test name
Test status
Simulation time 6923364264 ps
CPU time 232.45 seconds
Started Mar 19 02:12:31 PM PDT 24
Finished Mar 19 02:16:24 PM PDT 24
Peak memory 250384 kb
Host smart-49460acf-06cf-4b54-a726-47ee82009b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21313
94148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2131394148
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.909099297
Short name T485
Test name
Test status
Simulation time 1016439083 ps
CPU time 74.07 seconds
Started Mar 19 02:12:31 PM PDT 24
Finished Mar 19 02:13:46 PM PDT 24
Peak memory 247744 kb
Host smart-4e66ced0-9809-43bf-b26d-c9807c217738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90909
9297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.909099297
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2697510494
Short name T328
Test name
Test status
Simulation time 41573369054 ps
CPU time 2581.36 seconds
Started Mar 19 02:12:28 PM PDT 24
Finished Mar 19 02:55:31 PM PDT 24
Peak memory 289268 kb
Host smart-43537671-0b8e-49f4-8d04-15254c4555d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697510494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2697510494
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1025012762
Short name T662
Test name
Test status
Simulation time 159958784317 ps
CPU time 2571.85 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:55:19 PM PDT 24
Peak memory 273468 kb
Host smart-79852a8a-543e-4343-aa9d-ff1d15f203e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025012762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1025012762
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2763026089
Short name T319
Test name
Test status
Simulation time 12561228582 ps
CPU time 277.18 seconds
Started Mar 19 02:12:30 PM PDT 24
Finished Mar 19 02:17:09 PM PDT 24
Peak memory 248240 kb
Host smart-91e3d3ec-eb75-4c44-919d-5dda68e6b0ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763026089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2763026089
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3239550362
Short name T429
Test name
Test status
Simulation time 3945071348 ps
CPU time 60.92 seconds
Started Mar 19 02:12:27 PM PDT 24
Finished Mar 19 02:13:29 PM PDT 24
Peak memory 256464 kb
Host smart-00fb6dac-6c7a-4646-bfd0-ac1ed14735f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32395
50362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3239550362
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3851700808
Short name T690
Test name
Test status
Simulation time 906880202 ps
CPU time 10.37 seconds
Started Mar 19 02:12:33 PM PDT 24
Finished Mar 19 02:12:44 PM PDT 24
Peak memory 255256 kb
Host smart-d302a13e-1b33-46a9-bba7-aeb7e51dc4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
00808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3851700808
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.835883566
Short name T267
Test name
Test status
Simulation time 3900070569 ps
CPU time 73.94 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:13:41 PM PDT 24
Peak memory 255596 kb
Host smart-64ee622d-54de-4f52-9ddc-7964017363e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83588
3566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.835883566
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1326202555
Short name T71
Test name
Test status
Simulation time 452382300 ps
CPU time 46.77 seconds
Started Mar 19 02:12:26 PM PDT 24
Finished Mar 19 02:13:14 PM PDT 24
Peak memory 249136 kb
Host smart-5ef130ce-4095-4c0d-846c-b6a9e362d5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13262
02555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1326202555
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.254379252
Short name T239
Test name
Test status
Simulation time 90398256 ps
CPU time 2.59 seconds
Started Mar 19 02:02:06 PM PDT 24
Finished Mar 19 02:02:08 PM PDT 24
Peak memory 249072 kb
Host smart-f9df3bf6-09a9-4083-a304-9c96dcfaff89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=254379252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.254379252
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4037101401
Short name T623
Test name
Test status
Simulation time 56998831301 ps
CPU time 2394.06 seconds
Started Mar 19 02:02:13 PM PDT 24
Finished Mar 19 02:42:07 PM PDT 24
Peak memory 289704 kb
Host smart-f0409edc-4a47-4998-8feb-3226638cbf04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037101401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4037101401
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1125889645
Short name T664
Test name
Test status
Simulation time 199076918 ps
CPU time 10.08 seconds
Started Mar 19 02:02:12 PM PDT 24
Finished Mar 19 02:02:22 PM PDT 24
Peak memory 240620 kb
Host smart-be49fb07-0878-4f04-93cd-a5af3b181402
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1125889645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1125889645
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3678537967
Short name T711
Test name
Test status
Simulation time 4283725887 ps
CPU time 142.92 seconds
Started Mar 19 02:02:36 PM PDT 24
Finished Mar 19 02:04:59 PM PDT 24
Peak memory 257028 kb
Host smart-c6467c0e-388d-459f-8410-33df5b3affaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36785
37967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3678537967
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.147068653
Short name T471
Test name
Test status
Simulation time 308363615 ps
CPU time 22.18 seconds
Started Mar 19 02:02:05 PM PDT 24
Finished Mar 19 02:02:27 PM PDT 24
Peak memory 254412 kb
Host smart-d8a5cbd0-49b2-439f-90e4-b63bd20f62e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14706
8653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.147068653
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.934767950
Short name T201
Test name
Test status
Simulation time 23283488044 ps
CPU time 1541.26 seconds
Started Mar 19 02:02:25 PM PDT 24
Finished Mar 19 02:28:06 PM PDT 24
Peak memory 271736 kb
Host smart-91531aff-504d-4429-b8ab-c248daa55d1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934767950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.934767950
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2575745230
Short name T311
Test name
Test status
Simulation time 7994095802 ps
CPU time 87.99 seconds
Started Mar 19 02:02:41 PM PDT 24
Finished Mar 19 02:04:10 PM PDT 24
Peak memory 248004 kb
Host smart-acfdeb26-0d14-4068-ab2a-c4c5b6249c65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575745230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2575745230
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2882319792
Short name T568
Test name
Test status
Simulation time 486430073 ps
CPU time 27.77 seconds
Started Mar 19 02:02:30 PM PDT 24
Finished Mar 19 02:02:58 PM PDT 24
Peak memory 255492 kb
Host smart-924ea61c-0f29-4b59-b26f-7bc3f50b3f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
19792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2882319792
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1570165361
Short name T476
Test name
Test status
Simulation time 832154661 ps
CPU time 27.68 seconds
Started Mar 19 02:02:10 PM PDT 24
Finished Mar 19 02:02:37 PM PDT 24
Peak memory 248500 kb
Host smart-2027c5fa-4191-4609-ab62-fe3c30238b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15701
65361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1570165361
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.768407065
Short name T360
Test name
Test status
Simulation time 223476604 ps
CPU time 5.88 seconds
Started Mar 19 02:02:08 PM PDT 24
Finished Mar 19 02:02:15 PM PDT 24
Peak memory 238972 kb
Host smart-d09fceda-faa0-4efe-89c4-8f2e62e6b668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76840
7065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.768407065
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3201665289
Short name T591
Test name
Test status
Simulation time 178006332 ps
CPU time 6.55 seconds
Started Mar 19 02:02:08 PM PDT 24
Finished Mar 19 02:02:15 PM PDT 24
Peak memory 252052 kb
Host smart-b81df35a-224f-4f7d-b2d3-f6625194784e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016
65289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3201665289
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3457086290
Short name T529
Test name
Test status
Simulation time 76449721668 ps
CPU time 3348.89 seconds
Started Mar 19 02:02:19 PM PDT 24
Finished Mar 19 02:58:09 PM PDT 24
Peak memory 314356 kb
Host smart-34347929-28ac-4f42-a4c9-c4a512efc698
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457086290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3457086290
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1428541499
Short name T235
Test name
Test status
Simulation time 23897090 ps
CPU time 2.57 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:03:04 PM PDT 24
Peak memory 249016 kb
Host smart-cc48fb25-d1c0-49b9-a3af-79d1ddd818f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1428541499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1428541499
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1460354938
Short name T579
Test name
Test status
Simulation time 584630003 ps
CPU time 9.32 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:03:10 PM PDT 24
Peak memory 240680 kb
Host smart-7f8851f6-2fd7-423e-9941-38374dc988e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1460354938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1460354938
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3903757991
Short name T396
Test name
Test status
Simulation time 670711915 ps
CPU time 40.01 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:43 PM PDT 24
Peak memory 254688 kb
Host smart-43451d53-0eb5-4112-83a8-121784ef3441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
57991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3903757991
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1146361196
Short name T543
Test name
Test status
Simulation time 67019577 ps
CPU time 5.15 seconds
Started Mar 19 02:02:56 PM PDT 24
Finished Mar 19 02:03:02 PM PDT 24
Peak memory 250732 kb
Host smart-4d2ba62f-1115-4662-aa0f-6f15fd8ea175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
61196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1146361196
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1954553879
Short name T502
Test name
Test status
Simulation time 113180844388 ps
CPU time 1497.79 seconds
Started Mar 19 02:02:58 PM PDT 24
Finished Mar 19 02:27:59 PM PDT 24
Peak memory 265236 kb
Host smart-1f55d95a-5448-4414-affc-586b9e2b9542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954553879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1954553879
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3752435272
Short name T286
Test name
Test status
Simulation time 21116101772 ps
CPU time 1243.73 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:23:46 PM PDT 24
Peak memory 288964 kb
Host smart-5e048c90-500a-4eb4-9f7d-86410ec3abd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752435272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3752435272
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4221779718
Short name T300
Test name
Test status
Simulation time 8449515450 ps
CPU time 345.2 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:08:47 PM PDT 24
Peak memory 248076 kb
Host smart-c37de4b3-e898-442d-8092-4c4f01715f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221779718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4221779718
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1872109250
Short name T436
Test name
Test status
Simulation time 251752803 ps
CPU time 7.89 seconds
Started Mar 19 02:02:38 PM PDT 24
Finished Mar 19 02:02:46 PM PDT 24
Peak memory 254716 kb
Host smart-2b9db794-07fe-4ed7-9718-1f8a174efbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18721
09250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1872109250
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2021927383
Short name T361
Test name
Test status
Simulation time 2788013784 ps
CPU time 50.81 seconds
Started Mar 19 02:02:41 PM PDT 24
Finished Mar 19 02:03:32 PM PDT 24
Peak memory 256080 kb
Host smart-895a071a-d0c6-40c7-be21-9e4ef1ede7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20219
27383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2021927383
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.898940831
Short name T650
Test name
Test status
Simulation time 3231335958 ps
CPU time 52.87 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:03:53 PM PDT 24
Peak memory 256176 kb
Host smart-82967cdb-e57e-4a48-9ac2-e0184637e2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89894
0831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.898940831
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2173402487
Short name T18
Test name
Test status
Simulation time 1262126007 ps
CPU time 47.11 seconds
Started Mar 19 02:02:12 PM PDT 24
Finished Mar 19 02:02:59 PM PDT 24
Peak memory 256060 kb
Host smart-5fdfad1c-de82-4bc8-94ef-444247c600e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21734
02487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2173402487
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3793442434
Short name T119
Test name
Test status
Simulation time 43671671830 ps
CPU time 2987.54 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:52:50 PM PDT 24
Peak memory 289456 kb
Host smart-737b202b-07d5-4c44-968a-6a50ba53f026
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793442434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3793442434
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4153520410
Short name T80
Test name
Test status
Simulation time 22808764 ps
CPU time 2.71 seconds
Started Mar 19 02:03:04 PM PDT 24
Finished Mar 19 02:03:09 PM PDT 24
Peak memory 249124 kb
Host smart-442c88cb-4891-445a-90d0-5050616c12bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4153520410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4153520410
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3458148094
Short name T707
Test name
Test status
Simulation time 47747332144 ps
CPU time 2800.76 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:49:44 PM PDT 24
Peak memory 289468 kb
Host smart-e0d2b839-98d2-4297-a8dc-d6709bb03a4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458148094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3458148094
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3963451313
Short name T614
Test name
Test status
Simulation time 1091926596 ps
CPU time 26.85 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:30 PM PDT 24
Peak memory 248864 kb
Host smart-8298b38d-3675-4bef-a439-69529aacc7b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3963451313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3963451313
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.266233409
Short name T428
Test name
Test status
Simulation time 84174534 ps
CPU time 8.56 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:03:09 PM PDT 24
Peak memory 254116 kb
Host smart-b91a3013-d88c-4384-a435-02e79e4fb810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26623
3409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.266233409
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.122284336
Short name T495
Test name
Test status
Simulation time 818062935 ps
CPU time 51.6 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:54 PM PDT 24
Peak memory 248872 kb
Host smart-c67ebca3-ad43-4db5-b592-dbb38cbe060b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12228
4336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.122284336
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1292487063
Short name T6
Test name
Test status
Simulation time 37445807245 ps
CPU time 2081.25 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:37:44 PM PDT 24
Peak memory 289720 kb
Host smart-d1c402d5-5af3-4102-a890-f3bee4747093
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292487063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1292487063
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.777421429
Short name T687
Test name
Test status
Simulation time 8610707211 ps
CPU time 777.54 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:16:00 PM PDT 24
Peak memory 270444 kb
Host smart-f42f61b5-0e6d-4e7d-9ffe-ce081e7774eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777421429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.777421429
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3391259773
Short name T73
Test name
Test status
Simulation time 6930702462 ps
CPU time 316.1 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:08:19 PM PDT 24
Peak memory 247928 kb
Host smart-5ea08150-187f-4286-abb8-8332e1206212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391259773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3391259773
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3105988180
Short name T418
Test name
Test status
Simulation time 678348618 ps
CPU time 7.57 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:03:10 PM PDT 24
Peak memory 240608 kb
Host smart-0ff6c770-61b6-4fc4-ba52-2d456a4a6529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31059
88180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3105988180
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1057166734
Short name T531
Test name
Test status
Simulation time 322833649 ps
CPU time 31.68 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:35 PM PDT 24
Peak memory 256032 kb
Host smart-961901cb-de98-40cf-903a-f0d49b78516f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10571
66734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1057166734
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3135722332
Short name T50
Test name
Test status
Simulation time 136854444 ps
CPU time 12.11 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:15 PM PDT 24
Peak memory 251836 kb
Host smart-0111339d-d0d0-4241-8327-f6148922559f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
22332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3135722332
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2995316675
Short name T694
Test name
Test status
Simulation time 70173676 ps
CPU time 5.97 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:08 PM PDT 24
Peak memory 254152 kb
Host smart-9fe0b21d-9848-488c-a9af-1aacf89f83b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29953
16675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2995316675
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2573014771
Short name T440
Test name
Test status
Simulation time 3109747325 ps
CPU time 195.24 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:06:18 PM PDT 24
Peak memory 250000 kb
Host smart-e024dab4-5899-44db-a7ef-a10713198564
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573014771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2573014771
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.424408139
Short name T236
Test name
Test status
Simulation time 185001897 ps
CPU time 4.17 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:03:06 PM PDT 24
Peak memory 249104 kb
Host smart-9544da7d-5ec8-419c-a4cd-add97dff5810
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=424408139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.424408139
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1747640224
Short name T684
Test name
Test status
Simulation time 7895366901 ps
CPU time 880.74 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:17:43 PM PDT 24
Peak memory 269688 kb
Host smart-361f15b4-31ab-4bfa-a760-6ba53c811a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747640224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1747640224
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2437883526
Short name T365
Test name
Test status
Simulation time 1153161280 ps
CPU time 106.37 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:04:49 PM PDT 24
Peak memory 249888 kb
Host smart-327e7dac-dd96-4206-8dde-3787a4480901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24378
83526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2437883526
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1320889054
Short name T573
Test name
Test status
Simulation time 810307864 ps
CPU time 15.41 seconds
Started Mar 19 02:02:57 PM PDT 24
Finished Mar 19 02:03:16 PM PDT 24
Peak memory 255208 kb
Host smart-96603be4-5156-4eca-bb17-3680529a740c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13208
89054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1320889054
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2417637414
Short name T710
Test name
Test status
Simulation time 44756016140 ps
CPU time 2558.53 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:45:41 PM PDT 24
Peak memory 281720 kb
Host smart-4ecb1b81-2f81-4df7-b2f3-78269e1bb91e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417637414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2417637414
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3606173292
Short name T586
Test name
Test status
Simulation time 46097153367 ps
CPU time 1294.46 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:24:36 PM PDT 24
Peak memory 289212 kb
Host smart-be59af50-8118-45dd-bd24-85ebb66cf663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606173292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3606173292
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.227335454
Short name T218
Test name
Test status
Simulation time 30556383176 ps
CPU time 332.9 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:08:34 PM PDT 24
Peak memory 248112 kb
Host smart-bbf5a4d0-dccd-4d2e-afb7-7559ae82e240
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227335454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.227335454
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3504547615
Short name T477
Test name
Test status
Simulation time 1313776581 ps
CPU time 42.32 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:45 PM PDT 24
Peak memory 249204 kb
Host smart-37c305db-0711-4482-8e1a-0a3d5c74c60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
47615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3504547615
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1839348307
Short name T425
Test name
Test status
Simulation time 6142884551 ps
CPU time 55.71 seconds
Started Mar 19 02:02:59 PM PDT 24
Finished Mar 19 02:03:57 PM PDT 24
Peak memory 248908 kb
Host smart-984152b2-7e66-412c-98ee-0e288b828b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18393
48307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1839348307
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.893146460
Short name T258
Test name
Test status
Simulation time 157676009 ps
CPU time 11.24 seconds
Started Mar 19 02:02:58 PM PDT 24
Finished Mar 19 02:03:12 PM PDT 24
Peak memory 254236 kb
Host smart-a5c574a3-2474-4d8d-9e9f-a105fb00ec2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89314
6460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.893146460
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1358725874
Short name T580
Test name
Test status
Simulation time 161025647 ps
CPU time 10.72 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:13 PM PDT 24
Peak memory 257028 kb
Host smart-9bf6bd02-6122-4cba-9d91-a09e74a2ce99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587
25874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1358725874
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2265582445
Short name T532
Test name
Test status
Simulation time 42804106459 ps
CPU time 2043.21 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:37:06 PM PDT 24
Peak memory 289072 kb
Host smart-890f7dbd-1216-42a1-95f9-f8f5cc7ae8c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265582445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2265582445
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3288088992
Short name T227
Test name
Test status
Simulation time 14817073 ps
CPU time 2.44 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:03:13 PM PDT 24
Peak memory 249104 kb
Host smart-2afb8d8b-17b3-49e5-9665-d4d0ea2acf7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3288088992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3288088992
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1480094503
Short name T409
Test name
Test status
Simulation time 165594433455 ps
CPU time 2722.43 seconds
Started Mar 19 02:03:00 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 289236 kb
Host smart-5cc3f2c4-d59a-4f3e-8003-dcf40db2f116
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480094503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1480094503
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1023881917
Short name T463
Test name
Test status
Simulation time 559871619 ps
CPU time 15.24 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:18 PM PDT 24
Peak memory 240660 kb
Host smart-bbb11d31-008e-4dfd-b7ac-620f5bf465f6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1023881917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1023881917
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3393730788
Short name T372
Test name
Test status
Simulation time 3146833003 ps
CPU time 147.17 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:05:30 PM PDT 24
Peak memory 251020 kb
Host smart-49fe1d59-a61e-4846-a856-de06bdba7862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33937
30788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3393730788
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2544664191
Short name T40
Test name
Test status
Simulation time 289848113 ps
CPU time 17.8 seconds
Started Mar 19 02:03:03 PM PDT 24
Finished Mar 19 02:03:21 PM PDT 24
Peak memory 249348 kb
Host smart-1a0cc24d-817a-4b4f-b84b-036fd89d146b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
64191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2544664191
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2521493158
Short name T304
Test name
Test status
Simulation time 59376591493 ps
CPU time 3438.4 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 03:00:29 PM PDT 24
Peak memory 289004 kb
Host smart-907e35ab-861e-4e1d-a128-7e88e4997df6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521493158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2521493158
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2528089855
Short name T504
Test name
Test status
Simulation time 30651922914 ps
CPU time 1174.24 seconds
Started Mar 19 02:03:10 PM PDT 24
Finished Mar 19 02:22:45 PM PDT 24
Peak memory 272512 kb
Host smart-de44390a-3117-4bb9-ac5f-429c18d1403f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528089855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2528089855
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.98073710
Short name T445
Test name
Test status
Simulation time 54619564964 ps
CPU time 248.74 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:07:12 PM PDT 24
Peak memory 248064 kb
Host smart-0733ed07-2ee4-4ac3-af01-615cf1f7f213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98073710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.98073710
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3121158328
Short name T639
Test name
Test status
Simulation time 130749676 ps
CPU time 10.33 seconds
Started Mar 19 02:04:52 PM PDT 24
Finished Mar 19 02:05:02 PM PDT 24
Peak memory 252108 kb
Host smart-b803453d-3447-4242-83ee-e18e29595c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31211
58328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3121158328
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.402445552
Short name T411
Test name
Test status
Simulation time 2188917335 ps
CPU time 36.49 seconds
Started Mar 19 02:03:04 PM PDT 24
Finished Mar 19 02:03:41 PM PDT 24
Peak memory 247568 kb
Host smart-9e9eec97-8911-4727-b4cb-92cc264f5882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40244
5552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.402445552
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2658442585
Short name T500
Test name
Test status
Simulation time 3873066273 ps
CPU time 50.92 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:03:54 PM PDT 24
Peak memory 249260 kb
Host smart-1f7df108-ea7e-4966-851c-9d94712f067a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26584
42585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2658442585
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1330001945
Short name T75
Test name
Test status
Simulation time 219989121 ps
CPU time 13.79 seconds
Started Mar 19 02:03:02 PM PDT 24
Finished Mar 19 02:03:17 PM PDT 24
Peak memory 248864 kb
Host smart-1842a07f-06fb-4a38-a03b-1bea9bc41101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13300
01945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1330001945
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1835375146
Short name T214
Test name
Test status
Simulation time 630832816 ps
CPU time 53.98 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:03:57 PM PDT 24
Peak memory 248872 kb
Host smart-000a8aa0-9ae7-49a6-b795-958c44f50944
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835375146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1835375146
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4231192927
Short name T638
Test name
Test status
Simulation time 75754707716 ps
CPU time 1567.05 seconds
Started Mar 19 02:03:01 PM PDT 24
Finished Mar 19 02:29:10 PM PDT 24
Peak memory 289952 kb
Host smart-d4ddffa8-3285-4061-a079-e362630ce524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231192927 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4231192927
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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