Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77756	1			T5	9		T19	73		T45	189
class_i[0x1]	36869	1			T5	7		T19	467		T24	3
class_i[0x2]	86376	1			T5	1		T9	12		T45	69
class_i[0x3]	47380	1			T1	3		T5	5		T24	5

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62824	1			T5	9		T9	4		T19	36
alert[0x1]	65168	1			T5	1		T9	2		T19	446
alert[0x2]	59391	1			T1	1		T5	3		T9	3
alert[0x3]	60998	1			T1	2		T5	9		T9	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

248095

1

T1

3

T5

22

T9

8

esc_ping_fail

286

1

T9

4

T12

6

T13

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62740	1			T5	9		T9	3		T19	36
esc_integrity_fail	alert[0x1]	65095	1			T5	1		T9	1		T19	446
esc_integrity_fail	alert[0x2]	59327	1			T1	1		T5	3		T9	2
esc_integrity_fail	alert[0x3]	60933	1			T1	2		T5	9		T9	2
esc_ping_fail	alert[0x0]	84	1			T9	1		T12	1		T13	1
esc_ping_fail	alert[0x1]	73	1			T9	1		T12	2		T13	1
esc_ping_fail	alert[0x2]	64	1			T9	1		T12	1		T295	1
esc_ping_fail	alert[0x3]	65	1			T9	1		T12	2		T13	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	77664	1			T5	9		T19	73		T45	189
esc_integrity_fail	class_i[0x1]	36761	1			T5	7		T19	467		T24	3
esc_integrity_fail	class_i[0x2]	86316	1			T5	1		T9	8		T45	69
esc_integrity_fail	class_i[0x3]	47354	1			T1	3		T5	5		T24	5
esc_ping_fail	class_i[0x0]	92	1			T12	5		T13	3		T31	7
esc_ping_fail	class_i[0x1]	108	1			T295	5		T294	1		T307	1
esc_ping_fail	class_i[0x2]	60	1			T9	4		T12	1		T321	6
esc_ping_fail	class_i[0x3]	26	1			T294	4		T299	12		T298	2