Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	702342450	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	702342450	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	702342450	702154202	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	702342450	702154202	0	0
tb.dut.EdnKnownO_A	0	0	702342450	702154202	0	0
tb.dut.EscPKnownO_A	0	0	702342450	702154202	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	702342450	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	702342450	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	702342450	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	702342450	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	702342450	90	0	0
tb.dut.IrqAKnownO_A	0	0	702342450	702154202	0	0
tb.dut.IrqBKnownO_A	0	0	702342450	702154202	0	0
tb.dut.IrqCKnownO_A	0	0	702342450	702154202	0	0
tb.dut.IrqDKnownO_A	0	0	702342450	702154202	0	0
tb.dut.TlAReadyKnownO_A	0	0	702342450	702154202	0	0
tb.dut.TlDValidKnownO_A	0	0	702342450	702154202	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	728260726	3077587	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	728260726	14770	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	728260726	15053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	728260726	14920	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	728260726	15921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	728260726	16278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	728260726	16433	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	728260726	16063	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	728260726	19612	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	728260726	17304	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	728260726	13699	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	728260726	17248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	728260726	14948	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	728260726	15829	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	728260726	17160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	728260726	17097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	728260726	13519	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	728260726	15984	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	728260726	17166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	728260726	19139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	728260726	16002	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	728260726	18437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	728260726	15119	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	728260726	18309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	728260726	14221	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	728260726	16361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	728260726	14971	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	728260726	14927	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	728260726	14670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	728260726	16349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	728260726	15177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	728260726	17118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	728260726	14737	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	728260726	15224	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	728260726	14015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	728260726	15218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	728260726	14780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	728260726	16357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	728260726	13771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	728260726	16357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	728260726	16035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	728260726	17492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	728260726	18267	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	728260726	15940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	728260726	15159	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	728260726	17417	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	728260726	15041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	728260726	15008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	728260726	14666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	728260726	16726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	728260726	13880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	728260726	13760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	728260726	17377	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	728260726	17916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	728260726	15120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	728260726	13683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	728260726	15018	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	728260726	18156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	728260726	15037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	728260726	16866	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	728260726	15320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	728260726	17455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	728260726	17318	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	728260726	16072	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	728260726	15181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	728260726	17425	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	728260726	16021	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	728260726	15250	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	728260726	15980	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	728260726	13645	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	728260726	28460	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	728260726	15227	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	728260726	16110	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	728260726	13985	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	728260726	13967	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	728260726	14986	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	728260726	18678	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	728260726	16010	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	728260726	16840	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	702342450	1057	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	702342450	206659	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	702342450	380504481	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	702342450	332	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	702342450	809	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	702342450	39	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	702342450	398	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	702003349	302557515	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	702342450	901	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	702342450	881	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	702342450	860	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	702342450	833	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	702342450	914	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	702342450	104668	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	702342450	804	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	702342450	70	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	702342450	1704	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	702342450	1434	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	702342450	702154202	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	702342450	3502	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	702342450	179342	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	702342450	360968169	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	702342450	264	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	702342450	500	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	702342450	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	702342450	212	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	702003349	267398253	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	702342450	564	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	702342450	555	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	702342450	546	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	702342450	540	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	702342450	878	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	702342450	94540	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	702342450	804	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	702342450	57	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	702342450	1696	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	702342450	1426	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	702342450	702154202	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	702342450	5426	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	702342450	165648	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	702342450	400071777	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	702342450	360	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	702342450	498	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	702342450	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	702342450	224	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	702003349	318046848	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	702342450	583	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	702342450	575	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	702342450	568	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	702342450	559	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	702342450	949	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	702342450	101108	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	702342450	854	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	702342450	71	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	702342450	1703	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	702342450	1433	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	702342450	702154202	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	702342450	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	702342450	2498	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	702342450	158485	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	702342450	394807264	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	702342450	350	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	702342450	495	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	702342450	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	702342450	232	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	702003349	320746987	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	702342450	569	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	702342450	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	702342450	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	702342450	541	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	702342450	1622	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	702342450	193409	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	702342450	1539	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	702342450	67	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	702342450	1678	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	702342450	1408	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	702342450	702154202	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	728260726	129924747	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	728260726	727578984	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	728260726	727578984	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	728260726	178923170	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	728260726	727578984	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	728260726	727578984	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	827	827	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	827	827	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	827	827	0	0
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