Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	70	1			T19	1		T24	1		T25	1
class_index[0x1]	57	1			T19	2		T26	2		T75	1
class_index[0x2]	71	1			T25	1		T26	2		T75	1
class_index[0x3]	67	1			T1	1		T19	3		T26	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	95	1			T1	1		T19	1		T24	1
intr_timeout_cnt[1]	59	1			T19	2		T26	2		T73	1
intr_timeout_cnt[2]	28	1			T19	2		T75	1		T79	1
intr_timeout_cnt[3]	21	1			T87	1		T88	1		T274	1
intr_timeout_cnt[4]	16	1			T261	1		T103	1		T275	2
intr_timeout_cnt[5]	15	1			T19	1		T75	1		T48	1
intr_timeout_cnt[6]	7	1			T25	1		T75	1		T48	1
intr_timeout_cnt[7]	7	1			T25	1		T79	1		T30	1
intr_timeout_cnt[8]	10	1			T75	1		T81	1		T261	1
intr_timeout_cnt[9]	7	1			T276	1		T103	2		T277	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T19	1		T24	1		T73	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T73	1		T86	1		T88	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T278	1		T274	1		T174	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T97	1		T57	1		T279	1
class_index[0x0]	intr_timeout_cnt[4]	1	1			T280	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T25	1		T88	1		T281	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T30	1		T57	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T75	1		T282	1		T277	1
class_index[0x0]	intr_timeout_cnt[9]	4	1			T276	1		T103	2		T58	1
class_index[0x1]	intr_timeout_cnt[0]	18	1			T26	2		T88	1		T106	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T19	1		T48	1		T83	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T19	1		T29	2		T82	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T87	1		T174	1		T283	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T103	1		T58	1		T280	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T75	1		T103	1		T284	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T56	1		T277	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T51	1		T285	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T277	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	19	1			T26	1		T28	1		T47	2
class_index[0x2]	intr_timeout_cnt[1]	18	1			T26	1		T30	1		T51	1
class_index[0x2]	intr_timeout_cnt[2]	11	1			T75	1		T79	1		T29	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T88	1		T268	1		T97	1
class_index[0x2]	intr_timeout_cnt[4]	7	1			T57	5		T59	1		T101	1
class_index[0x2]	intr_timeout_cnt[5]	5	1			T84	1		T275	1		T57	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T48	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T25	1		T58	1		T286	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T81	1		T261	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T281	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T1	1		T28	1		T110	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T19	1		T26	1		T88	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T19	1		T204	1		T58	1
class_index[0x3]	intr_timeout_cnt[3]	7	1			T274	1		T97	1		T282	2
class_index[0x3]	intr_timeout_cnt[4]	4	1			T261	1		T275	2		T287	1
class_index[0x3]	intr_timeout_cnt[5]	6	1			T19	1		T48	1		T288	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T75	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T79	1		T289	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T57	3		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T57	1		-	-		-	-