Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	346388	1			T1	2432		T2	21		T3	21
all_values[1]	346388	1			T1	2432		T2	21		T3	21
all_values[2]	346388	1			T1	2432		T2	21		T3	21
all_values[3]	346388	1			T1	2432		T2	21		T3	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

690004

1

T1

4854

T2

48

T3

44

auto[1]

695548

1

T1

4874

T2

36

T3

40

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

826091

1

T1

5008

T2

74

T3

44

auto[1]

559461

1

T1

4720

T2

10

T3

40

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99751	1			T1	623		T2	7		T3	4
all_values[0]	auto[0]	auto[1]	71835	1			T1	591		T2	7		T3	4
all_values[0]	auto[1]	auto[0]	102003	1			T1	619		T2	4		T3	7
all_values[0]	auto[1]	auto[1]	72799	1			T1	599		T2	3		T3	6
all_values[1]	auto[0]	auto[0]	104524	1			T1	648		T2	13		T3	3
all_values[1]	auto[0]	auto[1]	68289	1			T1	590		T3	3		T4	384
all_values[1]	auto[1]	auto[0]	105679	1			T1	617		T2	8		T3	8
all_values[1]	auto[1]	auto[1]	67896	1			T1	577		T3	7		T4	363
all_values[2]	auto[0]	auto[0]	102047	1			T1	615		T2	11		T3	8
all_values[2]	auto[0]	auto[1]	70286	1			T1	587		T3	7		T4	366
all_values[2]	auto[1]	auto[0]	103603	1			T1	637		T2	10		T3	3
all_values[2]	auto[1]	auto[1]	70452	1			T1	593		T3	3		T4	330
all_values[3]	auto[0]	auto[0]	103938	1			T1	617		T2	10		T3	8
all_values[3]	auto[0]	auto[1]	69334	1			T1	583		T3	7		T4	375
all_values[3]	auto[1]	auto[0]	104546	1			T1	632		T2	11		T3	3
all_values[3]	auto[1]	auto[1]	68570	1			T1	600		T3	3		T4	373