Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	346388	1			T1	2432		T2	21		T3	21
all_pins[1]	346388	1			T1	2432		T2	21		T3	21
all_pins[2]	346388	1			T1	2432		T2	21		T3	21
all_pins[3]	346388	1			T1	2432		T2	21		T3	21

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1105835	1			T1	7359		T2	81		T3	65
values[0x1]	279717	1			T1	2369		T2	3		T3	19
transitions[0x0=>0x1]	186211	1			T1	1487		T2	3		T3	10
transitions[0x1=>0x0]	186472	1			T1	1488		T2	3		T3	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	273589	1			T1	1833		T2	18		T3	15
all_pins[0]	values[0x1]	72799	1			T1	599		T2	3		T3	6
all_pins[0]	transitions[0x0=>0x1]	72169	1			T1	598		T2	3		T3	5
all_pins[0]	transitions[0x1=>0x0]	68201	1			T1	600		T3	3		T4	373
all_pins[1]	values[0x0]	278492	1			T1	1855		T2	21		T3	14
all_pins[1]	values[0x1]	67896	1			T1	577		T3	7		T4	363
all_pins[1]	transitions[0x0=>0x1]	36978	1			T1	298		T3	2		T4	190
all_pins[1]	transitions[0x1=>0x0]	41881	1			T1	320		T2	3		T3	1
all_pins[2]	values[0x0]	275936	1			T1	1839		T2	21		T3	18
all_pins[2]	values[0x1]	70452	1			T1	593		T3	3		T4	330
all_pins[2]	transitions[0x0=>0x1]	39514	1			T1	296		T3	1		T4	168
all_pins[2]	transitions[0x1=>0x0]	36958	1			T1	280		T3	5		T4	201
all_pins[3]	values[0x0]	277818	1			T1	1832		T2	21		T3	18
all_pins[3]	values[0x1]	68570	1			T1	600		T3	3		T4	373
all_pins[3]	transitions[0x0=>0x1]	37550	1			T1	295		T3	2		T4	213
all_pins[3]	transitions[0x1=>0x0]	39432	1			T1	288		T3	2		T4	170