Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91438	1			T1	522		T4	388		T5	514
accum_cnt_1000	228178	1			T1	618		T4	351		T5	1191
accum_cnt_100	27116	1			T1	115		T4	21		T5	63
accum_cnt_50	63229	1			T1	3079		T2	6		T3	9
accum_cnt_10	172565	1			T1	1621		T2	2		T3	37
accum_cnt_0	409359	1			T1	567		T2	52		T3	18

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256299	1			T1	1719		T2	15		T3	16
class_index[0x1]	256299	1			T1	1719		T2	15		T3	16
class_index[0x2]	256299	1			T1	1719		T2	15		T3	16
class_index[0x3]	256299	1			T1	1719		T2	15		T3	16

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23495	1			T1	522		T8	680		T24	299
class_index[0x0]	accum_cnt_1000	53333	1			T1	518		T8	700		T17	701
class_index[0x0]	accum_cnt_100	6668	1			T1	51		T8	41		T17	155
class_index[0x0]	accum_cnt_50	14990	1			T1	38		T2	6		T3	9
class_index[0x0]	accum_cnt_10	45103	1			T1	63		T2	2		T3	5
class_index[0x0]	accum_cnt_0	103752	1			T1	173		T2	7		T3	2
class_index[0x1]	accum_cnt_2000	24937	1			T5	73		T65	517		T209	697
class_index[0x1]	accum_cnt_1000	64038	1			T1	54		T5	59		T17	708
class_index[0x1]	accum_cnt_100	7361	1			T1	30		T5	2		T17	169
class_index[0x1]	accum_cnt_50	16224	1			T1	1415		T5	6		T27	14
class_index[0x1]	accum_cnt_10	46314	1			T1	20		T3	16		T5	6
class_index[0x1]	accum_cnt_0	90151	1			T1	200		T2	15		T6	27
class_index[0x2]	accum_cnt_2000	20581	1			T5	214		T8	395		T18	360
class_index[0x2]	accum_cnt_1000	51785	1			T1	26		T5	590		T8	368
class_index[0x2]	accum_cnt_100	5669	1			T1	17		T5	30		T8	22
class_index[0x2]	accum_cnt_50	20082	1			T1	1470		T8	20		T27	12
class_index[0x2]	accum_cnt_10	43116	1			T1	51		T3	16		T7	601
class_index[0x2]	accum_cnt_0	105756	1			T1	155		T2	15		T6	27
class_index[0x3]	accum_cnt_2000	22425	1			T4	388		T5	227		T8	535
class_index[0x3]	accum_cnt_1000	59022	1			T1	20		T4	351		T5	542
class_index[0x3]	accum_cnt_100	7418	1			T1	17		T4	21		T5	31
class_index[0x3]	accum_cnt_50	11933	1			T1	156		T4	18		T5	29
class_index[0x3]	accum_cnt_10	38032	1			T1	1487		T4	9		T5	5
class_index[0x3]	accum_cnt_0	109700	1			T1	39		T2	15		T3	16