Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	7790	1			T45	448		T25	148		T62	635
alert[0x1]	5531	1			T9	1		T24	70		T62	147
alert[0x2]	5802	1			T5	41		T9	1		T45	18
alert[0x3]	3053	1			T45	97		T75	4		T28	114
alert[0x4]	9828	1			T5	10		T45	12		T24	19
alert[0x5]	4140	1			T26	1		T62	330		T35	27
alert[0x6]	4509	1			T5	3		T9	1		T45	22
alert[0x7]	2439	1			T45	41		T207	197		T28	7
alert[0x8]	7502	1			T24	116		T62	2337		T294	1
alert[0x9]	9157	1			T5	4210		T24	10		T26	6
alert[0xa]	10870	1			T45	7		T24	1		T62	15
alert[0xb]	11705	1			T5	9		T19	12		T45	2010
alert[0xc]	8408	1			T19	9		T45	8		T24	418
alert[0xd]	4577	1			T9	1		T45	3		T24	144
alert[0xe]	5601	1			T62	138		T207	64		T28	27
alert[0xf]	5442	1			T45	13		T24	33		T26	2
alert[0x10]	4419	1			T9	1		T19	10		T24	6
alert[0x11]	8205	1			T5	45		T62	271		T68	781
alert[0x12]	3915	1			T45	28		T24	25		T207	196
alert[0x13]	6151	1			T24	65		T210	1		T207	10
alert[0x14]	8264	1			T45	166		T62	157		T35	42
alert[0x15]	2849	1			T5	234		T12	2		T207	137
alert[0x16]	11343	1			T19	19		T24	2		T75	1
alert[0x17]	6781	1			T45	111		T24	427		T62	3
alert[0x18]	4035	1			T5	15		T62	74		T35	644
alert[0x19]	3285	1			T5	347		T19	7		T207	183
alert[0x1a]	4818	1			T5	37		T24	7		T65	2
alert[0x1b]	4570	1			T9	1		T24	167		T75	1
alert[0x1c]	8760	1			T9	1		T19	31		T45	312
alert[0x1d]	3874	1			T26	8		T12	1		T28	57
alert[0x1e]	12018	1			T45	12		T24	7		T26	17
alert[0x1f]	8859	1			T5	6		T19	2		T45	8
alert[0x20]	9556	1			T9	1		T24	559		T11	1
alert[0x21]	8470	1			T5	242		T24	13		T62	136
alert[0x22]	5228	1			T5	3455		T45	511		T24	7
alert[0x23]	2761	1			T1	9		T45	9		T26	2
alert[0x24]	4780	1			T19	14		T26	2		T76	39
alert[0x25]	2731	1			T5	13		T19	2		T24	171
alert[0x26]	5491	1			T45	44		T26	117		T75	8
alert[0x27]	3812	1			T5	7		T24	188		T26	2
alert[0x28]	6798	1			T45	54		T24	83		T75	7
alert[0x29]	14327	1			T62	630		T75	1		T68	671
alert[0x2a]	2356	1			T5	35		T19	15		T45	75
alert[0x2b]	12757	1			T10	1		T210	1		T194	4
alert[0x2c]	8285	1			T45	91		T290	1		T35	172
alert[0x2d]	2983	1			T19	1		T24	202		T65	3
alert[0x2e]	2263	1			T19	5		T295	1		T28	135
alert[0x2f]	7006	1			T12	1		T35	371		T28	1
alert[0x30]	2689	1			T5	85		T26	2		T31	1
alert[0x31]	4012	1			T19	2		T45	11		T294	1
alert[0x32]	1769	1			T62	94		T68	84		T294	2
alert[0x33]	7166	1			T1	4		T5	8		T45	552
alert[0x34]	3765	1			T5	72		T45	14		T26	6
alert[0x35]	6892	1			T62	56		T13	1		T173	1
alert[0x36]	9615	1			T5	66		T45	9		T26	3
alert[0x37]	5726	1			T1	18		T9	1		T45	49
alert[0x38]	3477	1			T24	2		T35	40		T68	410
alert[0x39]	5757	1			T5	105		T76	116		T207	96
alert[0x3a]	6234	1			T5	487		T45	148		T26	8
alert[0x3b]	4411	1			T5	547		T9	1		T19	33
alert[0x3c]	12050	1			T45	515		T207	19		T295	2
alert[0x3d]	5323	1			T45	358		T24	39		T62	52
alert[0x3e]	10367	1			T24	70		T25	3		T26	2
alert[0x3f]	7459	1			T45	89		T24	1248		T62	409
alert[0x40]	14286	1			T62	721		T77	2		T28	23

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	114562	1			T1	31		T9	1		T19	41
class_i[0x1]	110599	1			T5	10013		T9	2		T19	37
class_i[0x2]	98052	1			T5	65		T9	7		T19	81
class_i[0x3]	95889	1			T5	1		T19	3		T26	92

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

418399

1

T1

31

T5

10079

T19

162

alert_ping_fail

703

1

T9

10

T10

2

T11

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	7780	1			T45	448		T25	148		T62	635
alert_integrity_fail	alert[0x1]	5522	1			T24	70		T62	147		T35	13
alert_integrity_fail	alert[0x2]	5790	1			T5	41		T45	18		T35	7
alert_integrity_fail	alert[0x3]	3041	1			T45	97		T75	4		T28	114
alert_integrity_fail	alert[0x4]	9819	1			T5	10		T45	12		T24	19
alert_integrity_fail	alert[0x5]	4131	1			T26	1		T62	330		T35	27
alert_integrity_fail	alert[0x6]	4493	1			T5	3		T45	22		T24	3
alert_integrity_fail	alert[0x7]	2430	1			T45	41		T207	197		T28	7
alert_integrity_fail	alert[0x8]	7493	1			T24	116		T62	2337		T234	1
alert_integrity_fail	alert[0x9]	9145	1			T5	4210		T24	10		T26	6
alert_integrity_fail	alert[0xa]	10854	1			T45	7		T24	1		T62	15
alert_integrity_fail	alert[0xb]	11697	1			T5	9		T19	12		T45	2010
alert_integrity_fail	alert[0xc]	8399	1			T19	9		T45	8		T24	418
alert_integrity_fail	alert[0xd]	4569	1			T45	3		T24	144		T207	63
alert_integrity_fail	alert[0xe]	5593	1			T62	138		T207	64		T28	27
alert_integrity_fail	alert[0xf]	5436	1			T45	13		T24	33		T26	2
alert_integrity_fail	alert[0x10]	4408	1			T19	10		T24	6		T207	32
alert_integrity_fail	alert[0x11]	8195	1			T5	45		T62	271		T68	781
alert_integrity_fail	alert[0x12]	3902	1			T45	28		T24	25		T207	196
alert_integrity_fail	alert[0x13]	6136	1			T24	65		T207	10		T77	3
alert_integrity_fail	alert[0x14]	8247	1			T45	166		T62	157		T35	42
alert_integrity_fail	alert[0x15]	2829	1			T5	234		T207	137		T296	32
alert_integrity_fail	alert[0x16]	11329	1			T19	19		T24	2		T75	1
alert_integrity_fail	alert[0x17]	6773	1			T45	111		T24	427		T62	3
alert_integrity_fail	alert[0x18]	4027	1			T5	15		T62	74		T35	644
alert_integrity_fail	alert[0x19]	3276	1			T5	347		T19	7		T207	183
alert_integrity_fail	alert[0x1a]	4807	1			T5	37		T24	7		T65	2
alert_integrity_fail	alert[0x1b]	4554	1			T24	167		T75	1		T35	12
alert_integrity_fail	alert[0x1c]	8752	1			T19	31		T45	312		T26	3
alert_integrity_fail	alert[0x1d]	3860	1			T26	8		T28	57		T296	22
alert_integrity_fail	alert[0x1e]	12003	1			T45	12		T24	7		T26	17
alert_integrity_fail	alert[0x1f]	8840	1			T5	6		T19	2		T45	8
alert_integrity_fail	alert[0x20]	9542	1			T24	559		T35	5		T76	822
alert_integrity_fail	alert[0x21]	8460	1			T5	242		T24	13		T62	136
alert_integrity_fail	alert[0x22]	5214	1			T5	3455		T45	511		T24	7
alert_integrity_fail	alert[0x23]	2753	1			T1	9		T45	9		T26	2
alert_integrity_fail	alert[0x24]	4769	1			T19	14		T26	2		T76	39
alert_integrity_fail	alert[0x25]	2723	1			T5	13		T19	2		T24	171
alert_integrity_fail	alert[0x26]	5482	1			T45	44		T26	117		T75	8
alert_integrity_fail	alert[0x27]	3808	1			T5	7		T24	188		T26	2
alert_integrity_fail	alert[0x28]	6790	1			T45	54		T24	83		T75	7
alert_integrity_fail	alert[0x29]	14318	1			T62	630		T75	1		T68	671
alert_integrity_fail	alert[0x2a]	2347	1			T5	35		T19	15		T45	75
alert_integrity_fail	alert[0x2b]	12747	1			T194	4		T81	2		T82	159
alert_integrity_fail	alert[0x2c]	8265	1			T45	91		T35	172		T76	12
alert_integrity_fail	alert[0x2d]	2974	1			T19	1		T24	202		T65	3
alert_integrity_fail	alert[0x2e]	2249	1			T19	5		T28	135		T29	3
alert_integrity_fail	alert[0x2f]	6990	1			T35	371		T28	1		T296	16
alert_integrity_fail	alert[0x30]	2676	1			T5	85		T26	2		T296	103
alert_integrity_fail	alert[0x31]	4004	1			T19	2		T45	11		T82	89
alert_integrity_fail	alert[0x32]	1762	1			T62	94		T68	84		T82	210
alert_integrity_fail	alert[0x33]	7150	1			T1	4		T5	8		T45	552
alert_integrity_fail	alert[0x34]	3753	1			T5	72		T45	14		T26	6
alert_integrity_fail	alert[0x35]	6883	1			T62	56		T173	1		T261	1419
alert_integrity_fail	alert[0x36]	9610	1			T5	66		T45	9		T26	3
alert_integrity_fail	alert[0x37]	5716	1			T1	18		T45	49		T24	20
alert_integrity_fail	alert[0x38]	3463	1			T24	2		T35	40		T68	410
alert_integrity_fail	alert[0x39]	5751	1			T5	105		T76	116		T207	96
alert_integrity_fail	alert[0x3a]	6229	1			T5	487		T45	148		T26	8
alert_integrity_fail	alert[0x3b]	4401	1			T5	547		T19	33		T45	11
alert_integrity_fail	alert[0x3c]	12040	1			T45	515		T207	19		T79	2
alert_integrity_fail	alert[0x3d]	5313	1			T45	358		T24	39		T62	52
alert_integrity_fail	alert[0x3e]	10355	1			T24	70		T25	3		T26	2
alert_integrity_fail	alert[0x3f]	7453	1			T45	89		T24	1248		T62	409
alert_integrity_fail	alert[0x40]	14279	1			T62	721		T77	2		T28	23
alert_ping_fail	alert[0x0]	10	1			T295	1		T31	1		T294	1
alert_ping_fail	alert[0x1]	9	1			T9	1		T294	1		T297	1
alert_ping_fail	alert[0x2]	12	1			T9	1		T13	1		T298	1
alert_ping_fail	alert[0x3]	12	1			T299	2		T300	1		T179	1
alert_ping_fail	alert[0x4]	9	1			T301	1		T302	1		T298	1
alert_ping_fail	alert[0x5]	9	1			T294	2		T303	1		T304	1
alert_ping_fail	alert[0x6]	16	1			T9	1		T13	1		T295	1
alert_ping_fail	alert[0x7]	9	1			T267	1		T301	1		T305	1
alert_ping_fail	alert[0x8]	9	1			T294	1		T301	1		T302	1
alert_ping_fail	alert[0x9]	12	1			T306	1		T299	1		T298	1
alert_ping_fail	alert[0xa]	16	1			T294	2		T307	1		T293	1
alert_ping_fail	alert[0xb]	8	1			T12	1		T299	1		T179	1
alert_ping_fail	alert[0xc]	9	1			T308	1		T306	1		T302	1
alert_ping_fail	alert[0xd]	8	1			T9	1		T304	1		T309	1
alert_ping_fail	alert[0xe]	8	1			T294	1		T297	2		T310	1
alert_ping_fail	alert[0xf]	6	1			T299	2		T304	1		T305	1
alert_ping_fail	alert[0x10]	11	1			T9	1		T31	1		T294	1
alert_ping_fail	alert[0x11]	10	1			T31	1		T302	1		T311	1
alert_ping_fail	alert[0x12]	13	1			T308	1		T302	1		T298	2
alert_ping_fail	alert[0x13]	15	1			T210	1		T308	1		T231	1
alert_ping_fail	alert[0x14]	17	1			T294	1		T308	1		T312	2
alert_ping_fail	alert[0x15]	20	1			T12	2		T294	1		T238	2
alert_ping_fail	alert[0x16]	14	1			T294	1		T313	1		T238	1
alert_ping_fail	alert[0x17]	8	1			T306	1		T300	1		T314	1
alert_ping_fail	alert[0x18]	8	1			T299	2		T298	1		T311	1
alert_ping_fail	alert[0x19]	9	1			T295	2		T306	1		T304	1
alert_ping_fail	alert[0x1a]	11	1			T297	1		T300	2		T315	2
alert_ping_fail	alert[0x1b]	16	1			T9	1		T295	1		T308	2
alert_ping_fail	alert[0x1c]	8	1			T9	1		T12	1		T297	1
alert_ping_fail	alert[0x1d]	14	1			T12	1		T308	1		T307	1
alert_ping_fail	alert[0x1e]	15	1			T31	1		T308	1		T305	1
alert_ping_fail	alert[0x1f]	19	1			T12	1		T31	1		T294	1
alert_ping_fail	alert[0x20]	14	1			T9	1		T11	1		T31	1
alert_ping_fail	alert[0x21]	10	1			T295	1		T294	1		T306	1
alert_ping_fail	alert[0x22]	14	1			T210	1		T295	1		T31	1
alert_ping_fail	alert[0x23]	8	1			T31	1		T294	1		T298	1
alert_ping_fail	alert[0x24]	11	1			T295	1		T305	1		T309	1
alert_ping_fail	alert[0x25]	8	1			T306	1		T298	1		T300	1
alert_ping_fail	alert[0x26]	9	1			T302	2		T310	1		T316	1
alert_ping_fail	alert[0x27]	4	1			T302	1		T315	1		T179	1
alert_ping_fail	alert[0x28]	8	1			T295	1		T294	1		T238	1
alert_ping_fail	alert[0x29]	9	1			T302	1		T299	1		T311	1
alert_ping_fail	alert[0x2a]	9	1			T10	1		T299	1		T304	1
alert_ping_fail	alert[0x2b]	10	1			T10	1		T210	1		T299	1
alert_ping_fail	alert[0x2c]	20	1			T290	1		T307	1		T293	3
alert_ping_fail	alert[0x2d]	9	1			T308	1		T306	1		T113	1
alert_ping_fail	alert[0x2e]	14	1			T295	1		T31	1		T301	1
alert_ping_fail	alert[0x2f]	16	1			T12	1		T31	1		T313	1
alert_ping_fail	alert[0x30]	13	1			T31	1		T302	2		T298	1
alert_ping_fail	alert[0x31]	8	1			T294	1		T307	1		T314	1
alert_ping_fail	alert[0x32]	7	1			T294	2		T301	1		T309	1
alert_ping_fail	alert[0x33]	16	1			T12	1		T31	1		T308	1
alert_ping_fail	alert[0x34]	12	1			T295	1		T31	1		T305	1
alert_ping_fail	alert[0x35]	9	1			T13	1		T315	1		T317	1
alert_ping_fail	alert[0x36]	5	1			T311	1		T297	1		T309	1
alert_ping_fail	alert[0x37]	10	1			T9	1		T31	1		T308	2
alert_ping_fail	alert[0x38]	14	1			T295	1		T294	1		T302	2
alert_ping_fail	alert[0x39]	6	1			T294	1		T301	1		T297	1
alert_ping_fail	alert[0x3a]	5	1			T298	1		T318	1		T319	1
alert_ping_fail	alert[0x3b]	10	1			T9	1		T13	1		T306	1
alert_ping_fail	alert[0x3c]	10	1			T295	2		T305	1		T310	1
alert_ping_fail	alert[0x3d]	10	1			T12	1		T308	1		T298	1
alert_ping_fail	alert[0x3e]	12	1			T13	1		T294	1		T299	1
alert_ping_fail	alert[0x3f]	6	1			T307	1		T306	1		T302	1
alert_ping_fail	alert[0x40]	7	1			T294	1		T314	1		T320	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	114389	1			T1	31		T19	41		T45	168
alert_integrity_fail	class_i[0x1]	110444	1			T5	10013		T19	37		T24	4284
alert_integrity_fail	class_i[0x2]	97812	1			T5	65		T19	81		T45	5688
alert_integrity_fail	class_i[0x3]	95754	1			T5	1		T19	3		T26	92
alert_ping_fail	class_i[0x0]	173	1			T9	1		T11	1		T31	1
alert_ping_fail	class_i[0x1]	155	1			T9	2		T12	7		T13	5
alert_ping_fail	class_i[0x2]	240	1			T9	7		T12	1		T290	1
alert_ping_fail	class_i[0x3]	135	1			T10	2		T12	1		T210	3