Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.69 99.97 100.00 100.00 99.38 99.60


Total test records in report: 827
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T771 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.706648659 Mar 21 02:14:59 PM PDT 24 Mar 21 02:15:21 PM PDT 24 345955565 ps
T134 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1534132678 Mar 21 02:13:20 PM PDT 24 Mar 21 02:31:16 PM PDT 24 14314473187 ps
T772 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2296982633 Mar 21 02:15:32 PM PDT 24 Mar 21 02:15:37 PM PDT 24 112524481 ps
T136 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3622440841 Mar 21 02:14:32 PM PDT 24 Mar 21 02:19:24 PM PDT 24 4144774114 ps
T133 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4062008657 Mar 21 02:13:08 PM PDT 24 Mar 21 02:17:08 PM PDT 24 6950459147 ps
T773 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2612110345 Mar 21 02:15:32 PM PDT 24 Mar 21 02:15:33 PM PDT 24 8412360 ps
T774 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.935064517 Mar 21 02:15:00 PM PDT 24 Mar 21 02:15:01 PM PDT 24 7715743 ps
T775 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3645519190 Mar 21 02:15:55 PM PDT 24 Mar 21 02:15:57 PM PDT 24 25150406 ps
T776 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3453457579 Mar 21 02:15:37 PM PDT 24 Mar 21 02:15:40 PM PDT 24 16080769 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.645581377 Mar 21 02:14:30 PM PDT 24 Mar 21 02:14:32 PM PDT 24 10724100 ps
T355 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3505480099 Mar 21 02:14:59 PM PDT 24 Mar 21 02:22:00 PM PDT 24 7837677526 ps
T778 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1542865978 Mar 21 02:15:42 PM PDT 24 Mar 21 02:15:45 PM PDT 24 41097335 ps
T356 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2187684792 Mar 21 02:14:04 PM PDT 24 Mar 21 02:21:11 PM PDT 24 26492171770 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3501499928 Mar 21 02:13:39 PM PDT 24 Mar 21 02:18:27 PM PDT 24 15171595966 ps
T780 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1727067954 Mar 21 02:15:30 PM PDT 24 Mar 21 02:15:32 PM PDT 24 10422684 ps
T781 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1987296495 Mar 21 02:14:57 PM PDT 24 Mar 21 02:15:10 PM PDT 24 176855756 ps
T782 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4262957435 Mar 21 02:14:31 PM PDT 24 Mar 21 02:14:42 PM PDT 24 266212535 ps
T146 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3115394497 Mar 21 02:13:13 PM PDT 24 Mar 21 02:21:12 PM PDT 24 48393267224 ps
T783 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1462490409 Mar 21 02:15:44 PM PDT 24 Mar 21 02:15:48 PM PDT 24 9693225 ps
T353 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3730119201 Mar 21 02:14:19 PM PDT 24 Mar 21 02:22:22 PM PDT 24 6585219077 ps
T142 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3008513443 Mar 21 02:14:33 PM PDT 24 Mar 21 02:20:11 PM PDT 24 3038179329 ps
T784 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3842866928 Mar 21 02:13:37 PM PDT 24 Mar 21 02:13:46 PM PDT 24 220806319 ps
T143 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1886429029 Mar 21 02:14:20 PM PDT 24 Mar 21 02:26:09 PM PDT 24 5859861540 ps
T785 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.821336245 Mar 21 02:15:57 PM PDT 24 Mar 21 02:15:59 PM PDT 24 12718588 ps
T786 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.770915146 Mar 21 02:15:16 PM PDT 24 Mar 21 02:15:20 PM PDT 24 39707524 ps
T787 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1340602937 Mar 21 02:14:19 PM PDT 24 Mar 21 02:15:06 PM PDT 24 9046994897 ps
T788 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.61330739 Mar 21 02:15:31 PM PDT 24 Mar 21 02:15:33 PM PDT 24 10925995 ps
T789 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4269917988 Mar 21 02:15:35 PM PDT 24 Mar 21 02:15:45 PM PDT 24 386886105 ps
T790 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3031668146 Mar 21 02:14:18 PM PDT 24 Mar 21 02:14:44 PM PDT 24 325048585 ps
T140 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3067858947 Mar 21 02:15:34 PM PDT 24 Mar 21 02:25:04 PM PDT 24 16775993629 ps
T791 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4241178552 Mar 21 02:15:18 PM PDT 24 Mar 21 02:17:11 PM PDT 24 3210941353 ps
T160 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2874634228 Mar 21 02:14:44 PM PDT 24 Mar 21 02:15:05 PM PDT 24 319119439 ps
T792 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1524058570 Mar 21 02:15:32 PM PDT 24 Mar 21 02:16:09 PM PDT 24 531103975 ps
T793 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3080148097 Mar 21 02:15:42 PM PDT 24 Mar 21 02:15:45 PM PDT 24 14850083 ps
T794 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.943610761 Mar 21 02:15:32 PM PDT 24 Mar 21 02:15:34 PM PDT 24 10069342 ps
T144 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.760177570 Mar 21 02:14:10 PM PDT 24 Mar 21 02:16:47 PM PDT 24 7097168152 ps
T795 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2334011535 Mar 21 02:13:41 PM PDT 24 Mar 21 02:13:52 PM PDT 24 126760395 ps
T796 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.601980955 Mar 21 02:14:46 PM PDT 24 Mar 21 02:14:53 PM PDT 24 51380631 ps
T797 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4010770348 Mar 21 02:14:44 PM PDT 24 Mar 21 02:14:50 PM PDT 24 215078022 ps
T798 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3646759300 Mar 21 02:15:36 PM PDT 24 Mar 21 02:15:39 PM PDT 24 8215574 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1521312145 Mar 21 02:13:19 PM PDT 24 Mar 21 02:14:07 PM PDT 24 1853684258 ps
T800 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2270417805 Mar 21 02:15:27 PM PDT 24 Mar 21 02:15:34 PM PDT 24 77755352 ps
T801 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.895324952 Mar 21 02:15:43 PM PDT 24 Mar 21 02:15:46 PM PDT 24 32414281 ps
T802 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1770955943 Mar 21 02:13:30 PM PDT 24 Mar 21 02:13:39 PM PDT 24 53061199 ps
T803 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.402822866 Mar 21 02:15:42 PM PDT 24 Mar 21 02:15:45 PM PDT 24 11983114 ps
T804 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2243808614 Mar 21 02:13:40 PM PDT 24 Mar 21 02:17:18 PM PDT 24 1687000952 ps
T805 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3187690176 Mar 21 02:14:00 PM PDT 24 Mar 21 02:14:02 PM PDT 24 8149278 ps
T806 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.411142316 Mar 21 02:15:26 PM PDT 24 Mar 21 02:15:28 PM PDT 24 12252661 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1072163275 Mar 21 02:15:33 PM PDT 24 Mar 21 02:15:43 PM PDT 24 114251230 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.92686183 Mar 21 02:13:25 PM PDT 24 Mar 21 02:14:45 PM PDT 24 1187005432 ps
T809 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.835827017 Mar 21 02:15:30 PM PDT 24 Mar 21 02:17:15 PM PDT 24 816770386 ps
T810 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.59603265 Mar 21 02:15:17 PM PDT 24 Mar 21 02:15:39 PM PDT 24 503874691 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2597568885 Mar 21 02:13:38 PM PDT 24 Mar 21 02:13:52 PM PDT 24 242994166 ps
T812 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.102007385 Mar 21 02:14:19 PM PDT 24 Mar 21 02:14:41 PM PDT 24 298247846 ps
T813 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1440935870 Mar 21 02:15:30 PM PDT 24 Mar 21 02:15:32 PM PDT 24 8010402 ps
T814 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2219913381 Mar 21 02:15:42 PM PDT 24 Mar 21 02:15:45 PM PDT 24 6681398 ps
T158 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1633189372 Mar 21 02:14:58 PM PDT 24 Mar 21 02:15:01 PM PDT 24 36649653 ps
T354 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3970666003 Mar 21 02:14:47 PM PDT 24 Mar 21 02:35:58 PM PDT 24 63892548850 ps
T171 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4074511102 Mar 21 02:14:43 PM PDT 24 Mar 21 02:15:29 PM PDT 24 1219139963 ps
T159 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1524517350 Mar 21 02:13:09 PM PDT 24 Mar 21 02:13:14 PM PDT 24 54533651 ps
T815 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2645520470 Mar 21 02:14:10 PM PDT 24 Mar 21 02:14:17 PM PDT 24 111811901 ps
T155 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3920780413 Mar 21 02:12:54 PM PDT 24 Mar 21 02:14:14 PM PDT 24 8764640984 ps
T816 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1390782506 Mar 21 02:15:53 PM PDT 24 Mar 21 02:15:55 PM PDT 24 12967732 ps
T817 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4010763241 Mar 21 02:13:50 PM PDT 24 Mar 21 02:14:04 PM PDT 24 687616355 ps
T145 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2970106398 Mar 21 02:13:49 PM PDT 24 Mar 21 02:24:55 PM PDT 24 33065280264 ps
T818 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1992520970 Mar 21 02:15:01 PM PDT 24 Mar 21 02:15:12 PM PDT 24 487188215 ps
T819 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3487119241 Mar 21 02:14:44 PM PDT 24 Mar 21 02:14:51 PM PDT 24 156016608 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.827525312 Mar 21 02:12:51 PM PDT 24 Mar 21 02:29:30 PM PDT 24 13687860185 ps
T820 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.436785239 Mar 21 02:14:00 PM PDT 24 Mar 21 02:14:09 PM PDT 24 471204736 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.906507645 Mar 21 02:13:30 PM PDT 24 Mar 21 02:13:36 PM PDT 24 242202792 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1666778248 Mar 21 02:14:34 PM PDT 24 Mar 21 02:14:39 PM PDT 24 52164542 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3488677254 Mar 21 02:14:10 PM PDT 24 Mar 21 02:14:12 PM PDT 24 9964241 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2866773262 Mar 21 02:13:29 PM PDT 24 Mar 21 02:13:38 PM PDT 24 100511720 ps
T156 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3100487382 Mar 21 02:13:48 PM PDT 24 Mar 21 02:13:52 PM PDT 24 52550258 ps
T825 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.927617501 Mar 21 02:15:32 PM PDT 24 Mar 21 02:15:34 PM PDT 24 13262318 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.694407156 Mar 21 02:14:33 PM PDT 24 Mar 21 02:14:54 PM PDT 24 314337403 ps
T827 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2772964197 Mar 21 02:14:19 PM PDT 24 Mar 21 02:14:22 PM PDT 24 18492736 ps

Test location /workspace/coverage/default/49.alert_handler_stress_all.2573522474
Short name T1
Test name
Test status
Simulation time 20028036303 ps
CPU time 1899.12 seconds
Started Mar 21 02:32:11 PM PDT 24
Finished Mar 21 03:03:51 PM PDT 24
Peak memory 302712 kb
Host smart-d9ae3458-d6af-4b8f-a1ee-16042e173423
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573522474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2573522474
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.396448217
Short name T26
Test name
Test status
Simulation time 73135029187 ps
CPU time 1031.79 seconds
Started Mar 21 02:28:17 PM PDT 24
Finished Mar 21 02:45:29 PM PDT 24
Peak memory 272592 kb
Host smart-e55b0ed7-355d-4886-a9ea-b70856e17d12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396448217 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.396448217
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.645125483
Short name T14
Test name
Test status
Simulation time 1229263191 ps
CPU time 53.16 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:28:43 PM PDT 24
Peak memory 269188 kb
Host smart-3ffc02c8-1a37-4f60-aec1-5ad6d8797e10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=645125483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.645125483
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2384205771
Short name T45
Test name
Test status
Simulation time 38778218260 ps
CPU time 1935.76 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 03:01:20 PM PDT 24
Peak memory 284068 kb
Host smart-d41f9f67-1a9c-493f-8943-9e0623965682
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384205771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2384205771
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2410865382
Short name T150
Test name
Test status
Simulation time 632136864 ps
CPU time 47.15 seconds
Started Mar 21 02:14:31 PM PDT 24
Finished Mar 21 02:15:18 PM PDT 24
Peak memory 239596 kb
Host smart-d72c05ba-b578-43f3-830a-c77fa0701a37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2410865382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2410865382
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3648966395
Short name T34
Test name
Test status
Simulation time 100480322442 ps
CPU time 2981.37 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 03:20:24 PM PDT 24
Peak memory 289380 kb
Host smart-b87bc624-3962-417e-b330-8540d0a37663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648966395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3648966395
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1685279883
Short name T689
Test name
Test status
Simulation time 25978372250 ps
CPU time 1845.84 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:58:54 PM PDT 24
Peak memory 281528 kb
Host smart-391059d5-2438-4da4-80d4-1ff7f7886106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685279883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1685279883
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.131731847
Short name T117
Test name
Test status
Simulation time 12800051405 ps
CPU time 1107.35 seconds
Started Mar 21 02:13:29 PM PDT 24
Finished Mar 21 02:31:57 PM PDT 24
Peak memory 265152 kb
Host smart-ea2130ff-352d-4b62-a458-cad5d13f71ad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131731847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.131731847
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3144914166
Short name T210
Test name
Test status
Simulation time 169536625248 ps
CPU time 2711.85 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 03:15:54 PM PDT 24
Peak memory 289548 kb
Host smart-7359e373-d4e1-4095-a702-6714fa2aa52c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144914166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3144914166
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3098921024
Short name T19
Test name
Test status
Simulation time 35319099777 ps
CPU time 2669.88 seconds
Started Mar 21 02:28:51 PM PDT 24
Finished Mar 21 03:13:22 PM PDT 24
Peak memory 287404 kb
Host smart-475013c5-ced4-4e27-9d9f-c158f779cbff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098921024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3098921024
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1954212883
Short name T129
Test name
Test status
Simulation time 19705400157 ps
CPU time 339.51 seconds
Started Mar 21 02:13:19 PM PDT 24
Finished Mar 21 02:18:58 PM PDT 24
Peak memory 265132 kb
Host smart-8ceac58c-75fe-4783-8e08-cbefbf0d1557
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1954212883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1954212883
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3349438462
Short name T89
Test name
Test status
Simulation time 78282631895 ps
CPU time 2020.59 seconds
Started Mar 21 02:28:52 PM PDT 24
Finished Mar 21 03:02:33 PM PDT 24
Peak memory 281676 kb
Host smart-ed87e137-9ed4-4e91-91f9-7ae122d18b6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349438462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3349438462
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2196988747
Short name T294
Test name
Test status
Simulation time 22536386669 ps
CPU time 496.22 seconds
Started Mar 21 02:31:42 PM PDT 24
Finished Mar 21 02:39:58 PM PDT 24
Peak memory 247852 kb
Host smart-6b04e046-19d0-493b-8e86-638663a646a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196988747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2196988747
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4097942498
Short name T32
Test name
Test status
Simulation time 149842802434 ps
CPU time 1585.74 seconds
Started Mar 21 02:32:11 PM PDT 24
Finished Mar 21 02:58:37 PM PDT 24
Peak memory 272624 kb
Host smart-8939f504-f53d-48e3-acf8-1c8a75da3cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097942498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4097942498
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3632243083
Short name T135
Test name
Test status
Simulation time 6625545265 ps
CPU time 640.75 seconds
Started Mar 21 02:14:12 PM PDT 24
Finished Mar 21 02:24:54 PM PDT 24
Peak memory 273316 kb
Host smart-280e5569-07fe-4c6c-ae74-638730db0dcc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632243083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3632243083
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.866058468
Short name T82
Test name
Test status
Simulation time 269058152788 ps
CPU time 3702.6 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 03:32:59 PM PDT 24
Peak memory 304884 kb
Host smart-b84f33d7-7941-4033-a35e-262b2e6c02ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866058468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.866058468
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3735019398
Short name T138
Test name
Test status
Simulation time 8124986488 ps
CPU time 284.27 seconds
Started Mar 21 02:15:16 PM PDT 24
Finished Mar 21 02:20:01 PM PDT 24
Peak memory 265108 kb
Host smart-77527e82-f0f0-4bab-af15-cbc80b1ef132
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3735019398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3735019398
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2597419107
Short name T151
Test name
Test status
Simulation time 8404143 ps
CPU time 1.48 seconds
Started Mar 21 02:13:09 PM PDT 24
Finished Mar 21 02:13:10 PM PDT 24
Peak memory 235792 kb
Host smart-0a029bcc-449e-4909-8d74-a3ea99d53f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2597419107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2597419107
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2857064211
Short name T20
Test name
Test status
Simulation time 27023580237 ps
CPU time 1345.85 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:50:56 PM PDT 24
Peak memory 272876 kb
Host smart-407ee7a0-1f46-41cd-9571-380535406c40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857064211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2857064211
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3622440841
Short name T136
Test name
Test status
Simulation time 4144774114 ps
CPU time 291.65 seconds
Started Mar 21 02:14:32 PM PDT 24
Finished Mar 21 02:19:24 PM PDT 24
Peak memory 265372 kb
Host smart-4be008a1-0e88-4b71-9d43-77a1534285fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3622440841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3622440841
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1102838240
Short name T118
Test name
Test status
Simulation time 8089039475 ps
CPU time 366.98 seconds
Started Mar 21 02:13:42 PM PDT 24
Finished Mar 21 02:19:50 PM PDT 24
Peak memory 265208 kb
Host smart-83a63543-800b-473c-8bf2-03d644c95c7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102838240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1102838240
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2898724965
Short name T10
Test name
Test status
Simulation time 606612336057 ps
CPU time 2152.28 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 03:07:07 PM PDT 24
Peak memory 284236 kb
Host smart-4b1136fc-92a3-4103-a445-411e78a04ec9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898724965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2898724965
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1740270648
Short name T9
Test name
Test status
Simulation time 20345799730 ps
CPU time 206.28 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:34:42 PM PDT 24
Peak memory 247976 kb
Host smart-1dd07fae-723a-4807-9e83-4d1bb28cf505
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740270648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1740270648
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.827525312
Short name T147
Test name
Test status
Simulation time 13687860185 ps
CPU time 998.8 seconds
Started Mar 21 02:12:51 PM PDT 24
Finished Mar 21 02:29:30 PM PDT 24
Peak memory 265104 kb
Host smart-6dec5072-5fc1-42cc-a0f0-2523f9820ae1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827525312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.827525312
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.796573896
Short name T57
Test name
Test status
Simulation time 42987792144 ps
CPU time 733.41 seconds
Started Mar 21 02:29:16 PM PDT 24
Finished Mar 21 02:41:30 PM PDT 24
Peak memory 265352 kb
Host smart-d03d822c-d6e7-4730-a365-0862f0d56a45
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796573896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.796573896
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4280965257
Short name T297
Test name
Test status
Simulation time 100567865216 ps
CPU time 590.26 seconds
Started Mar 21 02:28:31 PM PDT 24
Finished Mar 21 02:38:22 PM PDT 24
Peak memory 247872 kb
Host smart-638ffb7a-1fdd-4886-8bcd-979165abd130
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280965257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4280965257
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2338197465
Short name T341
Test name
Test status
Simulation time 241486419594 ps
CPU time 2375.65 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 03:08:29 PM PDT 24
Peak memory 273436 kb
Host smart-6e9c9e68-2b3b-451e-9ccf-8b96d5d0e78e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338197465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2338197465
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.217195850
Short name T261
Test name
Test status
Simulation time 528393114366 ps
CPU time 4296.99 seconds
Started Mar 21 02:29:54 PM PDT 24
Finished Mar 21 03:41:32 PM PDT 24
Peak memory 298072 kb
Host smart-1d1d9cfa-87d7-472d-9861-adeeeaf692ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217195850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.217195850
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1534132678
Short name T134
Test name
Test status
Simulation time 14314473187 ps
CPU time 1075.6 seconds
Started Mar 21 02:13:20 PM PDT 24
Finished Mar 21 02:31:16 PM PDT 24
Peak memory 265160 kb
Host smart-7c6f142a-5ad0-459d-b7e0-05eef99603d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534132678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1534132678
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3852202652
Short name T316
Test name
Test status
Simulation time 20799186333 ps
CPU time 428.91 seconds
Started Mar 21 02:29:39 PM PDT 24
Finished Mar 21 02:36:49 PM PDT 24
Peak memory 248168 kb
Host smart-b4e3e270-6c3d-432f-9063-0bb7ea737a10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852202652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3852202652
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3462765184
Short name T290
Test name
Test status
Simulation time 75693562936 ps
CPU time 1307.98 seconds
Started Mar 21 02:29:16 PM PDT 24
Finished Mar 21 02:51:04 PM PDT 24
Peak memory 286628 kb
Host smart-02622a8e-7f1c-4d19-926a-db6c280446ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462765184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3462765184
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1897411149
Short name T126
Test name
Test status
Simulation time 15294504179 ps
CPU time 289.54 seconds
Started Mar 21 02:13:41 PM PDT 24
Finished Mar 21 02:18:33 PM PDT 24
Peak memory 267232 kb
Host smart-e02f41c0-81f0-4932-970e-4f85278a7dba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1897411149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1897411149
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2841388731
Short name T298
Test name
Test status
Simulation time 27814891571 ps
CPU time 307.82 seconds
Started Mar 21 02:31:00 PM PDT 24
Finished Mar 21 02:36:07 PM PDT 24
Peak memory 248192 kb
Host smart-5629e111-1d19-4435-8daa-8608c3b90a64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841388731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2841388731
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.441340153
Short name T717
Test name
Test status
Simulation time 9226038 ps
CPU time 1.39 seconds
Started Mar 21 02:15:39 PM PDT 24
Finished Mar 21 02:15:40 PM PDT 24
Peak memory 236688 kb
Host smart-ad938787-5996-4243-a637-1055185f3a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=441340153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.441340153
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3575771862
Short name T88
Test name
Test status
Simulation time 385354383030 ps
CPU time 7221.91 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 04:30:50 PM PDT 24
Peak memory 322264 kb
Host smart-9bf04125-0ddf-4a45-9594-60f035658bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575771862 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3575771862
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2695076839
Short name T205
Test name
Test status
Simulation time 361012783 ps
CPU time 8.51 seconds
Started Mar 21 02:28:31 PM PDT 24
Finished Mar 21 02:28:40 PM PDT 24
Peak memory 240704 kb
Host smart-a6dc9b12-f3e5-487d-9ff8-c467ff3cfc6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2695076839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2695076839
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1475089852
Short name T29
Test name
Test status
Simulation time 138470063270 ps
CPU time 10631.9 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 05:25:21 PM PDT 24
Peak memory 354824 kb
Host smart-84375f52-7344-4b57-96b3-1e82752994ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475089852 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1475089852
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3087007798
Short name T127
Test name
Test status
Simulation time 34609727694 ps
CPU time 629.1 seconds
Started Mar 21 02:14:32 PM PDT 24
Finished Mar 21 02:25:02 PM PDT 24
Peak memory 265220 kb
Host smart-513c7366-bc61-404f-802f-3ca3950313f8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087007798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3087007798
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2250911372
Short name T325
Test name
Test status
Simulation time 81654722639 ps
CPU time 2699.57 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 03:14:05 PM PDT 24
Peak memory 289124 kb
Host smart-9031e2a3-30f9-4706-9735-957eb26662fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250911372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2250911372
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3086665828
Short name T123
Test name
Test status
Simulation time 10338418395 ps
CPU time 177.24 seconds
Started Mar 21 02:12:51 PM PDT 24
Finished Mar 21 02:15:49 PM PDT 24
Peak memory 265184 kb
Host smart-264ee356-5d83-4f29-9721-9d7a0e295020
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3086665828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3086665828
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2716627392
Short name T511
Test name
Test status
Simulation time 8240532756 ps
CPU time 347.87 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 256220 kb
Host smart-401bd2f3-49b7-4128-9391-cddceb4f5780
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716627392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2716627392
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3968581182
Short name T333
Test name
Test status
Simulation time 44937912787 ps
CPU time 1440.76 seconds
Started Mar 21 02:29:28 PM PDT 24
Finished Mar 21 02:53:29 PM PDT 24
Peak memory 273428 kb
Host smart-539b90e7-40d6-4617-9304-1064a908eecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968581182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3968581182
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3255985098
Short name T75
Test name
Test status
Simulation time 19100011557 ps
CPU time 1074.7 seconds
Started Mar 21 02:30:29 PM PDT 24
Finished Mar 21 02:48:24 PM PDT 24
Peak memory 269864 kb
Host smart-ed9ffaa8-2d57-4764-adbd-9f6b3a8c0360
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255985098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3255985098
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1106000848
Short name T174
Test name
Test status
Simulation time 60744649711 ps
CPU time 2988.4 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 03:17:40 PM PDT 24
Peak memory 305964 kb
Host smart-3e83540e-634f-43ff-a8b7-e85bd2fbea4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106000848 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1106000848
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3945535304
Short name T309
Test name
Test status
Simulation time 14727573683 ps
CPU time 601.56 seconds
Started Mar 21 02:29:55 PM PDT 24
Finished Mar 21 02:39:57 PM PDT 24
Peak memory 247848 kb
Host smart-6b814ee0-a815-466e-82fb-ea34e147a7f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945535304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3945535304
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1491133193
Short name T51
Test name
Test status
Simulation time 61829510243 ps
CPU time 3187.78 seconds
Started Mar 21 02:29:51 PM PDT 24
Finished Mar 21 03:22:59 PM PDT 24
Peak memory 321936 kb
Host smart-d3a66ee6-edab-43b1-a4e2-80e127ae136c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491133193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1491133193
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.327505266
Short name T58
Test name
Test status
Simulation time 41896383396 ps
CPU time 2691.82 seconds
Started Mar 21 02:27:52 PM PDT 24
Finished Mar 21 03:12:44 PM PDT 24
Peak memory 281704 kb
Host smart-72b5631d-f1bc-435f-b66d-dbba6f68d588
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327505266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.327505266
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.748932273
Short name T161
Test name
Test status
Simulation time 39135104 ps
CPU time 3.67 seconds
Started Mar 21 02:13:25 PM PDT 24
Finished Mar 21 02:13:29 PM PDT 24
Peak memory 236672 kb
Host smart-8d5aaa19-9947-45ae-90b9-4394d6cba6c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=748932273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.748932273
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2970106398
Short name T145
Test name
Test status
Simulation time 33065280264 ps
CPU time 665.59 seconds
Started Mar 21 02:13:49 PM PDT 24
Finished Mar 21 02:24:55 PM PDT 24
Peak memory 265400 kb
Host smart-46d3efd5-81e7-4134-ad2c-1a06d98311a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970106398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2970106398
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2683856356
Short name T130
Test name
Test status
Simulation time 58770937848 ps
CPU time 555.44 seconds
Started Mar 21 02:15:27 PM PDT 24
Finished Mar 21 02:24:43 PM PDT 24
Peak memory 267900 kb
Host smart-1a080db6-a3b2-4970-b0e6-1a0568da2307
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683856356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2683856356
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1123833136
Short name T166
Test name
Test status
Simulation time 468534393 ps
CPU time 36.16 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:36 PM PDT 24
Peak memory 240336 kb
Host smart-ff3c2423-4451-485b-b6a3-29b8b05ad5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1123833136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1123833136
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.289104204
Short name T223
Test name
Test status
Simulation time 134314751 ps
CPU time 4.12 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:27:42 PM PDT 24
Peak memory 249084 kb
Host smart-7c491017-8e0e-4dc3-adf5-10169c26407f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=289104204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.289104204
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.833243738
Short name T221
Test name
Test status
Simulation time 24415725 ps
CPU time 2.41 seconds
Started Mar 21 02:27:37 PM PDT 24
Finished Mar 21 02:27:39 PM PDT 24
Peak memory 249096 kb
Host smart-56d14b7d-1fee-4cae-8e98-8086b8e8f6b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=833243738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.833243738
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.145897830
Short name T219
Test name
Test status
Simulation time 21848891 ps
CPU time 2.33 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:28:23 PM PDT 24
Peak memory 249100 kb
Host smart-6100fab3-5012-4c0d-9af2-65a1ec6f3097
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=145897830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.145897830
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2264050202
Short name T218
Test name
Test status
Simulation time 79560542 ps
CPU time 3.74 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:29:09 PM PDT 24
Peak memory 249040 kb
Host smart-1797380a-9224-480a-b6dd-ec6b698fd598
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2264050202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2264050202
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3936155431
Short name T277
Test name
Test status
Simulation time 286176535 ps
CPU time 37.06 seconds
Started Mar 21 02:29:55 PM PDT 24
Finished Mar 21 02:30:32 PM PDT 24
Peak memory 248196 kb
Host smart-c45c208e-28fc-47ed-acdf-c48c2e018afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
55431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3936155431
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.276334032
Short name T332
Test name
Test status
Simulation time 109071778691 ps
CPU time 3079.24 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 03:21:48 PM PDT 24
Peak memory 288924 kb
Host smart-098e5849-d9b0-445f-8698-20b9996620d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276334032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.276334032
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3444788784
Short name T315
Test name
Test status
Simulation time 54631926059 ps
CPU time 534.81 seconds
Started Mar 21 02:30:43 PM PDT 24
Finished Mar 21 02:39:39 PM PDT 24
Peak memory 248120 kb
Host smart-e270824c-2612-4aae-aeb3-8b54a995391c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444788784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3444788784
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.196242154
Short name T281
Test name
Test status
Simulation time 106318047249 ps
CPU time 3380.94 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 03:27:19 PM PDT 24
Peak memory 289596 kb
Host smart-14a85bd0-7042-43ed-a8c6-6fceed2d2aa6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196242154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.196242154
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4044361331
Short name T116
Test name
Test status
Simulation time 30133023907 ps
CPU time 611.86 seconds
Started Mar 21 02:14:59 PM PDT 24
Finished Mar 21 02:25:12 PM PDT 24
Peak memory 265176 kb
Host smart-68202611-8acf-4699-84ae-7ff45b0a60b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044361331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4044361331
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3781670277
Short name T120
Test name
Test status
Simulation time 3516082734 ps
CPU time 297.32 seconds
Started Mar 21 02:14:20 PM PDT 24
Finished Mar 21 02:19:19 PM PDT 24
Peak memory 269584 kb
Host smart-b37fc5e0-2489-4b52-b0da-6635dd664d86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3781670277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3781670277
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4000478509
Short name T269
Test name
Test status
Simulation time 109362793766 ps
CPU time 1594.35 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:54:14 PM PDT 24
Peak memory 273500 kb
Host smart-9afa01c3-b5f7-4f09-b6e4-89d0085f714e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000478509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4000478509
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2661205796
Short name T650
Test name
Test status
Simulation time 20816562302 ps
CPU time 1226.47 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:48:04 PM PDT 24
Peak memory 267392 kb
Host smart-ee15d4f2-5225-41ab-be1e-4f7490f6475f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661205796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2661205796
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1782424672
Short name T289
Test name
Test status
Simulation time 11742429077 ps
CPU time 179.84 seconds
Started Mar 21 02:28:29 PM PDT 24
Finished Mar 21 02:31:29 PM PDT 24
Peak memory 251096 kb
Host smart-20a2ce9f-4081-4be6-8300-3d44163d258f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782424672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1782424672
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1284993672
Short name T204
Test name
Test status
Simulation time 221581825395 ps
CPU time 6043.66 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 04:09:37 PM PDT 24
Peak memory 354800 kb
Host smart-3ae5b249-b037-4356-9b04-2a6fd814a28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284993672 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1284993672
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2126529896
Short name T280
Test name
Test status
Simulation time 299571958608 ps
CPU time 4372.71 seconds
Started Mar 21 02:27:41 PM PDT 24
Finished Mar 21 03:40:34 PM PDT 24
Peak memory 298028 kb
Host smart-0c580379-223f-456d-b5ed-a8cbe98ba167
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126529896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2126529896
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.827016952
Short name T48
Test name
Test status
Simulation time 16301357928 ps
CPU time 1853.6 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 03:00:11 PM PDT 24
Peak memory 298160 kb
Host smart-b4dc23cf-fe90-4989-9e17-7a44537cac12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827016952 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.827016952
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1913994376
Short name T253
Test name
Test status
Simulation time 238557052 ps
CPU time 20.7 seconds
Started Mar 21 02:29:24 PM PDT 24
Finished Mar 21 02:29:44 PM PDT 24
Peak memory 248896 kb
Host smart-2c8ad241-aa71-4a52-a2ed-ae73d9e431c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19139
94376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1913994376
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1904377070
Short name T252
Test name
Test status
Simulation time 138790937348 ps
CPU time 1559.17 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 02:55:53 PM PDT 24
Peak memory 268472 kb
Host smart-02377606-e45e-4098-bac1-a89e66c7ee39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904377070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1904377070
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3927465985
Short name T102
Test name
Test status
Simulation time 1355545491 ps
CPU time 48.87 seconds
Started Mar 21 02:31:03 PM PDT 24
Finished Mar 21 02:31:52 PM PDT 24
Peak memory 255488 kb
Host smart-255c4953-118c-42a2-88e7-88ba248f1784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39274
65985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3927465985
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3636943182
Short name T256
Test name
Test status
Simulation time 80996176169 ps
CPU time 2167.57 seconds
Started Mar 21 02:31:27 PM PDT 24
Finished Mar 21 03:07:34 PM PDT 24
Peak memory 306240 kb
Host smart-d5992089-8db2-49d1-b565-4fc10761f8a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636943182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3636943182
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3425948481
Short name T15
Test name
Test status
Simulation time 961983639 ps
CPU time 28.15 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:28:07 PM PDT 24
Peak memory 264252 kb
Host smart-3a800977-b327-402f-b1bf-3d6a97f7c04f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3425948481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3425948481
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1762697778
Short name T131
Test name
Test status
Simulation time 2570802869 ps
CPU time 235.15 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:18:39 PM PDT 24
Peak memory 265180 kb
Host smart-08ce6b89-1271-44be-9ae4-43f6e90e13d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1762697778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1762697778
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2874634228
Short name T160
Test name
Test status
Simulation time 319119439 ps
CPU time 20.24 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:15:05 PM PDT 24
Peak memory 240340 kb
Host smart-50960cd0-5bf0-4136-a982-ea35301d7772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2874634228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2874634228
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.669027060
Short name T164
Test name
Test status
Simulation time 60372833 ps
CPU time 2.69 seconds
Started Mar 21 02:15:18 PM PDT 24
Finished Mar 21 02:15:20 PM PDT 24
Peak memory 236664 kb
Host smart-8ccacbfe-687e-46c2-ba6a-5a00fba7288a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=669027060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.669027060
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1627396897
Short name T154
Test name
Test status
Simulation time 422107035 ps
CPU time 2.85 seconds
Started Mar 21 02:13:39 PM PDT 24
Finished Mar 21 02:13:43 PM PDT 24
Peak memory 236680 kb
Host smart-84a82f31-413b-4b86-bd8e-42ac8064ad50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1627396897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1627396897
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3100487382
Short name T156
Test name
Test status
Simulation time 52550258 ps
CPU time 3.96 seconds
Started Mar 21 02:13:48 PM PDT 24
Finished Mar 21 02:13:52 PM PDT 24
Peak memory 236696 kb
Host smart-71bc4969-180f-46da-85cf-3892b29142db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3100487382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3100487382
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2084231347
Short name T157
Test name
Test status
Simulation time 82723366 ps
CPU time 3.15 seconds
Started Mar 21 02:14:11 PM PDT 24
Finished Mar 21 02:14:15 PM PDT 24
Peak memory 236652 kb
Host smart-2fc8101e-bf89-43b8-9164-8d337258b730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2084231347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2084231347
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.759581837
Short name T22
Test name
Test status
Simulation time 5119861755 ps
CPU time 69.22 seconds
Started Mar 21 02:28:37 PM PDT 24
Finished Mar 21 02:29:47 PM PDT 24
Peak memory 248948 kb
Host smart-9e8c2e22-5425-42fc-b39d-846295b8d230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75958
1837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.759581837
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1524517350
Short name T159
Test name
Test status
Simulation time 54533651 ps
CPU time 4.71 seconds
Started Mar 21 02:13:09 PM PDT 24
Finished Mar 21 02:13:14 PM PDT 24
Peak memory 237728 kb
Host smart-602e33e7-5a6c-445f-a320-6406ae52173c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1524517350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1524517350
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2636984966
Short name T167
Test name
Test status
Simulation time 62302677 ps
CPU time 3.02 seconds
Started Mar 21 02:14:31 PM PDT 24
Finished Mar 21 02:14:34 PM PDT 24
Peak memory 236612 kb
Host smart-20d050b0-81ae-43c1-8c3b-e193eed86c10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2636984966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2636984966
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4074511102
Short name T171
Test name
Test status
Simulation time 1219139963 ps
CPU time 45.72 seconds
Started Mar 21 02:14:43 PM PDT 24
Finished Mar 21 02:15:29 PM PDT 24
Peak memory 240352 kb
Host smart-b18766f8-c8f0-4bf4-9458-b7cccc1dc461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4074511102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4074511102
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1633189372
Short name T158
Test name
Test status
Simulation time 36649653 ps
CPU time 3.03 seconds
Started Mar 21 02:14:58 PM PDT 24
Finished Mar 21 02:15:01 PM PDT 24
Peak memory 236684 kb
Host smart-1a540dc0-fc71-44de-97d9-3cbccab651e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1633189372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1633189372
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3759817623
Short name T168
Test name
Test status
Simulation time 1843938240 ps
CPU time 40.19 seconds
Started Mar 21 02:14:58 PM PDT 24
Finished Mar 21 02:15:38 PM PDT 24
Peak memory 236944 kb
Host smart-d0b185de-ac53-4b5d-82f4-7dba731bc5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3759817623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3759817623
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3196241808
Short name T163
Test name
Test status
Simulation time 94712907 ps
CPU time 3.73 seconds
Started Mar 21 02:13:30 PM PDT 24
Finished Mar 21 02:13:34 PM PDT 24
Peak memory 237004 kb
Host smart-fe0ad613-c762-499c-8ae7-1686091e74b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3196241808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3196241808
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3920780413
Short name T155
Test name
Test status
Simulation time 8764640984 ps
CPU time 80.26 seconds
Started Mar 21 02:12:54 PM PDT 24
Finished Mar 21 02:14:14 PM PDT 24
Peak memory 239440 kb
Host smart-1106dcf2-04ac-441c-9a42-6cae247990ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3920780413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3920780413
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.690104247
Short name T162
Test name
Test status
Simulation time 61454577 ps
CPU time 3.2 seconds
Started Mar 21 02:15:34 PM PDT 24
Finished Mar 21 02:15:38 PM PDT 24
Peak memory 235816 kb
Host smart-0391d20d-4184-4fb3-958f-85280f9a7e37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=690104247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.690104247
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4278688075
Short name T165
Test name
Test status
Simulation time 1303148153 ps
CPU time 40 seconds
Started Mar 21 02:13:58 PM PDT 24
Finished Mar 21 02:14:39 PM PDT 24
Peak memory 245284 kb
Host smart-84a12be6-f13f-4b52-9132-c2cd1c0487e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4278688075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4278688075
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2022027859
Short name T172
Test name
Test status
Simulation time 91126863 ps
CPU time 2.62 seconds
Started Mar 21 02:14:19 PM PDT 24
Finished Mar 21 02:14:22 PM PDT 24
Peak memory 236680 kb
Host smart-998a2850-cb54-44f3-9658-2378c9c823fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2022027859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2022027859
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1230756593
Short name T730
Test name
Test status
Simulation time 17693160681 ps
CPU time 291.59 seconds
Started Mar 21 02:13:13 PM PDT 24
Finished Mar 21 02:18:04 PM PDT 24
Peak memory 239296 kb
Host smart-7e68c18a-cccd-4c49-8fb1-c283d4ab3cfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1230756593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1230756593
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1802665474
Short name T759
Test name
Test status
Simulation time 60861481474 ps
CPU time 243.86 seconds
Started Mar 21 02:12:54 PM PDT 24
Finished Mar 21 02:16:58 PM PDT 24
Peak memory 236540 kb
Host smart-7e7ff13c-6919-4537-9c7c-916e0fb536c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1802665474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1802665474
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2155801329
Short name T749
Test name
Test status
Simulation time 142520664 ps
CPU time 6.59 seconds
Started Mar 21 02:12:54 PM PDT 24
Finished Mar 21 02:13:00 PM PDT 24
Peak memory 240280 kb
Host smart-b566ceee-4faa-4839-a777-0e95da4c6637
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2155801329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2155801329
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2407795363
Short name T761
Test name
Test status
Simulation time 633900456 ps
CPU time 9.09 seconds
Started Mar 21 02:13:13 PM PDT 24
Finished Mar 21 02:13:22 PM PDT 24
Peak memory 253172 kb
Host smart-eda2ab51-4be5-4466-b5bd-0e425bae36f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407795363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2407795363
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2662070441
Short name T763
Test name
Test status
Simulation time 66641015 ps
CPU time 5.28 seconds
Started Mar 21 02:12:54 PM PDT 24
Finished Mar 21 02:12:59 PM PDT 24
Peak memory 240248 kb
Host smart-bfc32c3d-8cd9-41b6-8325-977704ca19b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2662070441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2662070441
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2592196900
Short name T716
Test name
Test status
Simulation time 8486758 ps
CPU time 1.61 seconds
Started Mar 21 02:12:55 PM PDT 24
Finished Mar 21 02:12:57 PM PDT 24
Peak memory 235828 kb
Host smart-6a1c3e91-0543-4d36-8e4e-8e78a86830fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2592196900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2592196900
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1905571227
Short name T185
Test name
Test status
Simulation time 2426110489 ps
CPU time 47.28 seconds
Started Mar 21 02:13:08 PM PDT 24
Finished Mar 21 02:13:55 PM PDT 24
Peak memory 244076 kb
Host smart-18c41a22-11d9-4407-9e97-ad4a71876c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1905571227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1905571227
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2289722659
Short name T710
Test name
Test status
Simulation time 101210703 ps
CPU time 14.31 seconds
Started Mar 21 02:12:53 PM PDT 24
Finished Mar 21 02:13:08 PM PDT 24
Peak memory 248056 kb
Host smart-b4425ef5-5090-40b9-8721-50475bb3f6c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2289722659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2289722659
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3208740146
Short name T720
Test name
Test status
Simulation time 596024341 ps
CPU time 89.61 seconds
Started Mar 21 02:13:09 PM PDT 24
Finished Mar 21 02:14:39 PM PDT 24
Peak memory 236624 kb
Host smart-29df511f-1725-4d00-ace8-acafd4a015a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3208740146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3208740146
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1622284970
Short name T722
Test name
Test status
Simulation time 10205605593 ps
CPU time 118.38 seconds
Started Mar 21 02:13:10 PM PDT 24
Finished Mar 21 02:15:08 PM PDT 24
Peak memory 236688 kb
Host smart-c16702db-80b7-467d-b0ac-6ab979276b3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1622284970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1622284970
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2101278362
Short name T736
Test name
Test status
Simulation time 484549635 ps
CPU time 4.93 seconds
Started Mar 21 02:13:10 PM PDT 24
Finished Mar 21 02:13:15 PM PDT 24
Peak memory 240292 kb
Host smart-7bdeccdb-fd0f-49eb-aa75-0fbbb9aeb08b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2101278362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2101278362
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2877866504
Short name T201
Test name
Test status
Simulation time 154203371 ps
CPU time 12.12 seconds
Started Mar 21 02:13:08 PM PDT 24
Finished Mar 21 02:13:20 PM PDT 24
Peak memory 250724 kb
Host smart-56c0bf89-127e-42f5-bc5c-c12a414a765b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877866504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2877866504
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2828066629
Short name T244
Test name
Test status
Simulation time 65855012 ps
CPU time 5.98 seconds
Started Mar 21 02:13:09 PM PDT 24
Finished Mar 21 02:13:15 PM PDT 24
Peak memory 236596 kb
Host smart-96d5e615-631d-4094-af01-4e6a1492118c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2828066629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2828066629
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2936878139
Short name T746
Test name
Test status
Simulation time 1068170641 ps
CPU time 41.75 seconds
Started Mar 21 02:13:08 PM PDT 24
Finished Mar 21 02:13:50 PM PDT 24
Peak memory 244832 kb
Host smart-9678b483-d4e3-4468-bd7d-8c2decb5974f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2936878139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2936878139
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4062008657
Short name T133
Test name
Test status
Simulation time 6950459147 ps
CPU time 239.23 seconds
Started Mar 21 02:13:08 PM PDT 24
Finished Mar 21 02:17:08 PM PDT 24
Peak memory 265156 kb
Host smart-acd29a5b-21e8-4c27-9b36-256723fc86eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4062008657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.4062008657
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3115394497
Short name T146
Test name
Test status
Simulation time 48393267224 ps
CPU time 478.46 seconds
Started Mar 21 02:13:13 PM PDT 24
Finished Mar 21 02:21:12 PM PDT 24
Peak memory 265416 kb
Host smart-97c59987-d400-4b35-b476-b31635adc556
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115394497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3115394497
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.282548669
Short name T248
Test name
Test status
Simulation time 312846502 ps
CPU time 23.37 seconds
Started Mar 21 02:13:09 PM PDT 24
Finished Mar 21 02:13:33 PM PDT 24
Peak memory 247848 kb
Host smart-5b996121-fa11-425c-9e24-92fae303b3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282548669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.282548669
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.423564513
Short name T765
Test name
Test status
Simulation time 383903748 ps
CPU time 8.37 seconds
Started Mar 21 02:14:30 PM PDT 24
Finished Mar 21 02:14:39 PM PDT 24
Peak memory 239308 kb
Host smart-9bc2726a-115a-4017-858a-1c0760154ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423564513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.423564513
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1666778248
Short name T822
Test name
Test status
Simulation time 52164542 ps
CPU time 4.5 seconds
Started Mar 21 02:14:34 PM PDT 24
Finished Mar 21 02:14:39 PM PDT 24
Peak memory 235828 kb
Host smart-e54313d4-f12a-4dfa-89d2-9c6ebf3ccc72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1666778248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1666778248
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.147320438
Short name T734
Test name
Test status
Simulation time 8789651 ps
CPU time 1.36 seconds
Started Mar 21 02:14:32 PM PDT 24
Finished Mar 21 02:14:34 PM PDT 24
Peak memory 234808 kb
Host smart-d65c0e02-e3aa-4fa3-a664-1ab79e2e5fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=147320438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.147320438
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3263728842
Short name T742
Test name
Test status
Simulation time 352220848 ps
CPU time 11.38 seconds
Started Mar 21 02:14:34 PM PDT 24
Finished Mar 21 02:14:46 PM PDT 24
Peak memory 248632 kb
Host smart-303fb607-311d-4d20-82dd-daaca06e0a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3263728842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3263728842
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1886429029
Short name T143
Test name
Test status
Simulation time 5859861540 ps
CPU time 709.15 seconds
Started Mar 21 02:14:20 PM PDT 24
Finished Mar 21 02:26:09 PM PDT 24
Peak memory 265172 kb
Host smart-2f61f28b-1145-4426-95ce-9cdb2cad8d33
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886429029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1886429029
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2180901157
Short name T712
Test name
Test status
Simulation time 331573436 ps
CPU time 7.53 seconds
Started Mar 21 02:14:21 PM PDT 24
Finished Mar 21 02:14:29 PM PDT 24
Peak memory 249616 kb
Host smart-ea0bea6c-2144-470f-95a0-64e4b6b9492e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2180901157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2180901157
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.285794004
Short name T757
Test name
Test status
Simulation time 85264182 ps
CPU time 3.92 seconds
Started Mar 21 02:14:31 PM PDT 24
Finished Mar 21 02:14:36 PM PDT 24
Peak memory 248464 kb
Host smart-37d97a52-3e74-475d-b9c9-ff12e920d6ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285794004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.285794004
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2172879704
Short name T745
Test name
Test status
Simulation time 66226331 ps
CPU time 3.74 seconds
Started Mar 21 02:14:30 PM PDT 24
Finished Mar 21 02:14:34 PM PDT 24
Peak memory 236560 kb
Host smart-77c39f1c-6503-4be9-966a-575190b9abfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2172879704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2172879704
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.645581377
Short name T777
Test name
Test status
Simulation time 10724100 ps
CPU time 1.74 seconds
Started Mar 21 02:14:30 PM PDT 24
Finished Mar 21 02:14:32 PM PDT 24
Peak memory 235844 kb
Host smart-69f5f581-c792-4799-a3b4-6d6b1a6238f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645581377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.645581377
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.694407156
Short name T826
Test name
Test status
Simulation time 314337403 ps
CPU time 20.82 seconds
Started Mar 21 02:14:33 PM PDT 24
Finished Mar 21 02:14:54 PM PDT 24
Peak memory 240344 kb
Host smart-e1811f4a-e712-4c7f-a472-3af869608e6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=694407156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.694407156
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.4262957435
Short name T782
Test name
Test status
Simulation time 266212535 ps
CPU time 9.83 seconds
Started Mar 21 02:14:31 PM PDT 24
Finished Mar 21 02:14:42 PM PDT 24
Peak memory 248660 kb
Host smart-7d0c247f-60ae-47b6-af3d-53a009ce6de0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4262957435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.4262957435
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1719255893
Short name T751
Test name
Test status
Simulation time 546327822 ps
CPU time 10.13 seconds
Started Mar 21 02:14:43 PM PDT 24
Finished Mar 21 02:14:53 PM PDT 24
Peak memory 240384 kb
Host smart-e69da73f-fefb-4310-a82c-225bae57645c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719255893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1719255893
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4010770348
Short name T797
Test name
Test status
Simulation time 215078022 ps
CPU time 6 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:14:50 PM PDT 24
Peak memory 236628 kb
Host smart-779ed974-4f54-4994-9500-18cf16e54acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4010770348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4010770348
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.369658589
Short name T756
Test name
Test status
Simulation time 8051296 ps
CPU time 1.51 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:14:46 PM PDT 24
Peak memory 235816 kb
Host smart-3b26acd8-c015-4352-84e1-32102527f440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=369658589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.369658589
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3283750042
Short name T723
Test name
Test status
Simulation time 501239888 ps
CPU time 20.39 seconds
Started Mar 21 02:14:42 PM PDT 24
Finished Mar 21 02:15:03 PM PDT 24
Peak memory 240360 kb
Host smart-0413ef28-ff01-4ed6-be2f-031fe3f26144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3283750042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3283750042
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2708178141
Short name T139
Test name
Test status
Simulation time 2500777892 ps
CPU time 195.61 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:18:00 PM PDT 24
Peak memory 265152 kb
Host smart-f93a481b-698f-4fd8-8523-7fdd55840757
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2708178141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2708178141
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3008513443
Short name T142
Test name
Test status
Simulation time 3038179329 ps
CPU time 338.21 seconds
Started Mar 21 02:14:33 PM PDT 24
Finished Mar 21 02:20:11 PM PDT 24
Peak memory 265212 kb
Host smart-e0cc4d4e-e306-4020-9544-c07e3b45ff68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008513443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3008513443
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.601980955
Short name T796
Test name
Test status
Simulation time 51380631 ps
CPU time 7.48 seconds
Started Mar 21 02:14:46 PM PDT 24
Finished Mar 21 02:14:53 PM PDT 24
Peak memory 252480 kb
Host smart-1ef1cf2a-b876-47c2-b921-54201d9a3a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=601980955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.601980955
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1992520970
Short name T818
Test name
Test status
Simulation time 487188215 ps
CPU time 10.35 seconds
Started Mar 21 02:15:01 PM PDT 24
Finished Mar 21 02:15:12 PM PDT 24
Peak memory 240372 kb
Host smart-8d63702c-b089-4c84-9d2d-c3dd4e3d5704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992520970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1992520970
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.757524716
Short name T348
Test name
Test status
Simulation time 373484294 ps
CPU time 7.31 seconds
Started Mar 21 02:14:46 PM PDT 24
Finished Mar 21 02:14:53 PM PDT 24
Peak memory 240232 kb
Host smart-f3eb2664-ec1f-4f82-aac1-0832d5e22a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=757524716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.757524716
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2819437125
Short name T737
Test name
Test status
Simulation time 18008197 ps
CPU time 1.34 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:14:46 PM PDT 24
Peak memory 236700 kb
Host smart-40b78402-32b2-4910-857d-439fd7f516d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2819437125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2819437125
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.706648659
Short name T771
Test name
Test status
Simulation time 345955565 ps
CPU time 21.68 seconds
Started Mar 21 02:14:59 PM PDT 24
Finished Mar 21 02:15:21 PM PDT 24
Peak memory 244852 kb
Host smart-70404d43-70d6-489a-8445-ae7deed65b46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=706648659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.706648659
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3970666003
Short name T354
Test name
Test status
Simulation time 63892548850 ps
CPU time 1270.86 seconds
Started Mar 21 02:14:47 PM PDT 24
Finished Mar 21 02:35:58 PM PDT 24
Peak memory 265232 kb
Host smart-1afe2a78-24eb-4fd3-b019-a172587886c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970666003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3970666003
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3487119241
Short name T819
Test name
Test status
Simulation time 156016608 ps
CPU time 6.61 seconds
Started Mar 21 02:14:44 PM PDT 24
Finished Mar 21 02:14:51 PM PDT 24
Peak memory 240404 kb
Host smart-bb3c8e64-fd49-44a1-89d6-f8750ba47dec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3487119241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3487119241
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.931714366
Short name T351
Test name
Test status
Simulation time 243650903 ps
CPU time 11.68 seconds
Started Mar 21 02:15:00 PM PDT 24
Finished Mar 21 02:15:11 PM PDT 24
Peak memory 256796 kb
Host smart-2691576d-cffc-4cf3-8808-d581638b7e4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931714366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.931714366
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3108104503
Short name T741
Test name
Test status
Simulation time 29669056 ps
CPU time 3.19 seconds
Started Mar 21 02:15:00 PM PDT 24
Finished Mar 21 02:15:04 PM PDT 24
Peak memory 235712 kb
Host smart-b9d231a1-156a-4ca6-aea7-a3b35cc4e5d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3108104503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3108104503
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2185737284
Short name T758
Test name
Test status
Simulation time 22269436 ps
CPU time 1.27 seconds
Started Mar 21 02:14:57 PM PDT 24
Finished Mar 21 02:14:59 PM PDT 24
Peak memory 236564 kb
Host smart-a073ccb4-db44-45d3-b0d7-65996768ab4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2185737284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2185737284
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3037681714
Short name T186
Test name
Test status
Simulation time 170582155 ps
CPU time 26.32 seconds
Started Mar 21 02:14:59 PM PDT 24
Finished Mar 21 02:15:26 PM PDT 24
Peak memory 248508 kb
Host smart-e9a2074d-46e1-4c92-9434-cfa056373023
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3037681714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3037681714
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2172677507
Short name T119
Test name
Test status
Simulation time 6810728229 ps
CPU time 133.19 seconds
Started Mar 21 02:14:57 PM PDT 24
Finished Mar 21 02:17:10 PM PDT 24
Peak memory 265172 kb
Host smart-901a3b8c-6da2-456e-9c6f-2aa52d2ec0dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2172677507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2172677507
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3505480099
Short name T355
Test name
Test status
Simulation time 7837677526 ps
CPU time 421.04 seconds
Started Mar 21 02:14:59 PM PDT 24
Finished Mar 21 02:22:00 PM PDT 24
Peak memory 265180 kb
Host smart-aedbed30-a0c2-4a1d-8bb7-a336fbde0820
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505480099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3505480099
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.394885418
Short name T246
Test name
Test status
Simulation time 817859688 ps
CPU time 14.13 seconds
Started Mar 21 02:14:58 PM PDT 24
Finished Mar 21 02:15:12 PM PDT 24
Peak memory 248268 kb
Host smart-c0fe643c-58d3-496f-bcd8-52f0466efeae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=394885418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.394885418
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.261359909
Short name T349
Test name
Test status
Simulation time 92993293 ps
CPU time 5.62 seconds
Started Mar 21 02:15:00 PM PDT 24
Finished Mar 21 02:15:06 PM PDT 24
Peak memory 240400 kb
Host smart-18355028-5ab4-4c1b-b38e-abb77e3e3f7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261359909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.261359909
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3485399483
Short name T352
Test name
Test status
Simulation time 48029304 ps
CPU time 4.74 seconds
Started Mar 21 02:15:01 PM PDT 24
Finished Mar 21 02:15:06 PM PDT 24
Peak memory 236612 kb
Host smart-8f81ec82-3c63-455a-9ee3-75506eb4f070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3485399483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3485399483
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.935064517
Short name T774
Test name
Test status
Simulation time 7715743 ps
CPU time 1.33 seconds
Started Mar 21 02:15:00 PM PDT 24
Finished Mar 21 02:15:01 PM PDT 24
Peak memory 236668 kb
Host smart-116971ce-d244-4b79-bbee-c70d1afedd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=935064517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.935064517
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3018420641
Short name T190
Test name
Test status
Simulation time 2833774110 ps
CPU time 24.43 seconds
Started Mar 21 02:15:00 PM PDT 24
Finished Mar 21 02:15:24 PM PDT 24
Peak memory 240428 kb
Host smart-79cd55b1-a587-41c4-add5-fc7069da94af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3018420641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3018420641
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2621524516
Short name T128
Test name
Test status
Simulation time 4580413917 ps
CPU time 341.88 seconds
Started Mar 21 02:14:59 PM PDT 24
Finished Mar 21 02:20:41 PM PDT 24
Peak memory 265204 kb
Host smart-20827799-28e4-4a0d-8466-5062bbb52c20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2621524516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2621524516
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1987296495
Short name T781
Test name
Test status
Simulation time 176855756 ps
CPU time 12.9 seconds
Started Mar 21 02:14:57 PM PDT 24
Finished Mar 21 02:15:10 PM PDT 24
Peak memory 247360 kb
Host smart-b2657393-b7be-450d-b745-475921970b69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987296495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1987296495
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1689639860
Short name T740
Test name
Test status
Simulation time 99474877 ps
CPU time 8.58 seconds
Started Mar 21 02:15:18 PM PDT 24
Finished Mar 21 02:15:27 PM PDT 24
Peak memory 238516 kb
Host smart-d416426e-45d2-426f-ae97-3ca2205f9fae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689639860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1689639860
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.770915146
Short name T786
Test name
Test status
Simulation time 39707524 ps
CPU time 3.73 seconds
Started Mar 21 02:15:16 PM PDT 24
Finished Mar 21 02:15:20 PM PDT 24
Peak memory 240248 kb
Host smart-3d05d479-f487-48a4-9068-44a07e9e4158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=770915146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.770915146
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.411142316
Short name T806
Test name
Test status
Simulation time 12252661 ps
CPU time 1.76 seconds
Started Mar 21 02:15:26 PM PDT 24
Finished Mar 21 02:15:28 PM PDT 24
Peak memory 235840 kb
Host smart-4ea08b73-ce95-4fa5-a5c9-dd7b00963a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=411142316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.411142316
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.59603265
Short name T810
Test name
Test status
Simulation time 503874691 ps
CPU time 21.38 seconds
Started Mar 21 02:15:17 PM PDT 24
Finished Mar 21 02:15:39 PM PDT 24
Peak memory 244036 kb
Host smart-f61e11dc-4715-400c-be60-7be9981dc4c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=59603265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outs
tanding.59603265
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2006973512
Short name T125
Test name
Test status
Simulation time 8685855527 ps
CPU time 320.66 seconds
Started Mar 21 02:15:00 PM PDT 24
Finished Mar 21 02:20:21 PM PDT 24
Peak memory 265212 kb
Host smart-cc552610-36ad-4d6b-86f3-a7481682c2ad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006973512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2006973512
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1190074763
Short name T732
Test name
Test status
Simulation time 108140480 ps
CPU time 3.69 seconds
Started Mar 21 02:15:19 PM PDT 24
Finished Mar 21 02:15:23 PM PDT 24
Peak memory 248320 kb
Host smart-54343b30-fb58-4b3f-a138-60a6ab234904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1190074763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1190074763
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2270417805
Short name T800
Test name
Test status
Simulation time 77755352 ps
CPU time 7.08 seconds
Started Mar 21 02:15:27 PM PDT 24
Finished Mar 21 02:15:34 PM PDT 24
Peak memory 239352 kb
Host smart-b8373151-b4fe-46d6-b4ee-59ab19619354
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270417805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2270417805
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1292390094
Short name T726
Test name
Test status
Simulation time 522713735 ps
CPU time 8.32 seconds
Started Mar 21 02:15:28 PM PDT 24
Finished Mar 21 02:15:36 PM PDT 24
Peak memory 240268 kb
Host smart-be147d5c-5470-47ae-9991-6a85d6900e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1292390094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1292390094
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1918986680
Short name T743
Test name
Test status
Simulation time 8938014 ps
CPU time 1.5 seconds
Started Mar 21 02:15:28 PM PDT 24
Finished Mar 21 02:15:30 PM PDT 24
Peak memory 234820 kb
Host smart-a6066a9c-0ebc-4a99-9922-35fa902d36db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1918986680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1918986680
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1101648826
Short name T762
Test name
Test status
Simulation time 986807359 ps
CPU time 34.68 seconds
Started Mar 21 02:15:26 PM PDT 24
Finished Mar 21 02:16:02 PM PDT 24
Peak memory 243992 kb
Host smart-f432810d-27ef-40f3-8640-8b87bb265352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1101648826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1101648826
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4241178552
Short name T791
Test name
Test status
Simulation time 3210941353 ps
CPU time 112.74 seconds
Started Mar 21 02:15:18 PM PDT 24
Finished Mar 21 02:17:11 PM PDT 24
Peak memory 265164 kb
Host smart-2713ab75-025d-48a8-a0a5-0e93384545fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4241178552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4241178552
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1968759842
Short name T141
Test name
Test status
Simulation time 35709303360 ps
CPU time 583.29 seconds
Started Mar 21 02:15:17 PM PDT 24
Finished Mar 21 02:25:01 PM PDT 24
Peak memory 265200 kb
Host smart-f67f7a92-5155-4759-a67f-8c7a5b19ec26
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968759842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1968759842
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3101928194
Short name T713
Test name
Test status
Simulation time 883605941 ps
CPU time 18.96 seconds
Started Mar 21 02:15:25 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 248368 kb
Host smart-fbfda646-2ecd-46f5-931d-e47caf655a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3101928194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3101928194
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3783390061
Short name T148
Test name
Test status
Simulation time 83100755 ps
CPU time 4.55 seconds
Started Mar 21 02:15:28 PM PDT 24
Finished Mar 21 02:15:32 PM PDT 24
Peak memory 237220 kb
Host smart-d95f703b-3ff8-4a8c-995f-45abd504345e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3783390061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3783390061
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3973151576
Short name T739
Test name
Test status
Simulation time 118507609 ps
CPU time 8.72 seconds
Started Mar 21 02:15:30 PM PDT 24
Finished Mar 21 02:15:39 PM PDT 24
Peak memory 238964 kb
Host smart-0b19df64-a250-4778-a637-ec8506ae669f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973151576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3973151576
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2296982633
Short name T772
Test name
Test status
Simulation time 112524481 ps
CPU time 4.46 seconds
Started Mar 21 02:15:32 PM PDT 24
Finished Mar 21 02:15:37 PM PDT 24
Peak memory 235748 kb
Host smart-71e814f6-88ec-46cb-a6c2-bcf5e41e32e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2296982633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2296982633
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3646759300
Short name T798
Test name
Test status
Simulation time 8215574 ps
CPU time 1.57 seconds
Started Mar 21 02:15:36 PM PDT 24
Finished Mar 21 02:15:39 PM PDT 24
Peak memory 235812 kb
Host smart-e10083df-928f-49f1-b6da-b4472f79fd2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3646759300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3646759300
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.519831090
Short name T754
Test name
Test status
Simulation time 1779969697 ps
CPU time 57.94 seconds
Started Mar 21 02:15:31 PM PDT 24
Finished Mar 21 02:16:29 PM PDT 24
Peak memory 248556 kb
Host smart-3757afc1-708e-4a76-bee4-f091fc31ace5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=519831090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.519831090
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.835827017
Short name T809
Test name
Test status
Simulation time 816770386 ps
CPU time 105.74 seconds
Started Mar 21 02:15:30 PM PDT 24
Finished Mar 21 02:17:15 PM PDT 24
Peak memory 256880 kb
Host smart-05a6c700-ec22-4e43-9718-aad0cd56c134
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=835827017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.835827017
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.732715039
Short name T715
Test name
Test status
Simulation time 181113381 ps
CPU time 11.42 seconds
Started Mar 21 02:15:31 PM PDT 24
Finished Mar 21 02:15:43 PM PDT 24
Peak memory 248740 kb
Host smart-00e83a24-e4df-4815-ad2f-330e00cc7a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=732715039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.732715039
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1072163275
Short name T807
Test name
Test status
Simulation time 114251230 ps
CPU time 9.55 seconds
Started Mar 21 02:15:33 PM PDT 24
Finished Mar 21 02:15:43 PM PDT 24
Peak memory 238832 kb
Host smart-64fef195-32d8-426d-b3c9-bd4c6d14735c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072163275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1072163275
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1767617453
Short name T170
Test name
Test status
Simulation time 21728105 ps
CPU time 3.59 seconds
Started Mar 21 02:15:38 PM PDT 24
Finished Mar 21 02:15:42 PM PDT 24
Peak memory 235736 kb
Host smart-e0cd0ce2-53cc-4a1e-8951-5a6637acd230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1767617453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1767617453
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1399727111
Short name T735
Test name
Test status
Simulation time 9898366 ps
CPU time 1.33 seconds
Started Mar 21 02:15:31 PM PDT 24
Finished Mar 21 02:15:33 PM PDT 24
Peak memory 236776 kb
Host smart-8fedcd2d-b6f6-4f5d-b797-3d24c92cf68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1399727111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1399727111
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1524058570
Short name T792
Test name
Test status
Simulation time 531103975 ps
CPU time 37.59 seconds
Started Mar 21 02:15:32 PM PDT 24
Finished Mar 21 02:16:09 PM PDT 24
Peak memory 244888 kb
Host smart-fdc5a1c9-cbd4-4d5c-8d6a-f3514dfa6754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1524058570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1524058570
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2133939156
Short name T114
Test name
Test status
Simulation time 20132946676 ps
CPU time 252.94 seconds
Started Mar 21 02:15:28 PM PDT 24
Finished Mar 21 02:19:41 PM PDT 24
Peak memory 272496 kb
Host smart-1c894e59-090e-4f93-afc7-d7c1d0300a99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2133939156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2133939156
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3067858947
Short name T140
Test name
Test status
Simulation time 16775993629 ps
CPU time 570.14 seconds
Started Mar 21 02:15:34 PM PDT 24
Finished Mar 21 02:25:04 PM PDT 24
Peak memory 272380 kb
Host smart-3c483c9f-e7a0-45f2-badd-361bbc489dfc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067858947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3067858947
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4269917988
Short name T789
Test name
Test status
Simulation time 386886105 ps
CPU time 9.41 seconds
Started Mar 21 02:15:35 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 250340 kb
Host smart-b3732b6d-bb12-499f-9836-c87030deb7db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4269917988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4269917988
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1359229030
Short name T149
Test name
Test status
Simulation time 31480817 ps
CPU time 2.33 seconds
Started Mar 21 02:15:36 PM PDT 24
Finished Mar 21 02:15:40 PM PDT 24
Peak memory 236680 kb
Host smart-a29f6c26-930a-472d-b492-ea45ff551a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1359229030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1359229030
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.92686183
Short name T808
Test name
Test status
Simulation time 1187005432 ps
CPU time 79.91 seconds
Started Mar 21 02:13:25 PM PDT 24
Finished Mar 21 02:14:45 PM PDT 24
Peak memory 236608 kb
Host smart-08fb92be-b13a-4c59-843b-f7fc35a538c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=92686183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.92686183
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.707909620
Short name T769
Test name
Test status
Simulation time 35546870628 ps
CPU time 557.11 seconds
Started Mar 21 02:13:22 PM PDT 24
Finished Mar 21 02:22:39 PM PDT 24
Peak memory 240360 kb
Host smart-d1e4ebac-2f58-4999-b5b7-f0da72bd1999
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=707909620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.707909620
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3901441023
Short name T152
Test name
Test status
Simulation time 74785327 ps
CPU time 7.65 seconds
Started Mar 21 02:13:18 PM PDT 24
Finished Mar 21 02:13:25 PM PDT 24
Peak memory 240244 kb
Host smart-d8236a25-224e-48d5-a77a-abf19ca7faee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3901441023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3901441023
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1049551746
Short name T350
Test name
Test status
Simulation time 1754771636 ps
CPU time 9.18 seconds
Started Mar 21 02:13:17 PM PDT 24
Finished Mar 21 02:13:27 PM PDT 24
Peak memory 237144 kb
Host smart-b432c381-736b-455c-8155-dea70c6fc8be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049551746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1049551746
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3461270717
Short name T750
Test name
Test status
Simulation time 107539953 ps
CPU time 6.49 seconds
Started Mar 21 02:13:20 PM PDT 24
Finished Mar 21 02:13:27 PM PDT 24
Peak memory 236596 kb
Host smart-6ac9968d-e3c6-4d7a-b171-285cf5b9b005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3461270717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3461270717
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1380791423
Short name T748
Test name
Test status
Simulation time 16454841 ps
CPU time 1.23 seconds
Started Mar 21 02:13:19 PM PDT 24
Finished Mar 21 02:13:20 PM PDT 24
Peak memory 235880 kb
Host smart-b73b603a-bdfd-4cda-96aa-d1809ede00f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1380791423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1380791423
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1521312145
Short name T799
Test name
Test status
Simulation time 1853684258 ps
CPU time 48.13 seconds
Started Mar 21 02:13:19 PM PDT 24
Finished Mar 21 02:14:07 PM PDT 24
Peak memory 244856 kb
Host smart-37451123-bc3f-4a14-b004-7459007196b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1521312145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1521312145
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4160894126
Short name T115
Test name
Test status
Simulation time 1252019075 ps
CPU time 107.75 seconds
Started Mar 21 02:13:09 PM PDT 24
Finished Mar 21 02:14:57 PM PDT 24
Peak memory 255476 kb
Host smart-f995df50-91b3-43b0-8d64-2289463cb55f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4160894126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4160894126
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3764720366
Short name T137
Test name
Test status
Simulation time 23608423092 ps
CPU time 986.98 seconds
Started Mar 21 02:13:07 PM PDT 24
Finished Mar 21 02:29:34 PM PDT 24
Peak memory 265220 kb
Host smart-0f00afe0-7043-431e-afb9-9b336a8807f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764720366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3764720366
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.311263637
Short name T727
Test name
Test status
Simulation time 137231801 ps
CPU time 13.06 seconds
Started Mar 21 02:13:21 PM PDT 24
Finished Mar 21 02:13:34 PM PDT 24
Peak memory 248608 kb
Host smart-22f3d73a-7752-4a9e-b49e-0c90835ba1b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311263637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.311263637
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.927617501
Short name T825
Test name
Test status
Simulation time 13262318 ps
CPU time 1.37 seconds
Started Mar 21 02:15:32 PM PDT 24
Finished Mar 21 02:15:34 PM PDT 24
Peak memory 235752 kb
Host smart-133ec303-9091-4e02-a895-75877a924817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=927617501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.927617501
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2997776718
Short name T729
Test name
Test status
Simulation time 42542691 ps
CPU time 1.39 seconds
Started Mar 21 02:15:38 PM PDT 24
Finished Mar 21 02:15:40 PM PDT 24
Peak memory 236684 kb
Host smart-253701fb-ed9b-46b4-98d8-6e69ec2cc4ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2997776718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2997776718
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1727067954
Short name T780
Test name
Test status
Simulation time 10422684 ps
CPU time 1.34 seconds
Started Mar 21 02:15:30 PM PDT 24
Finished Mar 21 02:15:32 PM PDT 24
Peak memory 234800 kb
Host smart-e93cd2a9-16b7-418c-84b9-654fafe29c35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1727067954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1727067954
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1440935870
Short name T813
Test name
Test status
Simulation time 8010402 ps
CPU time 1.53 seconds
Started Mar 21 02:15:30 PM PDT 24
Finished Mar 21 02:15:32 PM PDT 24
Peak memory 236700 kb
Host smart-d78b1357-5de9-4af7-b8a5-2b7fd99520a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1440935870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1440935870
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.61330739
Short name T788
Test name
Test status
Simulation time 10925995 ps
CPU time 1.64 seconds
Started Mar 21 02:15:31 PM PDT 24
Finished Mar 21 02:15:33 PM PDT 24
Peak memory 236680 kb
Host smart-9be0e7b5-8ab8-4bd8-beb6-b866d33b642f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=61330739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.61330739
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3453457579
Short name T776
Test name
Test status
Simulation time 16080769 ps
CPU time 1.33 seconds
Started Mar 21 02:15:37 PM PDT 24
Finished Mar 21 02:15:40 PM PDT 24
Peak memory 235820 kb
Host smart-d8683e29-6141-442a-9261-33bb523569fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3453457579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3453457579
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3469091451
Short name T768
Test name
Test status
Simulation time 33853578 ps
CPU time 1.21 seconds
Started Mar 21 02:15:31 PM PDT 24
Finished Mar 21 02:15:32 PM PDT 24
Peak memory 235788 kb
Host smart-d0febdcd-c3dd-4303-9ec4-749f789bcbef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3469091451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3469091451
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.943610761
Short name T794
Test name
Test status
Simulation time 10069342 ps
CPU time 1.22 seconds
Started Mar 21 02:15:32 PM PDT 24
Finished Mar 21 02:15:34 PM PDT 24
Peak memory 236616 kb
Host smart-c74b9ba5-fe46-4bd0-a8d3-7c98e69eaa2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=943610761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.943610761
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2612110345
Short name T773
Test name
Test status
Simulation time 8412360 ps
CPU time 1.63 seconds
Started Mar 21 02:15:32 PM PDT 24
Finished Mar 21 02:15:33 PM PDT 24
Peak memory 236688 kb
Host smart-ace4d90e-1ae5-4bf2-b683-d42cd94b60c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2612110345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2612110345
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3928305877
Short name T187
Test name
Test status
Simulation time 7557238690 ps
CPU time 327.46 seconds
Started Mar 21 02:13:32 PM PDT 24
Finished Mar 21 02:19:00 PM PDT 24
Peak memory 240432 kb
Host smart-d6c51a22-58fe-48fa-910d-38dab262c991
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3928305877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3928305877
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.46487832
Short name T760
Test name
Test status
Simulation time 1704526772 ps
CPU time 180.91 seconds
Started Mar 21 02:13:31 PM PDT 24
Finished Mar 21 02:16:32 PM PDT 24
Peak memory 235764 kb
Host smart-b2b3e691-bf9d-4c0e-858a-58dc0a9e6c03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=46487832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.46487832
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2866773262
Short name T824
Test name
Test status
Simulation time 100511720 ps
CPU time 8.66 seconds
Started Mar 21 02:13:29 PM PDT 24
Finished Mar 21 02:13:38 PM PDT 24
Peak memory 240328 kb
Host smart-eabdfb69-7de8-4dd3-bf58-8f1e28d32f1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2866773262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2866773262
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1770955943
Short name T802
Test name
Test status
Simulation time 53061199 ps
CPU time 8.96 seconds
Started Mar 21 02:13:30 PM PDT 24
Finished Mar 21 02:13:39 PM PDT 24
Peak memory 250808 kb
Host smart-8e541dd8-c556-409f-b4da-42b9c944f299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770955943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1770955943
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.906507645
Short name T821
Test name
Test status
Simulation time 242202792 ps
CPU time 5.94 seconds
Started Mar 21 02:13:30 PM PDT 24
Finished Mar 21 02:13:36 PM PDT 24
Peak memory 236608 kb
Host smart-f454ce94-5b3b-4a62-ae1d-e43cbe5703ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=906507645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.906507645
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1401408137
Short name T770
Test name
Test status
Simulation time 13395091 ps
CPU time 1.38 seconds
Started Mar 21 02:13:28 PM PDT 24
Finished Mar 21 02:13:29 PM PDT 24
Peak memory 236688 kb
Host smart-f3f29c12-2a21-4f1d-b567-655c01012e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1401408137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1401408137
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2928810197
Short name T169
Test name
Test status
Simulation time 1010487738 ps
CPU time 43.92 seconds
Started Mar 21 02:13:29 PM PDT 24
Finished Mar 21 02:14:13 PM PDT 24
Peak memory 244888 kb
Host smart-b38e30d9-29c2-4cf4-be64-ce792557078c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928810197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2928810197
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2456865992
Short name T764
Test name
Test status
Simulation time 278080246 ps
CPU time 16.63 seconds
Started Mar 21 02:13:31 PM PDT 24
Finished Mar 21 02:13:49 PM PDT 24
Peak memory 248604 kb
Host smart-bc35a8d3-8ca4-4e04-a3ab-59f21759be0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2456865992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2456865992
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3384868236
Short name T725
Test name
Test status
Simulation time 16931371 ps
CPU time 1.73 seconds
Started Mar 21 02:15:37 PM PDT 24
Finished Mar 21 02:15:39 PM PDT 24
Peak memory 236684 kb
Host smart-f551550f-c5ca-4d56-a82e-969b25b72551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3384868236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3384868236
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3080148097
Short name T793
Test name
Test status
Simulation time 14850083 ps
CPU time 1.31 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 234740 kb
Host smart-26ed2fae-8a77-4f83-b810-120401b1ddd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3080148097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3080148097
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.402822866
Short name T803
Test name
Test status
Simulation time 11983114 ps
CPU time 1.26 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 235772 kb
Host smart-134726a1-5bb8-4278-9311-0cddda6c3301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402822866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.402822866
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3244993652
Short name T718
Test name
Test status
Simulation time 10804330 ps
CPU time 1.33 seconds
Started Mar 21 02:15:47 PM PDT 24
Finished Mar 21 02:15:50 PM PDT 24
Peak memory 235828 kb
Host smart-78479d77-ac73-4896-9341-bfd77fcf0c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3244993652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3244993652
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1542865978
Short name T778
Test name
Test status
Simulation time 41097335 ps
CPU time 1.33 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 234796 kb
Host smart-5e378c5c-9bee-47c9-9d54-2aa6162743c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542865978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1542865978
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2313381203
Short name T346
Test name
Test status
Simulation time 11558174 ps
CPU time 1.31 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 235812 kb
Host smart-a7a90ac1-1136-4a49-b505-8dfa71e1142e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2313381203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2313381203
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2219913381
Short name T814
Test name
Test status
Simulation time 6681398 ps
CPU time 1.48 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 235820 kb
Host smart-9f718d11-7fd2-47c7-886d-83aa54374e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2219913381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2219913381
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.895324952
Short name T801
Test name
Test status
Simulation time 32414281 ps
CPU time 1.35 seconds
Started Mar 21 02:15:43 PM PDT 24
Finished Mar 21 02:15:46 PM PDT 24
Peak memory 236688 kb
Host smart-d79d8b85-514a-4a37-992a-2a01b8648530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=895324952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.895324952
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2999325663
Short name T243
Test name
Test status
Simulation time 12296359 ps
CPU time 1.28 seconds
Started Mar 21 02:15:45 PM PDT 24
Finished Mar 21 02:15:47 PM PDT 24
Peak memory 236692 kb
Host smart-6c0bee13-4e00-4bfe-961e-1fbaa722363c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2999325663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2999325663
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.631578556
Short name T766
Test name
Test status
Simulation time 15271472 ps
CPU time 1.5 seconds
Started Mar 21 02:15:41 PM PDT 24
Finished Mar 21 02:15:44 PM PDT 24
Peak memory 235832 kb
Host smart-f31ce00b-14ec-41dd-97f8-0f05966b5772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=631578556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.631578556
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3501499928
Short name T779
Test name
Test status
Simulation time 15171595966 ps
CPU time 287.45 seconds
Started Mar 21 02:13:39 PM PDT 24
Finished Mar 21 02:18:27 PM PDT 24
Peak memory 238368 kb
Host smart-a53a0adc-b465-4deb-8d46-3c4beb110110
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3501499928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3501499928
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2243808614
Short name T804
Test name
Test status
Simulation time 1687000952 ps
CPU time 215.52 seconds
Started Mar 21 02:13:40 PM PDT 24
Finished Mar 21 02:17:18 PM PDT 24
Peak memory 236612 kb
Host smart-83463742-10cb-4441-b7c3-00637c8c87a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2243808614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2243808614
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3842866928
Short name T784
Test name
Test status
Simulation time 220806319 ps
CPU time 6.51 seconds
Started Mar 21 02:13:37 PM PDT 24
Finished Mar 21 02:13:46 PM PDT 24
Peak memory 240280 kb
Host smart-fe406a6b-452e-44bf-b267-9801b6a0c8bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3842866928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3842866928
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2597568885
Short name T811
Test name
Test status
Simulation time 242994166 ps
CPU time 12.75 seconds
Started Mar 21 02:13:38 PM PDT 24
Finished Mar 21 02:13:52 PM PDT 24
Peak memory 252652 kb
Host smart-30ff844b-a13b-4c8f-8847-d3ad3bf077cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597568885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2597568885
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2334011535
Short name T795
Test name
Test status
Simulation time 126760395 ps
CPU time 9.65 seconds
Started Mar 21 02:13:41 PM PDT 24
Finished Mar 21 02:13:52 PM PDT 24
Peak memory 236608 kb
Host smart-b2ff1ffd-6031-417b-9d92-a89c837b60b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2334011535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2334011535
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1578116988
Short name T343
Test name
Test status
Simulation time 20335952 ps
CPU time 1.81 seconds
Started Mar 21 02:13:41 PM PDT 24
Finished Mar 21 02:13:44 PM PDT 24
Peak memory 236692 kb
Host smart-580105ab-a5d7-4dce-9e50-805f582b719a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1578116988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1578116988
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3979424976
Short name T755
Test name
Test status
Simulation time 257936988 ps
CPU time 22.21 seconds
Started Mar 21 02:13:40 PM PDT 24
Finished Mar 21 02:14:04 PM PDT 24
Peak memory 244880 kb
Host smart-9aadf6e6-c3a8-42ac-80e6-37e1ef484b29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3979424976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3979424976
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2163667610
Short name T121
Test name
Test status
Simulation time 3344688096 ps
CPU time 213.73 seconds
Started Mar 21 02:13:40 PM PDT 24
Finished Mar 21 02:17:14 PM PDT 24
Peak memory 272416 kb
Host smart-1f383986-51bd-42ec-93c2-e75d64844efb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2163667610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2163667610
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.625907928
Short name T711
Test name
Test status
Simulation time 1735446855 ps
CPU time 23.59 seconds
Started Mar 21 02:13:40 PM PDT 24
Finished Mar 21 02:14:06 PM PDT 24
Peak memory 248616 kb
Host smart-2458992f-be00-4152-b4ec-bbbe813a9752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=625907928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.625907928
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.208479770
Short name T345
Test name
Test status
Simulation time 6360873 ps
CPU time 1.51 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 236700 kb
Host smart-682f2225-d5b5-4e99-86bc-0518df0cd5a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=208479770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.208479770
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1462490409
Short name T783
Test name
Test status
Simulation time 9693225 ps
CPU time 1.51 seconds
Started Mar 21 02:15:44 PM PDT 24
Finished Mar 21 02:15:48 PM PDT 24
Peak memory 234780 kb
Host smart-db89da3d-2699-4674-96bd-cc288b813f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1462490409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1462490409
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1563049105
Short name T344
Test name
Test status
Simulation time 9627748 ps
CPU time 1.42 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:45 PM PDT 24
Peak memory 234816 kb
Host smart-8ec9c5c9-3556-4ee1-9fdc-f5e67602f57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1563049105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1563049105
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2402501065
Short name T153
Test name
Test status
Simulation time 17050879 ps
CPU time 1.25 seconds
Started Mar 21 02:15:42 PM PDT 24
Finished Mar 21 02:15:44 PM PDT 24
Peak memory 235836 kb
Host smart-83ffbc94-218b-491b-9513-cc90d1be876f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2402501065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2402501065
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3242842384
Short name T744
Test name
Test status
Simulation time 10181899 ps
CPU time 1.57 seconds
Started Mar 21 02:15:43 PM PDT 24
Finished Mar 21 02:15:46 PM PDT 24
Peak memory 234760 kb
Host smart-d3c57529-4c41-48e3-a6d4-1993ad24b0c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3242842384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3242842384
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1294705776
Short name T747
Test name
Test status
Simulation time 23391268 ps
CPU time 1.39 seconds
Started Mar 21 02:15:47 PM PDT 24
Finished Mar 21 02:15:50 PM PDT 24
Peak memory 235820 kb
Host smart-07cc464e-8a48-4b11-bc8e-57eccea9dfcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1294705776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1294705776
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.821336245
Short name T785
Test name
Test status
Simulation time 12718588 ps
CPU time 1.45 seconds
Started Mar 21 02:15:57 PM PDT 24
Finished Mar 21 02:15:59 PM PDT 24
Peak memory 236688 kb
Host smart-0bd2c7d5-2d0c-4027-9da9-4f5e79a8afb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=821336245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.821336245
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1390782506
Short name T816
Test name
Test status
Simulation time 12967732 ps
CPU time 1.69 seconds
Started Mar 21 02:15:53 PM PDT 24
Finished Mar 21 02:15:55 PM PDT 24
Peak memory 235764 kb
Host smart-0138ed8e-5278-4e75-9195-e6ddbcd5e951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1390782506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1390782506
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.84572070
Short name T752
Test name
Test status
Simulation time 7157110 ps
CPU time 1.5 seconds
Started Mar 21 02:15:58 PM PDT 24
Finished Mar 21 02:15:59 PM PDT 24
Peak memory 236908 kb
Host smart-4dc4a19f-b661-4d1a-ac6a-5546f0adcc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=84572070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.84572070
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3645519190
Short name T775
Test name
Test status
Simulation time 25150406 ps
CPU time 1.64 seconds
Started Mar 21 02:15:55 PM PDT 24
Finished Mar 21 02:15:57 PM PDT 24
Peak memory 236740 kb
Host smart-89876e46-8a71-452d-aa8b-dcf7c60a9ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3645519190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3645519190
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2696577943
Short name T753
Test name
Test status
Simulation time 60510995 ps
CPU time 10.89 seconds
Started Mar 21 02:13:48 PM PDT 24
Finished Mar 21 02:13:59 PM PDT 24
Peak memory 243688 kb
Host smart-2de6e027-d2a2-41c8-9877-d03f1c05ffc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696577943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2696577943
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2730347374
Short name T738
Test name
Test status
Simulation time 180325642 ps
CPU time 4.99 seconds
Started Mar 21 02:13:48 PM PDT 24
Finished Mar 21 02:13:54 PM PDT 24
Peak memory 236468 kb
Host smart-26c21b2e-e7e4-4236-bdb4-0cb85bc2af0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2730347374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2730347374
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2806362972
Short name T347
Test name
Test status
Simulation time 12117605 ps
CPU time 1.27 seconds
Started Mar 21 02:13:49 PM PDT 24
Finished Mar 21 02:13:51 PM PDT 24
Peak memory 236560 kb
Host smart-f3d09bef-1220-43c7-bb19-7b1f7ceced06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2806362972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2806362972
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3827556742
Short name T731
Test name
Test status
Simulation time 1421165097 ps
CPU time 20.55 seconds
Started Mar 21 02:13:49 PM PDT 24
Finished Mar 21 02:14:09 PM PDT 24
Peak memory 248488 kb
Host smart-32c9a56e-a0d6-4bc3-a710-63a721c26990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3827556742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3827556742
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4010763241
Short name T817
Test name
Test status
Simulation time 687616355 ps
CPU time 14.06 seconds
Started Mar 21 02:13:50 PM PDT 24
Finished Mar 21 02:14:04 PM PDT 24
Peak memory 248608 kb
Host smart-00276f1c-ce26-4640-868c-a981f8779812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4010763241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4010763241
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.436785239
Short name T820
Test name
Test status
Simulation time 471204736 ps
CPU time 8.03 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:09 PM PDT 24
Peak memory 238860 kb
Host smart-837f94e5-5015-4786-842b-2bbbc2bdc537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436785239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.436785239
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3732280214
Short name T724
Test name
Test status
Simulation time 567196188 ps
CPU time 4.75 seconds
Started Mar 21 02:14:04 PM PDT 24
Finished Mar 21 02:14:08 PM PDT 24
Peak memory 235592 kb
Host smart-a7764052-9c86-4c5e-a594-3c0696fcc673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3732280214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3732280214
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1424052525
Short name T342
Test name
Test status
Simulation time 9718376 ps
CPU time 1.42 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:02 PM PDT 24
Peak memory 236704 kb
Host smart-3d5c25d8-3b6e-45e3-895d-590abe286b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1424052525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1424052525
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1839689805
Short name T733
Test name
Test status
Simulation time 1046348751 ps
CPU time 34.76 seconds
Started Mar 21 02:13:59 PM PDT 24
Finished Mar 21 02:14:34 PM PDT 24
Peak memory 244044 kb
Host smart-58452851-2250-4396-b762-b27421a6d92e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1839689805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1839689805
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1449037052
Short name T124
Test name
Test status
Simulation time 2008094286 ps
CPU time 142.68 seconds
Started Mar 21 02:13:51 PM PDT 24
Finished Mar 21 02:16:13 PM PDT 24
Peak memory 257008 kb
Host smart-97788fa1-b92b-4354-a7c8-05f9c808ad30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1449037052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1449037052
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.479084480
Short name T721
Test name
Test status
Simulation time 134480728 ps
CPU time 9.05 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:09 PM PDT 24
Peak memory 248596 kb
Host smart-5e6e2a2b-9d2c-452c-9ba6-01589fc7e65c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=479084480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.479084480
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3572687796
Short name T247
Test name
Test status
Simulation time 264854192 ps
CPU time 12.33 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:13 PM PDT 24
Peak memory 239080 kb
Host smart-3843c968-3169-4a2e-945d-35f8790ddb8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572687796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3572687796
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4108201484
Short name T189
Test name
Test status
Simulation time 616116302 ps
CPU time 4.98 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:05 PM PDT 24
Peak memory 236612 kb
Host smart-97cbd9c7-f4a1-41bf-bbf4-1df019ef2c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4108201484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4108201484
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3187690176
Short name T805
Test name
Test status
Simulation time 8149278 ps
CPU time 1.29 seconds
Started Mar 21 02:14:00 PM PDT 24
Finished Mar 21 02:14:02 PM PDT 24
Peak memory 234724 kb
Host smart-9200d80e-47af-4dc9-bdee-a400a2e89184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3187690176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3187690176
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3096106479
Short name T188
Test name
Test status
Simulation time 1775982913 ps
CPU time 19.27 seconds
Started Mar 21 02:13:59 PM PDT 24
Finished Mar 21 02:14:19 PM PDT 24
Peak memory 243848 kb
Host smart-bee27f87-baea-4aa0-87d0-7fd284adbe03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3096106479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3096106479
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3299341308
Short name T132
Test name
Test status
Simulation time 5982662221 ps
CPU time 199.64 seconds
Started Mar 21 02:13:59 PM PDT 24
Finished Mar 21 02:17:20 PM PDT 24
Peak memory 265140 kb
Host smart-a56199b0-a27c-4fc0-8960-fe13c91a7a3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3299341308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3299341308
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2187684792
Short name T356
Test name
Test status
Simulation time 26492171770 ps
CPU time 426.93 seconds
Started Mar 21 02:14:04 PM PDT 24
Finished Mar 21 02:21:11 PM PDT 24
Peak memory 267652 kb
Host smart-2be214f8-834e-4c40-b001-3b1c6686ee75
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187684792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2187684792
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3031668146
Short name T790
Test name
Test status
Simulation time 325048585 ps
CPU time 24.89 seconds
Started Mar 21 02:14:18 PM PDT 24
Finished Mar 21 02:14:44 PM PDT 24
Peak memory 248604 kb
Host smart-8c5cb676-6438-4504-a435-ff30f05c0a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031668146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3031668146
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1242722373
Short name T728
Test name
Test status
Simulation time 134410048 ps
CPU time 6.12 seconds
Started Mar 21 02:14:11 PM PDT 24
Finished Mar 21 02:14:18 PM PDT 24
Peak memory 256488 kb
Host smart-65d6f0c7-a414-47ed-8a8d-2d0681ad2d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242722373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1242722373
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2645520470
Short name T815
Test name
Test status
Simulation time 111811901 ps
CPU time 6.36 seconds
Started Mar 21 02:14:10 PM PDT 24
Finished Mar 21 02:14:17 PM PDT 24
Peak memory 236552 kb
Host smart-0ffed654-1f33-40fe-bc90-800050d01d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2645520470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2645520470
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3488677254
Short name T823
Test name
Test status
Simulation time 9964241 ps
CPU time 1.55 seconds
Started Mar 21 02:14:10 PM PDT 24
Finished Mar 21 02:14:12 PM PDT 24
Peak memory 236684 kb
Host smart-b7359ac8-9e79-44f2-a47d-8459bfa0f1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3488677254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3488677254
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2668951632
Short name T719
Test name
Test status
Simulation time 91151829 ps
CPU time 11.05 seconds
Started Mar 21 02:14:09 PM PDT 24
Finished Mar 21 02:14:21 PM PDT 24
Peak memory 243992 kb
Host smart-e2a2c906-bed7-4c5d-8d77-7509a9161347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2668951632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2668951632
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.760177570
Short name T144
Test name
Test status
Simulation time 7097168152 ps
CPU time 156.65 seconds
Started Mar 21 02:14:10 PM PDT 24
Finished Mar 21 02:16:47 PM PDT 24
Peak memory 256968 kb
Host smart-67e6dee7-9efe-42a7-bb9b-474096c43f20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=760177570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.760177570
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3716489676
Short name T714
Test name
Test status
Simulation time 127872989 ps
CPU time 10.89 seconds
Started Mar 21 02:14:10 PM PDT 24
Finished Mar 21 02:14:21 PM PDT 24
Peak memory 248584 kb
Host smart-5dddf02c-be32-41c1-b73a-fe58d2c22499
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3716489676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3716489676
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.489544483
Short name T767
Test name
Test status
Simulation time 56355422 ps
CPU time 5.06 seconds
Started Mar 21 02:14:18 PM PDT 24
Finished Mar 21 02:14:24 PM PDT 24
Peak memory 240460 kb
Host smart-cac2fc49-dd95-4467-a444-b0e842c0fb91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489544483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.489544483
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1276273429
Short name T245
Test name
Test status
Simulation time 487285972 ps
CPU time 8.96 seconds
Started Mar 21 02:14:21 PM PDT 24
Finished Mar 21 02:14:31 PM PDT 24
Peak memory 236620 kb
Host smart-e346d335-6e6c-4780-9166-2e434658d0cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1276273429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1276273429
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2772964197
Short name T827
Test name
Test status
Simulation time 18492736 ps
CPU time 1.36 seconds
Started Mar 21 02:14:19 PM PDT 24
Finished Mar 21 02:14:22 PM PDT 24
Peak memory 236668 kb
Host smart-70814e79-3b08-4753-96f7-9252e51836fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2772964197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2772964197
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1340602937
Short name T787
Test name
Test status
Simulation time 9046994897 ps
CPU time 46.36 seconds
Started Mar 21 02:14:19 PM PDT 24
Finished Mar 21 02:15:06 PM PDT 24
Peak memory 248624 kb
Host smart-72f4cce6-79a1-4e9c-8168-ae65e6fe150e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1340602937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1340602937
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1655642888
Short name T122
Test name
Test status
Simulation time 3750726534 ps
CPU time 252.7 seconds
Started Mar 21 02:14:18 PM PDT 24
Finished Mar 21 02:18:31 PM PDT 24
Peak memory 272860 kb
Host smart-8066ce4e-4202-4273-b638-2a09beaa81e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1655642888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1655642888
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3730119201
Short name T353
Test name
Test status
Simulation time 6585219077 ps
CPU time 481.66 seconds
Started Mar 21 02:14:19 PM PDT 24
Finished Mar 21 02:22:22 PM PDT 24
Peak memory 266180 kb
Host smart-fa997bee-c828-4b69-b8e3-8284a0cbeee6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730119201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3730119201
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.102007385
Short name T812
Test name
Test status
Simulation time 298247846 ps
CPU time 20.53 seconds
Started Mar 21 02:14:19 PM PDT 24
Finished Mar 21 02:14:41 PM PDT 24
Peak memory 248616 kb
Host smart-4506b75b-bf31-44e9-878e-b2d8055f97e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102007385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.102007385
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3708867240
Short name T175
Test name
Test status
Simulation time 32931676993 ps
CPU time 1762.61 seconds
Started Mar 21 02:27:31 PM PDT 24
Finished Mar 21 02:56:55 PM PDT 24
Peak memory 273496 kb
Host smart-6513308b-eb82-4337-9c6f-055f7d1eccee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708867240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3708867240
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.4197363550
Short name T629
Test name
Test status
Simulation time 133486376 ps
CPU time 8.48 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:27:47 PM PDT 24
Peak memory 240632 kb
Host smart-a9cd67d0-895c-45d7-a9e3-f8f6ecfe2d31
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4197363550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4197363550
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2766431629
Short name T396
Test name
Test status
Simulation time 5145139947 ps
CPU time 143.53 seconds
Started Mar 21 02:27:27 PM PDT 24
Finished Mar 21 02:29:52 PM PDT 24
Peak memory 256744 kb
Host smart-16afc416-9f55-4f9a-ba62-3f99c6e0f21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27664
31629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2766431629
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2446173389
Short name T395
Test name
Test status
Simulation time 886714344 ps
CPU time 55.54 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:28:25 PM PDT 24
Peak memory 248884 kb
Host smart-003b456a-1562-4ab6-9888-6529573649b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24461
73389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2446173389
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2975024289
Short name T575
Test name
Test status
Simulation time 188255412902 ps
CPU time 2714.31 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 03:12:46 PM PDT 24
Peak memory 281788 kb
Host smart-56bfe2de-ac79-437a-b447-b9683a7c23f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975024289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2975024289
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2767172686
Short name T696
Test name
Test status
Simulation time 83292718280 ps
CPU time 3102.92 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 03:19:21 PM PDT 24
Peak memory 289328 kb
Host smart-4c714428-cd7f-4dd1-8787-ef37ddeaafbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767172686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2767172686
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3908584428
Short name T588
Test name
Test status
Simulation time 27088941119 ps
CPU time 303.56 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 02:32:35 PM PDT 24
Peak memory 248076 kb
Host smart-9e8c8cff-dd9c-4df3-8433-bbd00c092847
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908584428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3908584428
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.264904707
Short name T260
Test name
Test status
Simulation time 7184144358 ps
CPU time 31.36 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:28:01 PM PDT 24
Peak memory 255980 kb
Host smart-52ba2249-875a-41f2-bd63-3281e77b9c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
4707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.264904707
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2929301149
Short name T67
Test name
Test status
Simulation time 182876256 ps
CPU time 12.48 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 02:27:44 PM PDT 24
Peak memory 248752 kb
Host smart-dbc80304-df1a-4d82-b251-784535aca52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29293
01149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2929301149
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3260695631
Short name T286
Test name
Test status
Simulation time 772706165 ps
CPU time 46.77 seconds
Started Mar 21 02:27:28 PM PDT 24
Finished Mar 21 02:28:16 PM PDT 24
Peak memory 248872 kb
Host smart-bff66e68-dcd3-489f-8bd2-899600649ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
95631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3260695631
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3452454232
Short name T608
Test name
Test status
Simulation time 211230030 ps
CPU time 15.61 seconds
Started Mar 21 02:27:30 PM PDT 24
Finished Mar 21 02:27:47 PM PDT 24
Peak memory 254084 kb
Host smart-13878b5c-2178-4dce-969c-981f6dd1e174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34524
54232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3452454232
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1261631965
Short name T35
Test name
Test status
Simulation time 21025935491 ps
CPU time 1908.37 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:59:27 PM PDT 24
Peak memory 297756 kb
Host smart-22c48e12-d5d0-4549-a3be-529ca24c9189
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261631965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1261631965
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2124824286
Short name T514
Test name
Test status
Simulation time 275826057 ps
CPU time 15.23 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:27:53 PM PDT 24
Peak memory 240644 kb
Host smart-0e18e6b8-2034-40db-b24d-82448a90da99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2124824286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2124824286
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3727900830
Short name T591
Test name
Test status
Simulation time 1869789852 ps
CPU time 166.24 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:30:25 PM PDT 24
Peak memory 250916 kb
Host smart-aaffe68e-e76d-4ab5-b62a-c6558a31d97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37279
00830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3727900830
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3543648824
Short name T552
Test name
Test status
Simulation time 85447916 ps
CPU time 4.41 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:27:42 PM PDT 24
Peak memory 239156 kb
Host smart-a6c4d8b5-215e-4068-9da1-3c4e0125989c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35436
48824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3543648824
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.593711400
Short name T63
Test name
Test status
Simulation time 5956256222 ps
CPU time 663.09 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:38:42 PM PDT 24
Peak memory 266352 kb
Host smart-fe1d1215-aec9-4dca-8022-fa3708cc28e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593711400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.593711400
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.714420443
Short name T665
Test name
Test status
Simulation time 25093494994 ps
CPU time 265.44 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:32:04 PM PDT 24
Peak memory 248036 kb
Host smart-8b129175-d4a5-4255-9599-b809ed950f37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714420443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.714420443
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2585355477
Short name T456
Test name
Test status
Simulation time 840317489 ps
CPU time 8.53 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:27:47 PM PDT 24
Peak memory 248860 kb
Host smart-d601c39f-004f-4017-9fc0-8991c354a2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25853
55477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2585355477
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3282958037
Short name T649
Test name
Test status
Simulation time 191355477 ps
CPU time 12.46 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:27:51 PM PDT 24
Peak memory 251912 kb
Host smart-a4367d22-446c-4d4a-8498-1567ef39189e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
58037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3282958037
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2166083839
Short name T36
Test name
Test status
Simulation time 1090063631 ps
CPU time 52.18 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:28:31 PM PDT 24
Peak memory 269660 kb
Host smart-9500a2b8-2fef-402f-9f24-ebf7be57b37e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2166083839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2166083839
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2518788387
Short name T390
Test name
Test status
Simulation time 3104672033 ps
CPU time 54.6 seconds
Started Mar 21 02:27:37 PM PDT 24
Finished Mar 21 02:28:32 PM PDT 24
Peak memory 255084 kb
Host smart-9651cc0a-d004-4b38-9bb2-f142cd70c0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25187
88387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2518788387
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.801021405
Short name T605
Test name
Test status
Simulation time 226323037 ps
CPU time 11.45 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:27:50 PM PDT 24
Peak memory 249024 kb
Host smart-d7f63247-b818-42d6-ab71-78b1e09cb76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80102
1405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.801021405
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.791149453
Short name T107
Test name
Test status
Simulation time 155746170377 ps
CPU time 2738.23 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 03:13:17 PM PDT 24
Peak memory 289792 kb
Host smart-8432e256-335e-4cd3-8e38-5d6de7b389ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791149453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.791149453
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2749339145
Short name T225
Test name
Test status
Simulation time 60337237 ps
CPU time 3.17 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:28:24 PM PDT 24
Peak memory 249092 kb
Host smart-dc9fe264-6957-424c-a47f-d9d1153821e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2749339145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2749339145
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2713101841
Short name T266
Test name
Test status
Simulation time 83500349227 ps
CPU time 2579.11 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 03:11:21 PM PDT 24
Peak memory 281700 kb
Host smart-65d56a70-e3d9-4c3a-a5c6-27f6bf997717
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713101841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2713101841
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2254430073
Short name T477
Test name
Test status
Simulation time 3143196137 ps
CPU time 10.43 seconds
Started Mar 21 02:28:23 PM PDT 24
Finished Mar 21 02:28:33 PM PDT 24
Peak memory 248924 kb
Host smart-26ed02c7-37cc-43e9-a355-a36cfcf4c831
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2254430073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2254430073
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.813313280
Short name T410
Test name
Test status
Simulation time 5200330579 ps
CPU time 274.66 seconds
Started Mar 21 02:28:22 PM PDT 24
Finished Mar 21 02:32:57 PM PDT 24
Peak memory 251356 kb
Host smart-ec7d3e6c-947a-4aa2-a1a4-d9756208ad23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81331
3280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.813313280
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3629481481
Short name T466
Test name
Test status
Simulation time 878431762 ps
CPU time 28.42 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 02:28:50 PM PDT 24
Peak memory 255356 kb
Host smart-df32a735-15e7-458d-94dd-a58e7b723cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36294
81481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3629481481
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3900193867
Short name T331
Test name
Test status
Simulation time 133042961911 ps
CPU time 1450.03 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 02:52:31 PM PDT 24
Peak memory 283972 kb
Host smart-40498c15-39e2-49d4-996a-a3cce11b6b1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900193867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3900193867
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1872992461
Short name T209
Test name
Test status
Simulation time 64054732865 ps
CPU time 2749.24 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 03:14:10 PM PDT 24
Peak memory 289844 kb
Host smart-64b434f6-2a48-4a03-b79e-90a9b366662f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872992461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1872992461
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3484351275
Short name T698
Test name
Test status
Simulation time 9974161380 ps
CPU time 415.4 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 02:35:16 PM PDT 24
Peak memory 248916 kb
Host smart-267b9f33-c2a2-4532-bf1c-cdaedce4e712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484351275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3484351275
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2438320464
Short name T483
Test name
Test status
Simulation time 106609031 ps
CPU time 12.92 seconds
Started Mar 21 02:28:18 PM PDT 24
Finished Mar 21 02:28:31 PM PDT 24
Peak memory 248812 kb
Host smart-5ca26224-4111-4335-87a7-d3701eaa6f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24383
20464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2438320464
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1158839972
Short name T627
Test name
Test status
Simulation time 471563536 ps
CPU time 29.51 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:28:50 PM PDT 24
Peak memory 255540 kb
Host smart-c6341414-9700-449e-aa5c-3d21dee4f4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11588
39972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1158839972
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.275724010
Short name T540
Test name
Test status
Simulation time 3808185018 ps
CPU time 49.82 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:29:10 PM PDT 24
Peak memory 248916 kb
Host smart-fe6a8518-4177-430c-82d6-29250220aedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27572
4010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.275724010
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4003267154
Short name T421
Test name
Test status
Simulation time 204906870 ps
CPU time 14.25 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:28:35 PM PDT 24
Peak memory 253100 kb
Host smart-4f4db63f-f613-4689-98b8-51b7e92b266f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40032
67154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4003267154
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2586109068
Short name T288
Test name
Test status
Simulation time 31298615128 ps
CPU time 2232.43 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 03:05:34 PM PDT 24
Peak memory 287816 kb
Host smart-cc8bd987-6ff5-4d0a-bd90-0bb500e8d1f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586109068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2586109068
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2782169614
Short name T590
Test name
Test status
Simulation time 51406738859 ps
CPU time 1473.08 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:52:52 PM PDT 24
Peak memory 273380 kb
Host smart-5807832d-6642-4f4c-979f-b0ca41eb2c4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782169614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2782169614
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.647590989
Short name T708
Test name
Test status
Simulation time 14811941587 ps
CPU time 70.77 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:29:31 PM PDT 24
Peak memory 248916 kb
Host smart-68058259-1f6e-43e0-a043-fafd0dbcc043
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=647590989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.647590989
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2108611987
Short name T404
Test name
Test status
Simulation time 1808940052 ps
CPU time 120 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:30:20 PM PDT 24
Peak memory 256712 kb
Host smart-8f3a3bd4-85d7-4d71-89d9-9affe2f2190f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21086
11987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2108611987
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1551130455
Short name T556
Test name
Test status
Simulation time 379544775 ps
CPU time 27.78 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:28:47 PM PDT 24
Peak memory 256008 kb
Host smart-81cbc513-808c-4ebe-b1d4-6f8edc9516d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15511
30455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1551130455
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2426008206
Short name T312
Test name
Test status
Simulation time 115830369248 ps
CPU time 2708.15 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 03:13:29 PM PDT 24
Peak memory 289428 kb
Host smart-465aefb6-d0a5-4db8-b0e5-86779a3c1428
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426008206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2426008206
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.81561576
Short name T664
Test name
Test status
Simulation time 142060237903 ps
CPU time 1675.4 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:56:16 PM PDT 24
Peak memory 273452 kb
Host smart-4d1bf735-fae8-4888-8741-9b0a3aa8df0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81561576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.81561576
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3978264351
Short name T31
Test name
Test status
Simulation time 42185772686 ps
CPU time 429.16 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 02:35:30 PM PDT 24
Peak memory 248140 kb
Host smart-9523d943-ba27-436c-82f2-2dc14c6b3063
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978264351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3978264351
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4014143922
Short name T500
Test name
Test status
Simulation time 612157819 ps
CPU time 40.23 seconds
Started Mar 21 02:28:25 PM PDT 24
Finished Mar 21 02:29:06 PM PDT 24
Peak memory 257032 kb
Host smart-04f7bf67-ae8d-4bbd-b4c2-e1ad10ce14b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40141
43922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4014143922
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1865988289
Short name T92
Test name
Test status
Simulation time 904789980 ps
CPU time 57.87 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:29:18 PM PDT 24
Peak memory 248888 kb
Host smart-a8b5130a-05b6-4902-bb56-18dab15c14cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18659
88289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1865988289
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1001435958
Short name T513
Test name
Test status
Simulation time 1055941378 ps
CPU time 64.41 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:29:24 PM PDT 24
Peak memory 249112 kb
Host smart-462af95c-47f8-4865-bd1a-ff705325acfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014
35958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1001435958
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.242926899
Short name T409
Test name
Test status
Simulation time 3908197513 ps
CPU time 25.01 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:28:44 PM PDT 24
Peak memory 248936 kb
Host smart-de0de905-7758-409b-abd5-138f8ff892b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24292
6899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.242926899
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1116247835
Short name T271
Test name
Test status
Simulation time 13886789476 ps
CPU time 822.5 seconds
Started Mar 21 02:28:22 PM PDT 24
Finished Mar 21 02:42:04 PM PDT 24
Peak memory 265308 kb
Host smart-a83e0ebf-e297-44a7-8d2d-b0896658919d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116247835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1116247835
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.657774110
Short name T173
Test name
Test status
Simulation time 73595175875 ps
CPU time 4067.98 seconds
Started Mar 21 02:28:24 PM PDT 24
Finished Mar 21 03:36:13 PM PDT 24
Peak memory 305372 kb
Host smart-1d104394-84d2-4b8c-a2b7-5e18022b5204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657774110 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.657774110
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1966738448
Short name T212
Test name
Test status
Simulation time 54188106 ps
CPU time 2.72 seconds
Started Mar 21 02:28:27 PM PDT 24
Finished Mar 21 02:28:30 PM PDT 24
Peak memory 249080 kb
Host smart-b2f31f92-1504-49e8-9403-cb59cbeaabf7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1966738448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1966738448
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2637759018
Short name T526
Test name
Test status
Simulation time 41244745356 ps
CPU time 993.55 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 02:44:54 PM PDT 24
Peak memory 281788 kb
Host smart-937fe115-4e23-48c0-b70e-71b13a9e23c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637759018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2637759018
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1005484966
Short name T405
Test name
Test status
Simulation time 7054684711 ps
CPU time 52.23 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:29:12 PM PDT 24
Peak memory 240704 kb
Host smart-ca5cf81f-2d3d-4189-92db-88097c4a7d92
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1005484966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1005484966
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3496641468
Short name T697
Test name
Test status
Simulation time 1243086535 ps
CPU time 36.49 seconds
Started Mar 21 02:28:26 PM PDT 24
Finished Mar 21 02:29:03 PM PDT 24
Peak memory 247276 kb
Host smart-1607fef4-c8c5-4ece-88c9-549d9f9002a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34966
41468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3496641468
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.873237982
Short name T400
Test name
Test status
Simulation time 1160489716 ps
CPU time 21.1 seconds
Started Mar 21 02:28:18 PM PDT 24
Finished Mar 21 02:28:40 PM PDT 24
Peak memory 255572 kb
Host smart-ab1e300e-eeb6-4d9e-8224-57b90b5fceef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87323
7982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.873237982
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.294598822
Short name T303
Test name
Test status
Simulation time 41117883636 ps
CPU time 2339.44 seconds
Started Mar 21 02:28:25 PM PDT 24
Finished Mar 21 03:07:24 PM PDT 24
Peak memory 282608 kb
Host smart-ea4e0d6b-e058-4d1d-8c7d-603d36147ada
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294598822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.294598822
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.384440851
Short name T451
Test name
Test status
Simulation time 71410519179 ps
CPU time 1098.45 seconds
Started Mar 21 02:28:27 PM PDT 24
Finished Mar 21 02:46:46 PM PDT 24
Peak memory 272160 kb
Host smart-7d87b7a1-cadc-4eb5-ba11-4c3c5ea886bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384440851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.384440851
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1448985935
Short name T659
Test name
Test status
Simulation time 1140058283 ps
CPU time 61.1 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:29:20 PM PDT 24
Peak memory 248796 kb
Host smart-5ad681d3-398e-4abe-99f5-0ef71cdf7b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14489
85935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1448985935
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1871540126
Short name T53
Test name
Test status
Simulation time 494266216 ps
CPU time 31.03 seconds
Started Mar 21 02:28:24 PM PDT 24
Finished Mar 21 02:28:55 PM PDT 24
Peak memory 256528 kb
Host smart-907128cb-b4d5-4084-ac1f-798bad34a455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18715
40126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1871540126
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1529495154
Short name T493
Test name
Test status
Simulation time 2619202246 ps
CPU time 30.17 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:28:51 PM PDT 24
Peak memory 247580 kb
Host smart-31f97c88-65a2-4e7a-a9d5-6a7d2db7c43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15294
95154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1529495154
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1786339366
Short name T614
Test name
Test status
Simulation time 345045589 ps
CPU time 39.92 seconds
Started Mar 21 02:28:22 PM PDT 24
Finished Mar 21 02:29:02 PM PDT 24
Peak memory 256040 kb
Host smart-1e24fc23-6dc6-4dd9-aa9b-324f947f3a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17863
39366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1786339366
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1467164987
Short name T94
Test name
Test status
Simulation time 46968240220 ps
CPU time 2182.74 seconds
Started Mar 21 02:28:25 PM PDT 24
Finished Mar 21 03:04:48 PM PDT 24
Peak memory 302068 kb
Host smart-b2a65489-a96b-4d0b-8630-132fac0325b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467164987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1467164987
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3595120372
Short name T59
Test name
Test status
Simulation time 175570009683 ps
CPU time 2671.46 seconds
Started Mar 21 02:28:27 PM PDT 24
Finished Mar 21 03:12:59 PM PDT 24
Peak memory 289916 kb
Host smart-44ec0746-1d11-43e4-a1ec-fd5d2183a159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595120372 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3595120372
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1033342197
Short name T222
Test name
Test status
Simulation time 50594588 ps
CPU time 4.82 seconds
Started Mar 21 02:28:29 PM PDT 24
Finished Mar 21 02:28:34 PM PDT 24
Peak memory 249088 kb
Host smart-54fddfe5-e9a0-44e1-af86-05269049fa02
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1033342197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1033342197
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2499005894
Short name T654
Test name
Test status
Simulation time 44005109246 ps
CPU time 1167.08 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:47:58 PM PDT 24
Peak memory 272864 kb
Host smart-7a5a4114-55d1-41d1-ae7c-f8613517c262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499005894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2499005894
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3439291625
Short name T643
Test name
Test status
Simulation time 6979504374 ps
CPU time 245.49 seconds
Started Mar 21 02:28:32 PM PDT 24
Finished Mar 21 02:32:37 PM PDT 24
Peak memory 257044 kb
Host smart-d2c04b66-b5a6-4866-a1b7-56ef594ce795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
91625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3439291625
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2462113958
Short name T74
Test name
Test status
Simulation time 1021495103 ps
CPU time 17.34 seconds
Started Mar 21 02:28:34 PM PDT 24
Finished Mar 21 02:28:52 PM PDT 24
Peak memory 255208 kb
Host smart-5254b356-7197-4bc6-bea3-92945f687e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24621
13958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2462113958
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4056361650
Short name T443
Test name
Test status
Simulation time 33487210693 ps
CPU time 1626.62 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:55:37 PM PDT 24
Peak memory 271920 kb
Host smart-20d74343-4ac8-4ab1-8d61-f4dad13e0f12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056361650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4056361650
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3697287071
Short name T301
Test name
Test status
Simulation time 4260718235 ps
CPU time 180.27 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:31:31 PM PDT 24
Peak memory 247844 kb
Host smart-f265ff78-b7d5-4b1a-859c-abcc4f8c0e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697287071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3697287071
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1435663359
Short name T370
Test name
Test status
Simulation time 42635161 ps
CPU time 6.76 seconds
Started Mar 21 02:28:26 PM PDT 24
Finished Mar 21 02:28:33 PM PDT 24
Peak memory 248856 kb
Host smart-1ee509c3-15e0-405b-a9b1-d9361edb3ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14356
63359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1435663359
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1461267280
Short name T439
Test name
Test status
Simulation time 2770883728 ps
CPU time 71.85 seconds
Started Mar 21 02:28:27 PM PDT 24
Finished Mar 21 02:29:39 PM PDT 24
Peak memory 255052 kb
Host smart-2210adf8-438e-430f-9a72-c7a1cfb16c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
67280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1461267280
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.42060371
Short name T522
Test name
Test status
Simulation time 148376398 ps
CPU time 10.35 seconds
Started Mar 21 02:28:29 PM PDT 24
Finished Mar 21 02:28:40 PM PDT 24
Peak memory 248828 kb
Host smart-d0c335eb-711e-42f7-ba3c-1603517ca399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060
371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.42060371
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2430537766
Short name T414
Test name
Test status
Simulation time 1484346817 ps
CPU time 49.22 seconds
Started Mar 21 02:28:26 PM PDT 24
Finished Mar 21 02:29:15 PM PDT 24
Peak memory 249000 kb
Host smart-3ae1f318-a18c-4758-811b-6a46b8c2295c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305
37766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2430537766
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.438301660
Short name T601
Test name
Test status
Simulation time 48198063846 ps
CPU time 2571.77 seconds
Started Mar 21 02:28:35 PM PDT 24
Finished Mar 21 03:11:27 PM PDT 24
Peak memory 289880 kb
Host smart-f788ec4d-d286-4579-8950-6a1de95f02ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438301660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.438301660
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1089545489
Short name T562
Test name
Test status
Simulation time 49718489716 ps
CPU time 4574.12 seconds
Started Mar 21 02:28:37 PM PDT 24
Finished Mar 21 03:44:52 PM PDT 24
Peak memory 330512 kb
Host smart-5e27060c-db04-4d12-8da3-91e7b153987f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089545489 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1089545489
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3542025949
Short name T195
Test name
Test status
Simulation time 18118204 ps
CPU time 2.56 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:28:33 PM PDT 24
Peak memory 249060 kb
Host smart-e10d3948-f000-4a6c-8b3e-5483c1a44117
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3542025949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3542025949
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3335054476
Short name T99
Test name
Test status
Simulation time 250867055272 ps
CPU time 1631.6 seconds
Started Mar 21 02:28:31 PM PDT 24
Finished Mar 21 02:55:43 PM PDT 24
Peak memory 273396 kb
Host smart-372dd1c9-6918-4cfd-bd4d-2b7012d2b051
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335054476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3335054476
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2610248793
Short name T384
Test name
Test status
Simulation time 804963134 ps
CPU time 20.19 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:28:51 PM PDT 24
Peak memory 240636 kb
Host smart-d2f91aa9-7896-435e-915d-2d7ec693b348
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2610248793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2610248793
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3220459092
Short name T387
Test name
Test status
Simulation time 2671787702 ps
CPU time 172.85 seconds
Started Mar 21 02:28:37 PM PDT 24
Finished Mar 21 02:31:30 PM PDT 24
Peak memory 257108 kb
Host smart-faa65095-2268-4666-ab3d-cba79403e796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32204
59092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3220459092
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.778134697
Short name T661
Test name
Test status
Simulation time 236327003 ps
CPU time 25.86 seconds
Started Mar 21 02:28:29 PM PDT 24
Finished Mar 21 02:28:55 PM PDT 24
Peak memory 254820 kb
Host smart-7e63baf6-8001-4fbf-8891-805870736af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77813
4697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.778134697
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1973714808
Short name T340
Test name
Test status
Simulation time 64741087613 ps
CPU time 2218.15 seconds
Started Mar 21 02:28:31 PM PDT 24
Finished Mar 21 03:05:30 PM PDT 24
Peak memory 283616 kb
Host smart-8e806bf4-2ba9-454c-85e0-29ad4d65983f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973714808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1973714808
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3696376494
Short name T265
Test name
Test status
Simulation time 85564609654 ps
CPU time 1417.06 seconds
Started Mar 21 02:28:34 PM PDT 24
Finished Mar 21 02:52:11 PM PDT 24
Peak memory 273436 kb
Host smart-a798fdbb-5b68-4b78-b70e-0173f13b4b2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696376494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3696376494
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3586881780
Short name T535
Test name
Test status
Simulation time 216405325 ps
CPU time 22.31 seconds
Started Mar 21 02:28:37 PM PDT 24
Finished Mar 21 02:29:00 PM PDT 24
Peak memory 249168 kb
Host smart-c9072b6a-a063-41e6-9fa3-35d17edd6656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35868
81780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3586881780
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1891487698
Short name T382
Test name
Test status
Simulation time 428285913 ps
CPU time 12.44 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:28:43 PM PDT 24
Peak memory 247424 kb
Host smart-a9ebe579-35ec-4b82-9b1d-2d93d25e7fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18914
87698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1891487698
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2695031794
Short name T675
Test name
Test status
Simulation time 1218932960 ps
CPU time 42.57 seconds
Started Mar 21 02:28:32 PM PDT 24
Finished Mar 21 02:29:14 PM PDT 24
Peak memory 255812 kb
Host smart-89dee385-b35d-491c-82c9-615ed633137f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
31794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2695031794
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.271756827
Short name T199
Test name
Test status
Simulation time 56546785855 ps
CPU time 4066.81 seconds
Started Mar 21 02:28:27 PM PDT 24
Finished Mar 21 03:36:14 PM PDT 24
Peak memory 305348 kb
Host smart-91996379-c085-46b5-9f11-8fe2b6f05b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271756827 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.271756827
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3448347744
Short name T216
Test name
Test status
Simulation time 126328942 ps
CPU time 3.61 seconds
Started Mar 21 02:28:41 PM PDT 24
Finished Mar 21 02:28:45 PM PDT 24
Peak memory 249116 kb
Host smart-3b040064-5c72-4fb9-8588-1430aa39def1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3448347744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3448347744
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1187464636
Short name T703
Test name
Test status
Simulation time 50158197150 ps
CPU time 1137.93 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:47:42 PM PDT 24
Peak memory 287620 kb
Host smart-8a3e6357-a3d4-434f-b2ae-b773c48c9068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187464636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1187464636
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2850590155
Short name T671
Test name
Test status
Simulation time 427496826 ps
CPU time 12.59 seconds
Started Mar 21 02:28:41 PM PDT 24
Finished Mar 21 02:28:54 PM PDT 24
Peak memory 240672 kb
Host smart-41169216-0ad5-4ff5-b60d-cb6a1b145099
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2850590155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2850590155
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1087780472
Short name T406
Test name
Test status
Simulation time 1437696372 ps
CPU time 118.75 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:30:43 PM PDT 24
Peak memory 248984 kb
Host smart-e7ed364a-5d65-477f-9c5f-a4212e823c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
80472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1087780472
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.807818631
Short name T274
Test name
Test status
Simulation time 1900737519 ps
CPU time 36.15 seconds
Started Mar 21 02:28:34 PM PDT 24
Finished Mar 21 02:29:11 PM PDT 24
Peak memory 254876 kb
Host smart-bcd0bf67-78ba-44b6-9456-73f65772077d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80781
8631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.807818631
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1146665271
Short name T620
Test name
Test status
Simulation time 35469798986 ps
CPU time 2317.75 seconds
Started Mar 21 02:28:43 PM PDT 24
Finished Mar 21 03:07:22 PM PDT 24
Peak memory 281684 kb
Host smart-a8234b11-28df-42d8-8da0-7e9e2d50cd23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146665271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1146665271
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1787991444
Short name T39
Test name
Test status
Simulation time 265442946620 ps
CPU time 2200.32 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 03:05:25 PM PDT 24
Peak memory 286824 kb
Host smart-39dcc53b-c190-438c-82e3-760ddf61424d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787991444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1787991444
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3679682214
Short name T307
Test name
Test status
Simulation time 18526850311 ps
CPU time 151.06 seconds
Started Mar 21 02:28:43 PM PDT 24
Finished Mar 21 02:31:15 PM PDT 24
Peak memory 248880 kb
Host smart-0613ae68-f943-4c42-8917-b0ccbdc2118d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679682214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3679682214
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3619309904
Short name T502
Test name
Test status
Simulation time 89810352 ps
CPU time 11.93 seconds
Started Mar 21 02:28:30 PM PDT 24
Finished Mar 21 02:28:42 PM PDT 24
Peak memory 248868 kb
Host smart-b857c166-a03c-49a9-a28f-2ff476d6b344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193
09904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3619309904
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2993280003
Short name T27
Test name
Test status
Simulation time 4496322173 ps
CPU time 60.97 seconds
Started Mar 21 02:28:29 PM PDT 24
Finished Mar 21 02:29:30 PM PDT 24
Peak memory 248916 kb
Host smart-95f8a664-735d-4dc9-b3dc-31ff528d3634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29932
80003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2993280003
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3348249245
Short name T638
Test name
Test status
Simulation time 583902609 ps
CPU time 25.28 seconds
Started Mar 21 02:28:42 PM PDT 24
Finished Mar 21 02:29:08 PM PDT 24
Peak memory 248860 kb
Host smart-a6ee66e1-9de1-4839-9ca5-1d70516afa49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33482
49245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3348249245
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3006306520
Short name T606
Test name
Test status
Simulation time 618116212 ps
CPU time 18.19 seconds
Started Mar 21 02:28:37 PM PDT 24
Finished Mar 21 02:28:55 PM PDT 24
Peak memory 255436 kb
Host smart-2ee66782-ba41-49de-bbb2-0a289000fce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30063
06520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3006306520
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.170248391
Short name T96
Test name
Test status
Simulation time 98747452203 ps
CPU time 2119.64 seconds
Started Mar 21 02:28:42 PM PDT 24
Finished Mar 21 03:04:02 PM PDT 24
Peak memory 288776 kb
Host smart-62010f36-e159-4dea-a73d-ea504feb127e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170248391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.170248391
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2348961130
Short name T198
Test name
Test status
Simulation time 25198890778 ps
CPU time 2762.01 seconds
Started Mar 21 02:28:42 PM PDT 24
Finished Mar 21 03:14:44 PM PDT 24
Peak memory 318636 kb
Host smart-c2159d89-1753-454e-96f3-7504a0f8f89b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348961130 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2348961130
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3249141434
Short name T220
Test name
Test status
Simulation time 393877328 ps
CPU time 3.44 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:28:48 PM PDT 24
Peak memory 249140 kb
Host smart-89c20013-ab07-4820-9d66-0b42d63f96bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3249141434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3249141434
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3512031345
Short name T487
Test name
Test status
Simulation time 25292560288 ps
CPU time 1857.07 seconds
Started Mar 21 02:28:42 PM PDT 24
Finished Mar 21 02:59:40 PM PDT 24
Peak memory 272596 kb
Host smart-c6387b9b-4d08-4103-b8d4-c381bbf3fe51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512031345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3512031345
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2066971175
Short name T420
Test name
Test status
Simulation time 810064490 ps
CPU time 34.32 seconds
Started Mar 21 02:28:46 PM PDT 24
Finished Mar 21 02:29:21 PM PDT 24
Peak memory 240660 kb
Host smart-a764be54-be26-436a-a6f5-5d0201a3d786
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2066971175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2066971175
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1967646943
Short name T524
Test name
Test status
Simulation time 1523630404 ps
CPU time 128.14 seconds
Started Mar 21 02:28:45 PM PDT 24
Finished Mar 21 02:30:53 PM PDT 24
Peak memory 256764 kb
Host smart-a9ce7c0b-8882-4290-977e-5d9c5260b143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19676
46943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1967646943
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1004588850
Short name T574
Test name
Test status
Simulation time 833471672 ps
CPU time 28.15 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:29:12 PM PDT 24
Peak memory 248896 kb
Host smart-04373e49-d027-46c7-9ad2-9881c07c25fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10045
88850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1004588850
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1862688374
Short name T324
Test name
Test status
Simulation time 148674520617 ps
CPU time 2585.72 seconds
Started Mar 21 02:28:47 PM PDT 24
Finished Mar 21 03:11:53 PM PDT 24
Peak memory 287908 kb
Host smart-2840ae28-5b3e-4591-a266-c2718fd7bd10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862688374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1862688374
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3655419909
Short name T7
Test name
Test status
Simulation time 17844696021 ps
CPU time 564.42 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:38:09 PM PDT 24
Peak memory 265488 kb
Host smart-a0d5f889-9734-408b-8a70-59196d91528e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655419909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3655419909
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1973933305
Short name T302
Test name
Test status
Simulation time 127222473934 ps
CPU time 515.36 seconds
Started Mar 21 02:28:46 PM PDT 24
Finished Mar 21 02:37:22 PM PDT 24
Peak memory 247808 kb
Host smart-d604e8ed-a41f-4248-8a9b-2666f1725a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973933305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1973933305
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3144612326
Short name T623
Test name
Test status
Simulation time 106930928 ps
CPU time 8.47 seconds
Started Mar 21 02:28:45 PM PDT 24
Finished Mar 21 02:28:54 PM PDT 24
Peak memory 248840 kb
Host smart-1296dee6-7d32-4ba7-a1ca-924768caf067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31446
12326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3144612326
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2850459511
Short name T672
Test name
Test status
Simulation time 844328711 ps
CPU time 58.77 seconds
Started Mar 21 02:28:45 PM PDT 24
Finished Mar 21 02:29:44 PM PDT 24
Peak memory 255540 kb
Host smart-77abd7aa-329b-4e91-bc4a-7917df2be69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28504
59511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2850459511
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3948760110
Short name T284
Test name
Test status
Simulation time 3840806226 ps
CPU time 42.19 seconds
Started Mar 21 02:28:45 PM PDT 24
Finished Mar 21 02:29:27 PM PDT 24
Peak memory 255580 kb
Host smart-54dc512c-3a32-4d97-9d63-5bffca682a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
60110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3948760110
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.460492036
Short name T232
Test name
Test status
Simulation time 949842401 ps
CPU time 57.62 seconds
Started Mar 21 02:28:41 PM PDT 24
Finished Mar 21 02:29:39 PM PDT 24
Peak memory 255956 kb
Host smart-fbbe5090-6614-4d09-90b5-f74b4ee73d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46049
2036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.460492036
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.586918120
Short name T484
Test name
Test status
Simulation time 39151991406 ps
CPU time 2366.65 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 03:08:12 PM PDT 24
Peak memory 282768 kb
Host smart-23a176e7-89a8-446c-9c77-50268a2ea34f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586918120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.586918120
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3749059263
Short name T215
Test name
Test status
Simulation time 60920261 ps
CPU time 2.64 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 02:28:56 PM PDT 24
Peak memory 249088 kb
Host smart-6a0433ca-70ff-4d0f-942c-23f39f60a994
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3749059263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3749059263
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3980691877
Short name T543
Test name
Test status
Simulation time 35011628124 ps
CPU time 2149.51 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 03:04:55 PM PDT 24
Peak memory 272840 kb
Host smart-d4fc5e78-19db-4f2f-8585-73bffc874686
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980691877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3980691877
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1925613089
Short name T411
Test name
Test status
Simulation time 182906201 ps
CPU time 10.34 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 02:29:04 PM PDT 24
Peak memory 240676 kb
Host smart-cb90a88f-a3cc-4f0b-9d1b-f2d4dd67e4e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1925613089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1925613089
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1509668834
Short name T542
Test name
Test status
Simulation time 4298152136 ps
CPU time 83.19 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:30:28 PM PDT 24
Peak memory 257100 kb
Host smart-3d4a835a-ddbb-4faf-a6ec-6411b0e6a28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15096
68834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1509668834
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.264339225
Short name T585
Test name
Test status
Simulation time 1071383104 ps
CPU time 26.66 seconds
Started Mar 21 02:28:52 PM PDT 24
Finished Mar 21 02:29:19 PM PDT 24
Peak memory 255940 kb
Host smart-9e33bfd5-7068-4580-95b7-9b3b0649c69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26433
9225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.264339225
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.139083292
Short name T311
Test name
Test status
Simulation time 18482178601 ps
CPU time 202.33 seconds
Started Mar 21 02:28:57 PM PDT 24
Finished Mar 21 02:32:19 PM PDT 24
Peak memory 247992 kb
Host smart-8ec37ae8-9ae3-403e-a91a-1080dbe90c23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139083292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.139083292
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1972971866
Short name T476
Test name
Test status
Simulation time 2459895070 ps
CPU time 18.84 seconds
Started Mar 21 02:28:48 PM PDT 24
Finished Mar 21 02:29:07 PM PDT 24
Peak memory 255228 kb
Host smart-017dd135-4467-4d6a-bb6d-9f86b656a5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
71866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1972971866
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1971228425
Short name T637
Test name
Test status
Simulation time 463138262 ps
CPU time 8.98 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:28:53 PM PDT 24
Peak memory 251432 kb
Host smart-22f69bce-3666-43e3-ac1f-116ae9d7bd86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19712
28425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1971228425
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.180312414
Short name T361
Test name
Test status
Simulation time 134973869 ps
CPU time 15.48 seconds
Started Mar 21 02:28:54 PM PDT 24
Finished Mar 21 02:29:09 PM PDT 24
Peak memory 256572 kb
Host smart-4d9563bb-b707-4f17-930f-758ea17f25f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
2414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.180312414
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1450375375
Short name T625
Test name
Test status
Simulation time 579336853 ps
CPU time 36.73 seconds
Started Mar 21 02:28:44 PM PDT 24
Finished Mar 21 02:29:21 PM PDT 24
Peak memory 248868 kb
Host smart-aaf0c547-20ff-4277-8f2a-8f8d44a64cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14503
75375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1450375375
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.275571780
Short name T235
Test name
Test status
Simulation time 674076216 ps
CPU time 16.46 seconds
Started Mar 21 02:28:54 PM PDT 24
Finished Mar 21 02:29:11 PM PDT 24
Peak memory 255252 kb
Host smart-a75d08fc-36b1-4f29-a907-1cda86099a36
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275571780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.275571780
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4277588247
Short name T214
Test name
Test status
Simulation time 157959097 ps
CPU time 3.74 seconds
Started Mar 21 02:28:56 PM PDT 24
Finished Mar 21 02:29:00 PM PDT 24
Peak memory 249120 kb
Host smart-8464ee82-5498-40c0-9043-fcbbb9d29296
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4277588247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4277588247
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1277056037
Short name T296
Test name
Test status
Simulation time 75156836151 ps
CPU time 2510.87 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 03:10:44 PM PDT 24
Peak memory 273420 kb
Host smart-624f2a9f-da7d-4b4b-afe0-b450eb4a6569
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277056037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1277056037
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.129305124
Short name T430
Test name
Test status
Simulation time 1160582379 ps
CPU time 17.82 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 02:29:11 PM PDT 24
Peak memory 248864 kb
Host smart-06af74ea-98fb-4ec5-be14-6a1624a55622
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=129305124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.129305124
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.4193256799
Short name T642
Test name
Test status
Simulation time 1095646800 ps
CPU time 114.84 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:31:01 PM PDT 24
Peak memory 250124 kb
Host smart-7dc13fea-3bd4-4be1-ae51-1acdcf1be9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41932
56799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4193256799
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2854913765
Short name T425
Test name
Test status
Simulation time 2750575098 ps
CPU time 45.56 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:29:51 PM PDT 24
Peak memory 254316 kb
Host smart-e0084c42-4354-4dd5-9225-caecc2448e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28549
13765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2854913765
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3240492293
Short name T267
Test name
Test status
Simulation time 34838475423 ps
CPU time 2061.34 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 03:03:14 PM PDT 24
Peak memory 289892 kb
Host smart-66e026ec-95ce-42b2-8b58-23e585e3ac37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240492293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3240492293
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3182692508
Short name T69
Test name
Test status
Simulation time 36136121336 ps
CPU time 1861.69 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 03:00:07 PM PDT 24
Peak memory 289556 kb
Host smart-d2870781-a899-4726-a6d8-52263582ba6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182692508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3182692508
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4264031749
Short name T520
Test name
Test status
Simulation time 13563179632 ps
CPU time 128.43 seconds
Started Mar 21 02:29:06 PM PDT 24
Finished Mar 21 02:31:14 PM PDT 24
Peak memory 253748 kb
Host smart-0e29bcff-3fba-44da-afbf-09a773c605c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264031749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4264031749
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2094234262
Short name T432
Test name
Test status
Simulation time 5824099675 ps
CPU time 42.39 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 02:29:36 PM PDT 24
Peak memory 249108 kb
Host smart-87d53ccf-c6d7-4682-9bf5-be97083b9326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
34262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2094234262
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2983504723
Short name T628
Test name
Test status
Simulation time 775126469 ps
CPU time 16.97 seconds
Started Mar 21 02:28:57 PM PDT 24
Finished Mar 21 02:29:14 PM PDT 24
Peak memory 249124 kb
Host smart-8bdd9bea-b147-4356-89b9-1bfca4585c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
04723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2983504723
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2824984864
Short name T448
Test name
Test status
Simulation time 2961779941 ps
CPU time 56.38 seconds
Started Mar 21 02:28:52 PM PDT 24
Finished Mar 21 02:29:49 PM PDT 24
Peak memory 256096 kb
Host smart-26eb8f9d-6c37-485a-9e2d-681f50ceaf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
84864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2824984864
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3288073565
Short name T560
Test name
Test status
Simulation time 2010303956 ps
CPU time 65.27 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 256084 kb
Host smart-ae4ea3d0-501d-4d15-bb69-8d1f706f8800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
73565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3288073565
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2297453416
Short name T429
Test name
Test status
Simulation time 45107599040 ps
CPU time 1218.41 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:49:23 PM PDT 24
Peak memory 288668 kb
Host smart-7ad61af3-28cb-4487-bab4-802a85a41e15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297453416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2297453416
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2594422323
Short name T616
Test name
Test status
Simulation time 18263638675 ps
CPU time 1061.26 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:46:46 PM PDT 24
Peak memory 265464 kb
Host smart-be229018-4ad1-43bc-8783-236c023a1ffb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594422323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2594422323
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4234965378
Short name T518
Test name
Test status
Simulation time 1734061180 ps
CPU time 21.28 seconds
Started Mar 21 02:29:07 PM PDT 24
Finished Mar 21 02:29:28 PM PDT 24
Peak memory 240680 kb
Host smart-c5694a90-6e32-41c6-b83b-96c613d0202d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4234965378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4234965378
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2795530899
Short name T250
Test name
Test status
Simulation time 2019486736 ps
CPU time 113.26 seconds
Started Mar 21 02:29:07 PM PDT 24
Finished Mar 21 02:31:00 PM PDT 24
Peak memory 248864 kb
Host smart-7f3e6232-fe44-48db-988a-9861f2147350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
30899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2795530899
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.325874325
Short name T596
Test name
Test status
Simulation time 925691484 ps
CPU time 49.91 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:29:55 PM PDT 24
Peak memory 249000 kb
Host smart-8d12b14d-8821-42dd-8377-9e816bc0de87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32587
4325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.325874325
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3039847807
Short name T538
Test name
Test status
Simulation time 10202148471 ps
CPU time 830.6 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:42:55 PM PDT 24
Peak memory 270436 kb
Host smart-745d0aa0-53cd-4a83-a530-a79ad6187dae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039847807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3039847807
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2852120313
Short name T492
Test name
Test status
Simulation time 26126602063 ps
CPU time 1210.58 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:49:15 PM PDT 24
Peak memory 273340 kb
Host smart-60c6336b-2aa7-4f9e-aec8-1c4bdb6dea6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852120313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2852120313
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3706199615
Short name T318
Test name
Test status
Simulation time 19113916085 ps
CPU time 418.47 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:36:02 PM PDT 24
Peak memory 247984 kb
Host smart-ea13ed47-bf56-4e4b-b1af-09b8e8515cd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706199615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3706199615
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.616361357
Short name T112
Test name
Test status
Simulation time 937776716 ps
CPU time 59.38 seconds
Started Mar 21 02:28:53 PM PDT 24
Finished Mar 21 02:29:53 PM PDT 24
Peak memory 256124 kb
Host smart-d68adc59-b8ef-457c-834b-8836f3512b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61636
1357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.616361357
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3917889542
Short name T104
Test name
Test status
Simulation time 1154543839 ps
CPU time 28.88 seconds
Started Mar 21 02:28:52 PM PDT 24
Finished Mar 21 02:29:21 PM PDT 24
Peak memory 255884 kb
Host smart-2c836f25-1c02-40d7-ad87-41e83cc1426d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39178
89542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3917889542
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3254803904
Short name T539
Test name
Test status
Simulation time 1613467820 ps
CPU time 55.87 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:30:02 PM PDT 24
Peak memory 248884 kb
Host smart-a691da19-b0e1-4d26-892d-b6275bbcfd70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32548
03904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3254803904
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3271225143
Short name T192
Test name
Test status
Simulation time 481157050 ps
CPU time 33.2 seconds
Started Mar 21 02:29:06 PM PDT 24
Finished Mar 21 02:29:39 PM PDT 24
Peak memory 248884 kb
Host smart-1303500a-6adc-4c89-b8fd-e0f6a6ce2187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32712
25143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3271225143
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3674048619
Short name T41
Test name
Test status
Simulation time 13567980 ps
CPU time 2.55 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:27:43 PM PDT 24
Peak memory 249080 kb
Host smart-3bbce2e2-5da2-4b77-b63d-f5cd69bb0d3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3674048619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3674048619
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2364127712
Short name T485
Test name
Test status
Simulation time 54257564013 ps
CPU time 1376.75 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:50:35 PM PDT 24
Peak memory 289784 kb
Host smart-eb93a056-b8f8-4184-ba2b-d0127cdd770e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364127712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2364127712
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3628489900
Short name T499
Test name
Test status
Simulation time 325306134 ps
CPU time 17.14 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:27:57 PM PDT 24
Peak memory 248864 kb
Host smart-0818bbc0-1a3d-4ea6-a26a-d7b838a8795d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3628489900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3628489900
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.865798197
Short name T228
Test name
Test status
Simulation time 3116340704 ps
CPU time 184.46 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:30:43 PM PDT 24
Peak memory 256928 kb
Host smart-c18d75ed-9f42-485f-b60e-66f021e8dfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86579
8197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.865798197
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3043637032
Short name T110
Test name
Test status
Simulation time 954696417 ps
CPU time 13.84 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:27:54 PM PDT 24
Peak memory 248848 kb
Host smart-b6face76-022c-4518-8c88-3a75b6438c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30436
37032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3043637032
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.675625703
Short name T326
Test name
Test status
Simulation time 25779341677 ps
CPU time 1079.36 seconds
Started Mar 21 02:27:45 PM PDT 24
Finished Mar 21 02:45:45 PM PDT 24
Peak memory 273504 kb
Host smart-b286f414-391b-46ef-b39e-30bff44a1735
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675625703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.675625703
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4169042929
Short name T4
Test name
Test status
Simulation time 8085757609 ps
CPU time 987.77 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:44:08 PM PDT 24
Peak memory 281660 kb
Host smart-0981cb7e-7a1b-4502-8bd4-c7fa06c9755e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169042929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4169042929
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2870190420
Short name T12
Test name
Test status
Simulation time 10502792335 ps
CPU time 227.22 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:31:26 PM PDT 24
Peak memory 247844 kb
Host smart-e3095595-1f33-463a-8ca8-7f731ff98c25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870190420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2870190420
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.712719820
Short name T381
Test name
Test status
Simulation time 582969529 ps
CPU time 18.41 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:27:59 PM PDT 24
Peak memory 248992 kb
Host smart-4775bb43-6345-40c2-a20c-8cd8b66d5312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271
9820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.712719820
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.4156183385
Short name T494
Test name
Test status
Simulation time 3425911426 ps
CPU time 58.57 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:28:38 PM PDT 24
Peak memory 255272 kb
Host smart-1dff5c05-ff9b-4b9a-94c4-54df57f3b02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41561
83385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.4156183385
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.299139671
Short name T16
Test name
Test status
Simulation time 417717532 ps
CPU time 24.11 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:28:04 PM PDT 24
Peak memory 270352 kb
Host smart-1fd55c1c-d038-4a39-8108-30264cb81c5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=299139671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.299139671
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2587821358
Short name T282
Test name
Test status
Simulation time 527616420 ps
CPU time 31.99 seconds
Started Mar 21 02:27:38 PM PDT 24
Finished Mar 21 02:28:10 PM PDT 24
Peak memory 247660 kb
Host smart-a137e219-4922-4aa7-b36a-c90703bbd88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25878
21358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2587821358
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3616490989
Short name T532
Test name
Test status
Simulation time 482361279 ps
CPU time 12.06 seconds
Started Mar 21 02:27:39 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 248860 kb
Host smart-47cf5ce1-65fe-4436-9fcf-6b3201f270b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36164
90989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3616490989
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2321086832
Short name T482
Test name
Test status
Simulation time 57886713348 ps
CPU time 4313.66 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 03:39:34 PM PDT 24
Peak memory 315008 kb
Host smart-9c36fa05-4822-4434-96fe-0d5153e1363c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321086832 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2321086832
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1468785208
Short name T644
Test name
Test status
Simulation time 19711731858 ps
CPU time 1362.62 seconds
Started Mar 21 02:29:03 PM PDT 24
Finished Mar 21 02:51:46 PM PDT 24
Peak memory 265280 kb
Host smart-6412a5ed-893f-4ee1-a7f5-e0ce5fb36bc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468785208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1468785208
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1250667963
Short name T368
Test name
Test status
Simulation time 18561788488 ps
CPU time 165.68 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:31:50 PM PDT 24
Peak memory 256776 kb
Host smart-6ed2c244-68f7-4290-83f3-e266a9f25e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506
67963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1250667963
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.169151821
Short name T541
Test name
Test status
Simulation time 6922118669 ps
CPU time 41.93 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:29:46 PM PDT 24
Peak memory 255388 kb
Host smart-c7ee44cd-9c76-4118-acdb-94816b9a7d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
1821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.169151821
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3991640079
Short name T465
Test name
Test status
Simulation time 149560985998 ps
CPU time 1618.59 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:56:03 PM PDT 24
Peak memory 289224 kb
Host smart-4b22821a-1861-437f-932f-8e1288787aad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991640079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3991640079
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1160520397
Short name T602
Test name
Test status
Simulation time 12519876753 ps
CPU time 476.32 seconds
Started Mar 21 02:29:04 PM PDT 24
Finished Mar 21 02:37:00 PM PDT 24
Peak memory 247844 kb
Host smart-e67cefee-9ee1-4018-ad22-85acfc7b5864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160520397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1160520397
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2090376477
Short name T436
Test name
Test status
Simulation time 869292396 ps
CPU time 55.08 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:30:01 PM PDT 24
Peak memory 249000 kb
Host smart-0e67bb9f-9f60-4182-9aee-619e91eda102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
76477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2090376477
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2403147387
Short name T505
Test name
Test status
Simulation time 1584022784 ps
CPU time 47.19 seconds
Started Mar 21 02:29:07 PM PDT 24
Finished Mar 21 02:29:55 PM PDT 24
Peak memory 255472 kb
Host smart-f13e2714-6804-44ff-a4e3-ba95c7f80820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24031
47387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2403147387
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4274856961
Short name T537
Test name
Test status
Simulation time 2344786018 ps
CPU time 13.36 seconds
Started Mar 21 02:29:05 PM PDT 24
Finished Mar 21 02:29:19 PM PDT 24
Peak memory 252828 kb
Host smart-6751583b-ff7c-4628-8fe9-5ed1009fa865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42748
56961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4274856961
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1180617982
Short name T550
Test name
Test status
Simulation time 739957609 ps
CPU time 23.44 seconds
Started Mar 21 02:29:06 PM PDT 24
Finished Mar 21 02:29:30 PM PDT 24
Peak memory 248860 kb
Host smart-b9f32ba6-d76e-47b7-8797-3da3f41a93f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806
17982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1180617982
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.127797701
Short name T101
Test name
Test status
Simulation time 5359211417 ps
CPU time 501.06 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:37:38 PM PDT 24
Peak memory 265264 kb
Host smart-c7a7d443-7082-4de9-ae8b-57e37ee5b3af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127797701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.127797701
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3946402085
Short name T572
Test name
Test status
Simulation time 24740775367 ps
CPU time 1524.44 seconds
Started Mar 21 02:29:15 PM PDT 24
Finished Mar 21 02:54:40 PM PDT 24
Peak memory 281452 kb
Host smart-da406307-8ff8-4117-bd6b-7e312770844b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946402085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3946402085
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3955548184
Short name T64
Test name
Test status
Simulation time 817502128 ps
CPU time 24.2 seconds
Started Mar 21 02:29:15 PM PDT 24
Finished Mar 21 02:29:40 PM PDT 24
Peak memory 255008 kb
Host smart-e8eb108d-717a-45d9-912b-edcff9832ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39555
48184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3955548184
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.15644343
Short name T455
Test name
Test status
Simulation time 173938435 ps
CPU time 20.33 seconds
Started Mar 21 02:29:15 PM PDT 24
Finished Mar 21 02:29:36 PM PDT 24
Peak memory 249160 kb
Host smart-bf2cde99-52fe-4aac-be9d-e6e2aa83566f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.15644343
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4273477497
Short name T259
Test name
Test status
Simulation time 134611115231 ps
CPU time 2086.63 seconds
Started Mar 21 02:29:23 PM PDT 24
Finished Mar 21 03:04:10 PM PDT 24
Peak memory 267660 kb
Host smart-ca631f91-8348-41ed-a4fa-72184c0af920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273477497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4273477497
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1140583559
Short name T632
Test name
Test status
Simulation time 68392298718 ps
CPU time 375.13 seconds
Started Mar 21 02:29:16 PM PDT 24
Finished Mar 21 02:35:32 PM PDT 24
Peak memory 248156 kb
Host smart-7fd9ee2b-351e-461b-b399-5cc2082a402d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140583559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1140583559
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.11084098
Short name T495
Test name
Test status
Simulation time 3089458989 ps
CPU time 51.31 seconds
Started Mar 21 02:29:18 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 257112 kb
Host smart-0f32b2ad-8b77-4ec9-9585-b4b7676c9a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11084
098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.11084098
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2136279687
Short name T78
Test name
Test status
Simulation time 241241917 ps
CPU time 5.74 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:29:24 PM PDT 24
Peak memory 239064 kb
Host smart-109a9ce9-5af9-481b-82ca-bf4c84abf40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21362
79687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2136279687
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.140607110
Short name T363
Test name
Test status
Simulation time 112442995 ps
CPU time 3.87 seconds
Started Mar 21 02:29:15 PM PDT 24
Finished Mar 21 02:29:19 PM PDT 24
Peak memory 250552 kb
Host smart-553e8b70-959b-4a21-ada3-fe5130687ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14060
7110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.140607110
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1120795521
Short name T458
Test name
Test status
Simulation time 1130130032 ps
CPU time 67.87 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:30:25 PM PDT 24
Peak memory 257056 kb
Host smart-0d93a91a-3cbe-4150-8975-e3335d374db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
95521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1120795521
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.4073997273
Short name T611
Test name
Test status
Simulation time 131642109481 ps
CPU time 2265.53 seconds
Started Mar 21 02:29:15 PM PDT 24
Finished Mar 21 03:07:01 PM PDT 24
Peak memory 273496 kb
Host smart-12ef4327-5431-447c-985c-204b89dce8fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073997273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.4073997273
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2047574836
Short name T379
Test name
Test status
Simulation time 1562045586 ps
CPU time 85.85 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:30:43 PM PDT 24
Peak memory 256776 kb
Host smart-6c9b6f79-e8f5-460f-b672-dd29a726183b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
74836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2047574836
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2313405228
Short name T694
Test name
Test status
Simulation time 1550024625 ps
CPU time 15.48 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:29:33 PM PDT 24
Peak memory 253008 kb
Host smart-399b26a3-ffb1-46ce-87a6-06cbae53b9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23134
05228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2313405228
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.868776004
Short name T679
Test name
Test status
Simulation time 7640030575 ps
CPU time 930.6 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:44:48 PM PDT 24
Peak memory 273172 kb
Host smart-f03faeed-f070-42dc-ac00-2cd057a49b9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868776004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.868776004
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3109296757
Short name T512
Test name
Test status
Simulation time 173002746785 ps
CPU time 2688.83 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 03:14:06 PM PDT 24
Peak memory 281720 kb
Host smart-6e2c25f5-2b3b-4123-92bd-8dc5b0aff690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109296757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3109296757
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3336980530
Short name T555
Test name
Test status
Simulation time 5070246390 ps
CPU time 196.63 seconds
Started Mar 21 02:29:25 PM PDT 24
Finished Mar 21 02:32:42 PM PDT 24
Peak memory 247076 kb
Host smart-4f637cfe-f703-4cd0-b3ac-92972c1a60c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336980530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3336980530
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1210859885
Short name T43
Test name
Test status
Simulation time 1540252270 ps
CPU time 30.82 seconds
Started Mar 21 02:29:16 PM PDT 24
Finished Mar 21 02:29:47 PM PDT 24
Peak memory 248856 kb
Host smart-0dc7b657-fc98-4a8e-abfa-52bf6bbc0ba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12108
59885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1210859885
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2278703402
Short name T239
Test name
Test status
Simulation time 1142582588 ps
CPU time 31.35 seconds
Started Mar 21 02:29:18 PM PDT 24
Finished Mar 21 02:29:49 PM PDT 24
Peak memory 254892 kb
Host smart-cb1f2422-34c4-4e03-b61a-e4fc09bd21a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787
03402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2278703402
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1569265667
Short name T287
Test name
Test status
Simulation time 146814913 ps
CPU time 15.16 seconds
Started Mar 21 02:29:16 PM PDT 24
Finished Mar 21 02:29:32 PM PDT 24
Peak memory 247308 kb
Host smart-c1a99d4a-4c51-4801-a6d8-d9c4d33bc210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15692
65667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1569265667
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1882249357
Short name T544
Test name
Test status
Simulation time 1852669591 ps
CPU time 50.73 seconds
Started Mar 21 02:29:16 PM PDT 24
Finished Mar 21 02:30:07 PM PDT 24
Peak memory 248852 kb
Host smart-93a67538-03f6-4701-95b5-5d1838ba9559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18822
49357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1882249357
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.794007259
Short name T275
Test name
Test status
Simulation time 111774113693 ps
CPU time 2359.4 seconds
Started Mar 21 02:29:15 PM PDT 24
Finished Mar 21 03:08:35 PM PDT 24
Peak memory 288964 kb
Host smart-9fc2f08e-5015-4c52-987f-0a46de4a7246
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794007259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.794007259
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2754943263
Short name T76
Test name
Test status
Simulation time 17324642102 ps
CPU time 1667.68 seconds
Started Mar 21 02:29:33 PM PDT 24
Finished Mar 21 02:57:21 PM PDT 24
Peak memory 288856 kb
Host smart-85989861-959a-4c4d-9d5c-01654bb9117c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754943263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2754943263
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2514014979
Short name T464
Test name
Test status
Simulation time 141864155 ps
CPU time 12.13 seconds
Started Mar 21 02:29:18 PM PDT 24
Finished Mar 21 02:29:31 PM PDT 24
Peak memory 254124 kb
Host smart-168afe5b-2f53-4e6f-814b-923ec8c66fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25140
14979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2514014979
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1015214081
Short name T254
Test name
Test status
Simulation time 1599832622 ps
CPU time 52.33 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:30:10 PM PDT 24
Peak memory 255296 kb
Host smart-58d0e66b-918f-4d6f-a801-7067db048073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152
14081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1015214081
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1963064844
Short name T408
Test name
Test status
Simulation time 347999167013 ps
CPU time 2997.38 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 03:19:26 PM PDT 24
Peak memory 289360 kb
Host smart-98ed509c-fd03-4982-9c8b-784af2d5e248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963064844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1963064844
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3542874618
Short name T310
Test name
Test status
Simulation time 7039210765 ps
CPU time 292.52 seconds
Started Mar 21 02:29:30 PM PDT 24
Finished Mar 21 02:34:22 PM PDT 24
Peak memory 247812 kb
Host smart-7b2eeb08-5c7d-432a-b239-3b395867eeae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542874618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3542874618
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2682695633
Short name T437
Test name
Test status
Simulation time 434736891 ps
CPU time 12.1 seconds
Started Mar 21 02:29:18 PM PDT 24
Finished Mar 21 02:29:30 PM PDT 24
Peak memory 248888 kb
Host smart-ff260932-44b6-4954-acb1-30b2d19f89ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826
95633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2682695633
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3175017228
Short name T81
Test name
Test status
Simulation time 705503730 ps
CPU time 51.82 seconds
Started Mar 21 02:29:18 PM PDT 24
Finished Mar 21 02:30:10 PM PDT 24
Peak memory 255536 kb
Host smart-bf9955b0-7a2a-482e-9d98-4f60dbb078c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
17228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3175017228
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3942192916
Short name T23
Test name
Test status
Simulation time 1001898808 ps
CPU time 29.17 seconds
Started Mar 21 02:29:17 PM PDT 24
Finished Mar 21 02:29:46 PM PDT 24
Peak memory 249084 kb
Host smart-944f9776-4394-43f8-9f23-349833bd11d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39421
92916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3942192916
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.87933004
Short name T68
Test name
Test status
Simulation time 79184066280 ps
CPU time 1547.51 seconds
Started Mar 21 02:29:34 PM PDT 24
Finished Mar 21 02:55:22 PM PDT 24
Peak memory 273500 kb
Host smart-52109e65-a48a-436d-91e0-e13532174eb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87933004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_hand
ler_stress_all.87933004
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.364484895
Short name T442
Test name
Test status
Simulation time 44752178259 ps
CPU time 2646.14 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 03:13:36 PM PDT 24
Peak memory 289668 kb
Host smart-e016d891-f7f3-4386-bd22-bda077530711
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364484895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.364484895
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2271269774
Short name T399
Test name
Test status
Simulation time 10765476514 ps
CPU time 141.68 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:31:50 PM PDT 24
Peak memory 256588 kb
Host smart-3b2a3429-929f-4361-8505-f8f1cc4bd10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22712
69774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2271269774
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2670151446
Short name T441
Test name
Test status
Simulation time 1181194317 ps
CPU time 67.68 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:30:37 PM PDT 24
Peak memory 254188 kb
Host smart-3cd12881-ce55-4543-9eb8-e81453187341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26701
51446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2670151446
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3885496124
Short name T434
Test name
Test status
Simulation time 238967292863 ps
CPU time 1893.68 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 03:01:03 PM PDT 24
Peak memory 289324 kb
Host smart-abe5b256-3079-4aff-9948-f47a40c27309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885496124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3885496124
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3997404867
Short name T449
Test name
Test status
Simulation time 36668787828 ps
CPU time 2174.28 seconds
Started Mar 21 02:29:27 PM PDT 24
Finished Mar 21 03:05:42 PM PDT 24
Peak memory 273500 kb
Host smart-c6eaef0e-75d0-459c-a432-7d6c75014d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997404867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3997404867
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1084865793
Short name T551
Test name
Test status
Simulation time 5939524888 ps
CPU time 238.07 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:33:27 PM PDT 24
Peak memory 248152 kb
Host smart-8d0634a9-f5f0-47ad-8ee2-e24f68250220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084865793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1084865793
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3712562791
Short name T681
Test name
Test status
Simulation time 1069970622 ps
CPU time 20.37 seconds
Started Mar 21 02:29:31 PM PDT 24
Finished Mar 21 02:29:52 PM PDT 24
Peak memory 248948 kb
Host smart-48c13ede-76ae-4923-b971-60dad0189841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
62791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3712562791
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3903023682
Short name T3
Test name
Test status
Simulation time 590903839 ps
CPU time 37.27 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:30:06 PM PDT 24
Peak memory 248192 kb
Host smart-8d5fe223-bfeb-4242-8db9-18e3516f0ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
23682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3903023682
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1318425984
Short name T641
Test name
Test status
Simulation time 1129107936 ps
CPU time 17.64 seconds
Started Mar 21 02:29:30 PM PDT 24
Finished Mar 21 02:29:47 PM PDT 24
Peak memory 248840 kb
Host smart-8247a4bf-794b-4fd9-8d0b-78d201c78d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13184
25984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1318425984
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2103888294
Short name T6
Test name
Test status
Simulation time 920722052 ps
CPU time 27.91 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:29:57 PM PDT 24
Peak memory 256688 kb
Host smart-1890ab16-2e20-4d0e-97c1-45badbc7ac63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
88294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2103888294
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2896256214
Short name T33
Test name
Test status
Simulation time 579298579 ps
CPU time 35.58 seconds
Started Mar 21 02:29:30 PM PDT 24
Finished Mar 21 02:30:05 PM PDT 24
Peak memory 255708 kb
Host smart-4e6c304d-6833-43da-8b50-b15a94df0f15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896256214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2896256214
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3001459608
Short name T56
Test name
Test status
Simulation time 57246549743 ps
CPU time 3940.59 seconds
Started Mar 21 02:29:31 PM PDT 24
Finished Mar 21 03:35:12 PM PDT 24
Peak memory 298164 kb
Host smart-fc0d2e2e-79cf-46ff-8eb8-a499a1a0ab58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001459608 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3001459608
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2818647159
Short name T62
Test name
Test status
Simulation time 16436342411 ps
CPU time 1669.37 seconds
Started Mar 21 02:29:32 PM PDT 24
Finished Mar 21 02:57:21 PM PDT 24
Peak memory 289164 kb
Host smart-f85304ce-682f-4dc6-92dd-bb44d3301a5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818647159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2818647159
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3955497650
Short name T415
Test name
Test status
Simulation time 2121395820 ps
CPU time 136.4 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:31:46 PM PDT 24
Peak memory 256492 kb
Host smart-723275d4-e405-4d93-bffd-2acfb07108c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39554
97650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3955497650
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3276654708
Short name T402
Test name
Test status
Simulation time 204964769 ps
CPU time 13.53 seconds
Started Mar 21 02:29:33 PM PDT 24
Finished Mar 21 02:29:46 PM PDT 24
Peak memory 249196 kb
Host smart-9f5bc334-3689-4d7d-b1d6-170f5ddc5c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32766
54708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3276654708
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.134989696
Short name T113
Test name
Test status
Simulation time 76359143297 ps
CPU time 1789.98 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:59:19 PM PDT 24
Peak memory 289168 kb
Host smart-76f4df44-9592-44b1-b8e7-8e60c0afebca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134989696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.134989696
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2263463781
Short name T380
Test name
Test status
Simulation time 54286265169 ps
CPU time 3388.68 seconds
Started Mar 21 02:29:31 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 288884 kb
Host smart-1add1894-5b1a-420c-9807-ff1841f4038d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263463781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2263463781
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2119296893
Short name T469
Test name
Test status
Simulation time 5664128856 ps
CPU time 247 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:33:36 PM PDT 24
Peak memory 247028 kb
Host smart-f86303d9-3c08-4480-9db4-dc721bfcd446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119296893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2119296893
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3414203632
Short name T566
Test name
Test status
Simulation time 4933696834 ps
CPU time 50.84 seconds
Started Mar 21 02:29:29 PM PDT 24
Finished Mar 21 02:30:20 PM PDT 24
Peak memory 249176 kb
Host smart-e548682e-f33e-4e4b-9e82-92df52df7854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
03632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3414203632
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.667759612
Short name T54
Test name
Test status
Simulation time 689855562 ps
CPU time 11.2 seconds
Started Mar 21 02:29:33 PM PDT 24
Finished Mar 21 02:29:44 PM PDT 24
Peak memory 248660 kb
Host smart-2b6bbd89-a736-4520-9f08-7ce282df5bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66775
9612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.667759612
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2809734005
Short name T446
Test name
Test status
Simulation time 550694424 ps
CPU time 14.95 seconds
Started Mar 21 02:29:33 PM PDT 24
Finished Mar 21 02:29:48 PM PDT 24
Peak memory 248884 kb
Host smart-63829a18-3e00-4107-be49-cd1ead63ff9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
34005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2809734005
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1250056543
Short name T534
Test name
Test status
Simulation time 2141858216 ps
CPU time 30.57 seconds
Started Mar 21 02:29:32 PM PDT 24
Finished Mar 21 02:30:03 PM PDT 24
Peak memory 248976 kb
Host smart-59f334b1-22f3-49c0-93e2-2c98ee2b15ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12500
56543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1250056543
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.418029727
Short name T364
Test name
Test status
Simulation time 629181032 ps
CPU time 31.21 seconds
Started Mar 21 02:29:42 PM PDT 24
Finished Mar 21 02:30:13 PM PDT 24
Peak memory 248752 kb
Host smart-fc1f8365-f9cb-4014-971b-2b968bf17bbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418029727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.418029727
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3935809301
Short name T594
Test name
Test status
Simulation time 89593210833 ps
CPU time 2446.38 seconds
Started Mar 21 02:29:39 PM PDT 24
Finished Mar 21 03:10:26 PM PDT 24
Peak memory 288800 kb
Host smart-8ee56958-66cb-4d9d-a6ac-67c9b4f526fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935809301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3935809301
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3714804956
Short name T413
Test name
Test status
Simulation time 1087229439 ps
CPU time 41.61 seconds
Started Mar 21 02:29:43 PM PDT 24
Finished Mar 21 02:30:24 PM PDT 24
Peak memory 248672 kb
Host smart-68374d77-a817-42d7-99d6-a704e0dfe69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37148
04956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3714804956
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2934006695
Short name T270
Test name
Test status
Simulation time 7639019959 ps
CPU time 41.22 seconds
Started Mar 21 02:29:42 PM PDT 24
Finished Mar 21 02:30:23 PM PDT 24
Peak memory 255668 kb
Host smart-626bfeca-10de-4c61-a6ce-7172336a9d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340
06695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2934006695
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2227035533
Short name T561
Test name
Test status
Simulation time 160292829026 ps
CPU time 2478.58 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 03:10:59 PM PDT 24
Peak memory 289860 kb
Host smart-7264c5d0-9b08-4d66-b8d3-e5ead26ebdd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227035533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2227035533
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3234665104
Short name T578
Test name
Test status
Simulation time 107410621752 ps
CPU time 1776.47 seconds
Started Mar 21 02:29:42 PM PDT 24
Finished Mar 21 02:59:18 PM PDT 24
Peak memory 273508 kb
Host smart-26911884-4b90-46cf-88ab-143343e85402
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234665104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3234665104
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1753911983
Short name T498
Test name
Test status
Simulation time 2992537801 ps
CPU time 126.06 seconds
Started Mar 21 02:29:50 PM PDT 24
Finished Mar 21 02:31:56 PM PDT 24
Peak memory 248224 kb
Host smart-1fea4290-7cec-488b-a6ea-1676829b448b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753911983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1753911983
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3804941476
Short name T61
Test name
Test status
Simulation time 376235739 ps
CPU time 29.47 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 249008 kb
Host smart-0be894c2-9de8-4fc5-864d-0713b5ea9891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38049
41476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3804941476
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.769582932
Short name T372
Test name
Test status
Simulation time 874775632 ps
CPU time 27.5 seconds
Started Mar 21 02:29:43 PM PDT 24
Finished Mar 21 02:30:10 PM PDT 24
Peak memory 253792 kb
Host smart-448a047b-0952-4ea0-b4c1-507858515474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76958
2932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.769582932
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2356535623
Short name T598
Test name
Test status
Simulation time 431433148 ps
CPU time 28.84 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 253820 kb
Host smart-e0bc784b-0ec6-4e04-b69c-61ea535e16f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23565
35623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2356535623
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3880250108
Short name T633
Test name
Test status
Simulation time 2462498355 ps
CPU time 45.63 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 02:30:26 PM PDT 24
Peak memory 256212 kb
Host smart-66eeb728-bb9a-426f-afa0-bce7e58d324c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
50108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3880250108
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3863536342
Short name T573
Test name
Test status
Simulation time 343885402187 ps
CPU time 2596.82 seconds
Started Mar 21 02:29:49 PM PDT 24
Finished Mar 21 03:13:06 PM PDT 24
Peak memory 289564 kb
Host smart-ad9a8ab4-1b58-48f5-8664-c0a0dc1ca277
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863536342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3863536342
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3921141513
Short name T388
Test name
Test status
Simulation time 8868088431 ps
CPU time 921.52 seconds
Started Mar 21 02:29:50 PM PDT 24
Finished Mar 21 02:45:12 PM PDT 24
Peak memory 288840 kb
Host smart-e067a378-4199-4edb-84f3-e057c602db38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921141513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3921141513
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4091545384
Short name T584
Test name
Test status
Simulation time 5528696088 ps
CPU time 90.11 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:31:11 PM PDT 24
Peak memory 256884 kb
Host smart-b91e51d6-65a5-44a1-9c1c-e0fd1c6ca28a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915
45384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4091545384
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3032843453
Short name T496
Test name
Test status
Simulation time 1650551215 ps
CPU time 27.95 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 02:30:08 PM PDT 24
Peak memory 255880 kb
Host smart-93a88251-4675-476a-a304-fd1f14a71b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30328
43453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3032843453
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1471508613
Short name T313
Test name
Test status
Simulation time 49611514477 ps
CPU time 1593.39 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:56:15 PM PDT 24
Peak memory 272820 kb
Host smart-7e992be2-17c7-4876-89c2-06b64ffa84b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471508613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1471508613
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3054659459
Short name T18
Test name
Test status
Simulation time 39049851896 ps
CPU time 2273.67 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 03:07:35 PM PDT 24
Peak memory 272772 kb
Host smart-ace8b789-452a-4916-a922-8dd7ba6f0611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054659459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3054659459
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2153797048
Short name T389
Test name
Test status
Simulation time 329564572 ps
CPU time 38.75 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:30:19 PM PDT 24
Peak memory 255208 kb
Host smart-9878aee4-8685-4a4f-8a41-9fb39cd2c632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21537
97048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2153797048
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3022317953
Short name T427
Test name
Test status
Simulation time 721747406 ps
CPU time 26.97 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 02:30:07 PM PDT 24
Peak memory 256128 kb
Host smart-3261d153-71d1-4079-a4dc-a24996b97072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30223
17953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3022317953
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.113315969
Short name T523
Test name
Test status
Simulation time 325652765 ps
CPU time 18.55 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:30:00 PM PDT 24
Peak memory 255968 kb
Host smart-75bbe2b7-9823-47c1-ac55-fc5a9d888116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11331
5969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.113315969
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1013021579
Short name T692
Test name
Test status
Simulation time 1297069821 ps
CPU time 30.46 seconds
Started Mar 21 02:29:49 PM PDT 24
Finished Mar 21 02:30:20 PM PDT 24
Peak memory 248940 kb
Host smart-20f6792e-8b75-4bb3-a190-eb28f54c40db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10130
21579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1013021579
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2237909527
Short name T49
Test name
Test status
Simulation time 886331009 ps
CPU time 53.6 seconds
Started Mar 21 02:29:42 PM PDT 24
Finished Mar 21 02:30:36 PM PDT 24
Peak memory 249740 kb
Host smart-6967603e-e863-4d52-9598-93d6a9041aa7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237909527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2237909527
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1410470099
Short name T583
Test name
Test status
Simulation time 63075649897 ps
CPU time 1525.58 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 02:55:19 PM PDT 24
Peak memory 281624 kb
Host smart-1937e94d-6e15-490b-850a-9f2114918e7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410470099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1410470099
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2587868131
Short name T474
Test name
Test status
Simulation time 15728961665 ps
CPU time 272.92 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:34:14 PM PDT 24
Peak memory 256912 kb
Host smart-d765931b-5e78-474b-85ba-d12d15985d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25878
68131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2587868131
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.919867775
Short name T83
Test name
Test status
Simulation time 273421503 ps
CPU time 21.75 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:30:03 PM PDT 24
Peak memory 254432 kb
Host smart-62e1f478-edd3-4154-a509-3499801d572e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91986
7775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.919867775
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2362471377
Short name T634
Test name
Test status
Simulation time 12303496113 ps
CPU time 1089.76 seconds
Started Mar 21 02:29:51 PM PDT 24
Finished Mar 21 02:48:01 PM PDT 24
Peak memory 270432 kb
Host smart-7abbf4d0-58ee-468e-8812-3976fd95ffb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362471377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2362471377
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2314169191
Short name T677
Test name
Test status
Simulation time 22239440741 ps
CPU time 1011.13 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 02:46:44 PM PDT 24
Peak memory 273468 kb
Host smart-8451ae64-94d7-4247-849e-37e0941edc36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314169191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2314169191
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.291746854
Short name T517
Test name
Test status
Simulation time 395961459 ps
CPU time 28.76 seconds
Started Mar 21 02:29:40 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 248860 kb
Host smart-7b12249e-0fe5-4e58-80c1-51902ca7efd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29174
6854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.291746854
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1244619796
Short name T684
Test name
Test status
Simulation time 503371628 ps
CPU time 18.55 seconds
Started Mar 21 02:29:42 PM PDT 24
Finished Mar 21 02:30:00 PM PDT 24
Peak memory 247420 kb
Host smart-bae2341b-b918-494b-9562-e69649f4bbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
19796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1244619796
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2281053405
Short name T181
Test name
Test status
Simulation time 1316151624 ps
CPU time 43.31 seconds
Started Mar 21 02:29:54 PM PDT 24
Finished Mar 21 02:30:37 PM PDT 24
Peak memory 255124 kb
Host smart-1d103c47-fdc2-427f-80af-57cb8c77a83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
53405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2281053405
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1298001461
Short name T705
Test name
Test status
Simulation time 415786343 ps
CPU time 27.96 seconds
Started Mar 21 02:29:41 PM PDT 24
Finished Mar 21 02:30:09 PM PDT 24
Peak memory 249096 kb
Host smart-860bbfb7-2e17-489b-84d9-45e66cb38609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12980
01461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1298001461
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.891249051
Short name T702
Test name
Test status
Simulation time 170954281705 ps
CPU time 2179.12 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 03:06:12 PM PDT 24
Peak memory 287160 kb
Host smart-f55bd661-0d4d-4b47-959a-21e9839a8b7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891249051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.891249051
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1329298470
Short name T693
Test name
Test status
Simulation time 21010830168 ps
CPU time 117.38 seconds
Started Mar 21 02:29:55 PM PDT 24
Finished Mar 21 02:31:53 PM PDT 24
Peak memory 256300 kb
Host smart-b9789cd6-4ff5-419e-b728-f4cbb828889b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13292
98470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1329298470
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2830130829
Short name T365
Test name
Test status
Simulation time 479651058 ps
CPU time 24.48 seconds
Started Mar 21 02:29:55 PM PDT 24
Finished Mar 21 02:30:20 PM PDT 24
Peak memory 249084 kb
Host smart-42fb3664-f902-4595-9e9f-b0c542df9f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28301
30829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2830130829
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1962897774
Short name T558
Test name
Test status
Simulation time 47042553292 ps
CPU time 459.9 seconds
Started Mar 21 02:29:55 PM PDT 24
Finished Mar 21 02:37:35 PM PDT 24
Peak memory 248152 kb
Host smart-27af1d77-f000-4d63-ab5a-6aa83cf9a42b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962897774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1962897774
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2147402691
Short name T2
Test name
Test status
Simulation time 823419182 ps
CPU time 23.76 seconds
Started Mar 21 02:29:55 PM PDT 24
Finished Mar 21 02:30:19 PM PDT 24
Peak memory 248852 kb
Host smart-0d97c691-76f2-41f1-aec5-32c16d6b5a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21474
02691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2147402691
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3144739845
Short name T630
Test name
Test status
Simulation time 678525752 ps
CPU time 14.09 seconds
Started Mar 21 02:29:52 PM PDT 24
Finished Mar 21 02:30:06 PM PDT 24
Peak memory 251656 kb
Host smart-7d328ab4-4043-45e7-8014-54fa12d19e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31447
39845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3144739845
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1763321592
Short name T374
Test name
Test status
Simulation time 1080686739 ps
CPU time 9.36 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 02:30:03 PM PDT 24
Peak memory 248880 kb
Host smart-24af19c2-a31c-4e50-9ba6-4b1ad010141d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17633
21592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1763321592
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1786807460
Short name T97
Test name
Test status
Simulation time 73282899218 ps
CPU time 2652.22 seconds
Started Mar 21 02:29:52 PM PDT 24
Finished Mar 21 03:14:05 PM PDT 24
Peak memory 289880 kb
Host smart-79ae91ec-935b-4f15-b057-8986e1fd17c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786807460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1786807460
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1532876997
Short name T639
Test name
Test status
Simulation time 222961528655 ps
CPU time 3825.56 seconds
Started Mar 21 02:29:56 PM PDT 24
Finished Mar 21 03:33:42 PM PDT 24
Peak memory 314208 kb
Host smart-33bf9ef4-3a27-4e21-990a-846b7a676a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532876997 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1532876997
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2102467508
Short name T180
Test name
Test status
Simulation time 38925291 ps
CPU time 2.38 seconds
Started Mar 21 02:27:53 PM PDT 24
Finished Mar 21 02:27:57 PM PDT 24
Peak memory 249124 kb
Host smart-a65700dd-ddda-4bab-bd49-2f9b62cb6d57
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2102467508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2102467508
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4169656236
Short name T60
Test name
Test status
Simulation time 33417339543 ps
CPU time 2127.1 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 03:03:07 PM PDT 24
Peak memory 281676 kb
Host smart-2beefb9c-48b1-4dba-a531-508c01813b72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169656236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4169656236
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2290390707
Short name T208
Test name
Test status
Simulation time 1331162908 ps
CPU time 30.26 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:28:19 PM PDT 24
Peak memory 240588 kb
Host smart-939eac0d-a454-4c86-b030-e6d44d77fdd2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2290390707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2290390707
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.417802813
Short name T403
Test name
Test status
Simulation time 2768363059 ps
CPU time 145.66 seconds
Started Mar 21 02:27:45 PM PDT 24
Finished Mar 21 02:30:11 PM PDT 24
Peak memory 256668 kb
Host smart-9937d0e7-ccd5-4f7c-add6-1466996f0655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41780
2813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.417802813
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.327778845
Short name T666
Test name
Test status
Simulation time 2456878810 ps
CPU time 33.19 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:28:13 PM PDT 24
Peak memory 256260 kb
Host smart-41e1c515-4401-432a-8a29-ab455f94ba4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32777
8845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.327778845
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3674734520
Short name T334
Test name
Test status
Simulation time 33860651900 ps
CPU time 2056.17 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 03:02:07 PM PDT 24
Peak memory 289844 kb
Host smart-741fdcbb-650b-4903-9cd2-278e8fb7e0e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674734520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3674734520
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4044671916
Short name T549
Test name
Test status
Simulation time 26967675673 ps
CPU time 1210.67 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:48:02 PM PDT 24
Peak memory 288644 kb
Host smart-52f4c9ba-023d-43c2-9f3f-19d7d0e0442c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044671916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4044671916
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3434108007
Short name T314
Test name
Test status
Simulation time 5831895167 ps
CPU time 263.09 seconds
Started Mar 21 02:27:52 PM PDT 24
Finished Mar 21 02:32:15 PM PDT 24
Peak memory 248096 kb
Host smart-e64ee8d0-b05c-42d5-998b-86c8d44b0542
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434108007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3434108007
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3855749647
Short name T509
Test name
Test status
Simulation time 543614417 ps
CPU time 32.22 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:28:12 PM PDT 24
Peak memory 256068 kb
Host smart-73858806-10c8-431e-ba27-4ae2b1131669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38557
49647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3855749647
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.423254212
Short name T423
Test name
Test status
Simulation time 2056388634 ps
CPU time 33.6 seconds
Started Mar 21 02:27:45 PM PDT 24
Finished Mar 21 02:28:18 PM PDT 24
Peak memory 248884 kb
Host smart-fee9d708-f33c-47e4-b495-634a7a8edc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42325
4212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.423254212
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1656482713
Short name T37
Test name
Test status
Simulation time 571133926 ps
CPU time 16.32 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:28:07 PM PDT 24
Peak memory 277604 kb
Host smart-8f329216-1ca1-4c51-86f1-75c2128b4a13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1656482713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1656482713
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.883790885
Short name T278
Test name
Test status
Simulation time 896192268 ps
CPU time 59.67 seconds
Started Mar 21 02:27:41 PM PDT 24
Finished Mar 21 02:28:41 PM PDT 24
Peak memory 256104 kb
Host smart-5e9752d9-568f-4d4e-a1ff-fc4351f85341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88379
0885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.883790885
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2306042297
Short name T648
Test name
Test status
Simulation time 566869782 ps
CPU time 35.19 seconds
Started Mar 21 02:27:40 PM PDT 24
Finished Mar 21 02:28:15 PM PDT 24
Peak memory 248888 kb
Host smart-783c17be-0fb0-40c9-ad4f-d964f34eb8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23060
42297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2306042297
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.134014959
Short name T652
Test name
Test status
Simulation time 62225656811 ps
CPU time 1951.9 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 03:02:25 PM PDT 24
Peak memory 281648 kb
Host smart-0796d6cd-8e48-4fcd-a018-6c760c5cffe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134014959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.134014959
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2422237243
Short name T519
Test name
Test status
Simulation time 16493488523 ps
CPU time 271.61 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 02:34:25 PM PDT 24
Peak memory 256696 kb
Host smart-87deca56-671f-409d-a056-dd171ffbc5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24222
37243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2422237243
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.667063253
Short name T362
Test name
Test status
Simulation time 554127037 ps
CPU time 29.91 seconds
Started Mar 21 02:29:59 PM PDT 24
Finished Mar 21 02:30:29 PM PDT 24
Peak memory 255380 kb
Host smart-305aa203-2a1d-487c-a270-56504f15d887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66706
3253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.667063253
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.531608947
Short name T17
Test name
Test status
Simulation time 12887038593 ps
CPU time 1168.55 seconds
Started Mar 21 02:30:14 PM PDT 24
Finished Mar 21 02:49:43 PM PDT 24
Peak memory 273392 kb
Host smart-a28057f1-b076-4a12-b5c1-4509fe751b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531608947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.531608947
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2849467861
Short name T98
Test name
Test status
Simulation time 25763812598 ps
CPU time 1887.17 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 03:01:39 PM PDT 24
Peak memory 272748 kb
Host smart-f4a32865-c625-4fa0-a96d-88498ea94838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849467861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2849467861
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.530835222
Short name T622
Test name
Test status
Simulation time 4887478236 ps
CPU time 97.09 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 02:31:48 PM PDT 24
Peak memory 247984 kb
Host smart-bfb6c77b-e46c-4aff-a1c2-6718e367c919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530835222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.530835222
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2297886541
Short name T50
Test name
Test status
Simulation time 201225404 ps
CPU time 9.98 seconds
Started Mar 21 02:29:56 PM PDT 24
Finished Mar 21 02:30:07 PM PDT 24
Peak memory 255016 kb
Host smart-7ad350aa-cc27-4c96-88c8-37f5df62677a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22978
86541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2297886541
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3675611206
Short name T369
Test name
Test status
Simulation time 2158606306 ps
CPU time 41.23 seconds
Started Mar 21 02:29:53 PM PDT 24
Finished Mar 21 02:30:35 PM PDT 24
Peak memory 255280 kb
Host smart-f048d09b-4850-42a0-a00c-081e12c2972f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36756
11206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3675611206
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2588149445
Short name T279
Test name
Test status
Simulation time 1952357147 ps
CPU time 47.64 seconds
Started Mar 21 02:29:52 PM PDT 24
Finished Mar 21 02:30:40 PM PDT 24
Peak memory 256720 kb
Host smart-6869a5eb-5aba-49b5-9de1-dfe4a7c6de78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25881
49445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2588149445
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2062432674
Short name T612
Test name
Test status
Simulation time 775345374 ps
CPU time 35.41 seconds
Started Mar 21 02:29:51 PM PDT 24
Finished Mar 21 02:30:27 PM PDT 24
Peak memory 248900 kb
Host smart-7c07ad7b-4169-4cfd-8049-3ee0f4e9a5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20624
32674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2062432674
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.559324510
Short name T285
Test name
Test status
Simulation time 33802364103 ps
CPU time 1620.19 seconds
Started Mar 21 02:30:12 PM PDT 24
Finished Mar 21 02:57:13 PM PDT 24
Peak memory 284384 kb
Host smart-451c3668-333e-432a-99b3-88e147971376
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559324510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.559324510
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3662393697
Short name T91
Test name
Test status
Simulation time 318875729336 ps
CPU time 7876.03 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 04:41:28 PM PDT 24
Peak memory 337892 kb
Host smart-3c125547-33e7-4eb4-9540-89c9c0762d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662393697 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3662393697
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.67511513
Short name T593
Test name
Test status
Simulation time 2791406667 ps
CPU time 161.3 seconds
Started Mar 21 02:30:12 PM PDT 24
Finished Mar 21 02:32:54 PM PDT 24
Peak memory 249980 kb
Host smart-dc6b8d7c-bc22-48cf-a72a-b062e597fbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67511
513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.67511513
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.512522963
Short name T545
Test name
Test status
Simulation time 22838798 ps
CPU time 3.16 seconds
Started Mar 21 02:30:10 PM PDT 24
Finished Mar 21 02:30:14 PM PDT 24
Peak memory 239208 kb
Host smart-ef7ae1f3-2b96-490c-8375-f65da04aa8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51252
2963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.512522963
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1380613042
Short name T323
Test name
Test status
Simulation time 43578582839 ps
CPU time 2582.66 seconds
Started Mar 21 02:30:10 PM PDT 24
Finished Mar 21 03:13:14 PM PDT 24
Peak memory 281696 kb
Host smart-6838996d-8a12-4474-8bad-03b5fad3db83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380613042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1380613042
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1778558556
Short name T651
Test name
Test status
Simulation time 100265424866 ps
CPU time 1586.46 seconds
Started Mar 21 02:30:12 PM PDT 24
Finished Mar 21 02:56:40 PM PDT 24
Peak memory 265324 kb
Host smart-16882526-1407-49f5-80cb-86a338576b34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778558556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1778558556
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1357591204
Short name T300
Test name
Test status
Simulation time 47046699346 ps
CPU time 572.14 seconds
Started Mar 21 02:30:09 PM PDT 24
Finished Mar 21 02:39:42 PM PDT 24
Peak memory 246968 kb
Host smart-cfc61539-225d-4e5d-9917-28bd15444bfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357591204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1357591204
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2283872910
Short name T233
Test name
Test status
Simulation time 894185336 ps
CPU time 27.03 seconds
Started Mar 21 02:30:13 PM PDT 24
Finished Mar 21 02:30:40 PM PDT 24
Peak memory 248880 kb
Host smart-4a543f16-a883-45e1-98fd-c757dae6d8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22838
72910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2283872910
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4075920951
Short name T635
Test name
Test status
Simulation time 20215503 ps
CPU time 3.26 seconds
Started Mar 21 02:30:12 PM PDT 24
Finished Mar 21 02:30:16 PM PDT 24
Peak memory 240624 kb
Host smart-8dd7eff6-cf19-4775-a89c-901c9db84e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40759
20951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4075920951
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3361071637
Short name T375
Test name
Test status
Simulation time 721767899 ps
CPU time 49.03 seconds
Started Mar 21 02:30:12 PM PDT 24
Finished Mar 21 02:31:02 PM PDT 24
Peak memory 256572 kb
Host smart-0e5c305e-ac7b-4cf3-9fe9-7eb9238a2ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33610
71637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3361071637
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4040551119
Short name T422
Test name
Test status
Simulation time 897096412 ps
CPU time 16.76 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 02:30:29 PM PDT 24
Peak memory 249136 kb
Host smart-c53aac11-d53b-4fee-a9dd-b5d302ead8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40405
51119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4040551119
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.289964782
Short name T268
Test name
Test status
Simulation time 37580694263 ps
CPU time 603.55 seconds
Started Mar 21 02:30:12 PM PDT 24
Finished Mar 21 02:40:17 PM PDT 24
Peak memory 265296 kb
Host smart-14578496-c625-4484-a5eb-9a9a9d2964d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289964782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.289964782
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1407995639
Short name T30
Test name
Test status
Simulation time 41736579834 ps
CPU time 3506.65 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 03:28:38 PM PDT 24
Peak memory 305460 kb
Host smart-d2a0d50a-a4d8-4d1f-ab2a-4ee58977bd97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407995639 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1407995639
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4282837496
Short name T273
Test name
Test status
Simulation time 36078067968 ps
CPU time 2147.75 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 03:05:59 PM PDT 24
Peak memory 281752 kb
Host smart-cb2c3be8-26bd-4dc9-8400-5fc5f8bf4ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282837496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4282837496
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2063899854
Short name T383
Test name
Test status
Simulation time 3026220137 ps
CPU time 165.36 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 02:32:57 PM PDT 24
Peak memory 256664 kb
Host smart-780781ae-df98-4cc5-bac0-b8d90f84788d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
99854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2063899854
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3576915876
Short name T86
Test name
Test status
Simulation time 4802102981 ps
CPU time 75.74 seconds
Started Mar 21 02:30:15 PM PDT 24
Finished Mar 21 02:31:31 PM PDT 24
Peak memory 255644 kb
Host smart-7fc2fe0d-0320-406d-a626-2705b0d5f5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35769
15876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3576915876
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3544219919
Short name T293
Test name
Test status
Simulation time 120856925227 ps
CPU time 2169.48 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 03:06:37 PM PDT 24
Peak memory 289420 kb
Host smart-4d59ec93-dde6-4255-aaf3-1f413c15edbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544219919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3544219919
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3025467688
Short name T582
Test name
Test status
Simulation time 82222318264 ps
CPU time 2577.52 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 03:13:25 PM PDT 24
Peak memory 282144 kb
Host smart-d6b36fad-417e-4a53-8894-28f1a420afed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025467688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3025467688
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4094499409
Short name T636
Test name
Test status
Simulation time 12161008724 ps
CPU time 215.29 seconds
Started Mar 21 02:30:11 PM PDT 24
Finished Mar 21 02:33:47 PM PDT 24
Peak memory 246876 kb
Host smart-5504aac0-cb9b-4cba-844e-f4e3064d6700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094499409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4094499409
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2388058040
Short name T663
Test name
Test status
Simulation time 399113354 ps
CPU time 12.28 seconds
Started Mar 21 02:30:10 PM PDT 24
Finished Mar 21 02:30:23 PM PDT 24
Peak memory 249060 kb
Host smart-e1db3c1b-26ca-4f79-9c99-4c8d06a35875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
58040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2388058040
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2222632105
Short name T676
Test name
Test status
Simulation time 1228808084 ps
CPU time 22.77 seconds
Started Mar 21 02:30:13 PM PDT 24
Finished Mar 21 02:30:36 PM PDT 24
Peak memory 248780 kb
Host smart-1a9bd26f-2a42-4e14-bed1-7ca10721f564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
32105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2222632105
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1431900781
Short name T378
Test name
Test status
Simulation time 73641493 ps
CPU time 9.26 seconds
Started Mar 21 02:30:10 PM PDT 24
Finished Mar 21 02:30:19 PM PDT 24
Peak memory 249352 kb
Host smart-b2cad966-4e9d-42fd-82ea-d54fa7c2582f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
00781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1431900781
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.803308601
Short name T377
Test name
Test status
Simulation time 1174209683 ps
CPU time 33.39 seconds
Started Mar 21 02:30:15 PM PDT 24
Finished Mar 21 02:30:49 PM PDT 24
Peak memory 256612 kb
Host smart-dd5fbcc1-9c74-40cc-857a-332cbf8e9cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80330
8601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.803308601
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1551227714
Short name T690
Test name
Test status
Simulation time 1983306149 ps
CPU time 121.52 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 02:32:30 PM PDT 24
Peak memory 255344 kb
Host smart-90d93a2e-4723-48cd-81b0-4cbe615f9235
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551227714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1551227714
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.440619779
Short name T592
Test name
Test status
Simulation time 21449263692 ps
CPU time 1172.77 seconds
Started Mar 21 02:30:29 PM PDT 24
Finished Mar 21 02:50:02 PM PDT 24
Peak memory 273484 kb
Host smart-1c96e2a1-cce1-41c4-bbb7-e7366af0a9a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440619779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.440619779
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3579634509
Short name T95
Test name
Test status
Simulation time 6621862399 ps
CPU time 82.21 seconds
Started Mar 21 02:30:26 PM PDT 24
Finished Mar 21 02:31:49 PM PDT 24
Peak memory 256848 kb
Host smart-3bc047bd-0558-4e76-bfdc-99f79bb635f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35796
34509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3579634509
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2838398236
Short name T687
Test name
Test status
Simulation time 434848002 ps
CPU time 34.18 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 02:31:03 PM PDT 24
Peak memory 255636 kb
Host smart-ac748f0c-3bd2-4c1a-b23d-ea2c5efea06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28383
98236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2838398236
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3427988231
Short name T329
Test name
Test status
Simulation time 100947560169 ps
CPU time 1446.42 seconds
Started Mar 21 02:30:25 PM PDT 24
Finished Mar 21 02:54:32 PM PDT 24
Peak memory 272548 kb
Host smart-a741a1ab-0e30-49c4-af8b-f633139735ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427988231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3427988231
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.209923251
Short name T8
Test name
Test status
Simulation time 54197645513 ps
CPU time 3155.12 seconds
Started Mar 21 02:30:25 PM PDT 24
Finished Mar 21 03:23:00 PM PDT 24
Peak memory 289336 kb
Host smart-b2ab0e5a-6e62-4bd0-91df-49b7cd66c599
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209923251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.209923251
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2822017647
Short name T688
Test name
Test status
Simulation time 5971383215 ps
CPU time 255.49 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 02:34:43 PM PDT 24
Peak memory 255332 kb
Host smart-28c5ea94-4399-48f8-a53d-b54f719587ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822017647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2822017647
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4213498879
Short name T478
Test name
Test status
Simulation time 341001094 ps
CPU time 23.75 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 02:30:52 PM PDT 24
Peak memory 256080 kb
Host smart-8622c2ac-e5f0-4ff4-bb85-abc4e820b60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
98879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4213498879
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3593186732
Short name T71
Test name
Test status
Simulation time 905301363 ps
CPU time 20.58 seconds
Started Mar 21 02:30:26 PM PDT 24
Finished Mar 21 02:30:47 PM PDT 24
Peak memory 253840 kb
Host smart-ebb31a21-ab8d-4824-85a2-eec67d1dfd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35931
86732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3593186732
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.543172362
Short name T621
Test name
Test status
Simulation time 950461717 ps
CPU time 10.86 seconds
Started Mar 21 02:30:30 PM PDT 24
Finished Mar 21 02:30:41 PM PDT 24
Peak memory 253380 kb
Host smart-0bf04ebd-4435-4bd7-ad75-120134bf3982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54317
2362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.543172362
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2840119761
Short name T193
Test name
Test status
Simulation time 418290433 ps
CPU time 21.3 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 02:30:49 PM PDT 24
Peak memory 255708 kb
Host smart-8456e9e8-c07f-4b43-9054-f1347d9ad370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
19761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2840119761
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3788619214
Short name T24
Test name
Test status
Simulation time 31791096092 ps
CPU time 1555.87 seconds
Started Mar 21 02:30:30 PM PDT 24
Finished Mar 21 02:56:26 PM PDT 24
Peak memory 289876 kb
Host smart-9e57065d-d744-4b30-9bb9-091aebc6e27a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788619214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3788619214
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.4266582193
Short name T177
Test name
Test status
Simulation time 17732973366 ps
CPU time 1091.13 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 02:48:39 PM PDT 24
Peak memory 265460 kb
Host smart-dc39751d-d905-4c6a-8de4-bf87b8c6b2a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266582193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.4266582193
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.403136567
Short name T263
Test name
Test status
Simulation time 4675125051 ps
CPU time 113.83 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 02:32:21 PM PDT 24
Peak memory 249916 kb
Host smart-77dc7f6e-c982-4a55-93f8-bf9d5a39bb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
6567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.403136567
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1044114090
Short name T516
Test name
Test status
Simulation time 141297560 ps
CPU time 13.77 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 02:30:41 PM PDT 24
Peak memory 255576 kb
Host smart-4dc23158-8b5d-4654-ace5-1c14e12eaba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10441
14090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1044114090
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.155526949
Short name T392
Test name
Test status
Simulation time 31431316906 ps
CPU time 704.06 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 02:42:11 PM PDT 24
Peak memory 273320 kb
Host smart-45d47977-08ab-4b00-be3b-0191caf583d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155526949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.155526949
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.499486415
Short name T295
Test name
Test status
Simulation time 34087558803 ps
CPU time 442.1 seconds
Started Mar 21 02:30:27 PM PDT 24
Finished Mar 21 02:37:49 PM PDT 24
Peak memory 247844 kb
Host smart-e4b713fb-aab1-4de1-99c0-d09bde8e7008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499486415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.499486415
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.673867621
Short name T546
Test name
Test status
Simulation time 2142898007 ps
CPU time 37.76 seconds
Started Mar 21 02:30:29 PM PDT 24
Finished Mar 21 02:31:07 PM PDT 24
Peak memory 249032 kb
Host smart-538846c3-8d2c-4ba7-8206-5c2fc560fd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67386
7621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.673867621
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2060769695
Short name T272
Test name
Test status
Simulation time 377002669 ps
CPU time 25.53 seconds
Started Mar 21 02:30:28 PM PDT 24
Finished Mar 21 02:30:54 PM PDT 24
Peak memory 253872 kb
Host smart-bbdba82a-eaeb-4245-a38a-dd416ba69d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20607
69695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2060769695
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1870153141
Short name T373
Test name
Test status
Simulation time 983604594 ps
CPU time 30.39 seconds
Started Mar 21 02:30:29 PM PDT 24
Finished Mar 21 02:30:59 PM PDT 24
Peak memory 248868 kb
Host smart-1fdba30f-0b4a-4c27-b6da-bbb42264e8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18701
53141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1870153141
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1663764654
Short name T536
Test name
Test status
Simulation time 222620801 ps
CPU time 9.8 seconds
Started Mar 21 02:30:29 PM PDT 24
Finished Mar 21 02:30:39 PM PDT 24
Peak memory 248868 kb
Host smart-7d069e8a-c802-4f5e-a5a3-d77c22d83e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16637
64654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1663764654
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1806301872
Short name T203
Test name
Test status
Simulation time 88804617534 ps
CPU time 9305.95 seconds
Started Mar 21 02:30:43 PM PDT 24
Finished Mar 21 05:05:51 PM PDT 24
Peak memory 394484 kb
Host smart-98649fe6-6495-4e29-94b5-9291a3c00a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806301872 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1806301872
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1747462608
Short name T670
Test name
Test status
Simulation time 8772756800 ps
CPU time 1054.97 seconds
Started Mar 21 02:30:41 PM PDT 24
Finished Mar 21 02:48:17 PM PDT 24
Peak memory 285700 kb
Host smart-d673b9b4-b686-4928-b059-2b9982b303b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747462608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1747462608
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1515118407
Short name T586
Test name
Test status
Simulation time 8299752152 ps
CPU time 124.1 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 02:32:49 PM PDT 24
Peak memory 256740 kb
Host smart-ff8f8a24-30c0-4ac7-b0eb-e1b75d42a3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
18407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1515118407
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2777368033
Short name T533
Test name
Test status
Simulation time 1139486511 ps
CPU time 24.52 seconds
Started Mar 21 02:30:44 PM PDT 24
Finished Mar 21 02:31:08 PM PDT 24
Peak memory 248760 kb
Host smart-c2bd21f1-0353-4024-a740-7efa66f053cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27773
68033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2777368033
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2800467522
Short name T330
Test name
Test status
Simulation time 16557773590 ps
CPU time 779.18 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 02:43:42 PM PDT 24
Peak memory 272948 kb
Host smart-9be0fafa-5728-4d45-848d-cf7c7771ab00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800467522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2800467522
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2989570250
Short name T597
Test name
Test status
Simulation time 191844251342 ps
CPU time 2294.71 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 03:08:58 PM PDT 24
Peak memory 289536 kb
Host smart-5c6f05b8-026a-4ae7-b516-33b24c302d05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989570250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2989570250
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.803672997
Short name T521
Test name
Test status
Simulation time 2263152319 ps
CPU time 90.97 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 02:32:13 PM PDT 24
Peak memory 246956 kb
Host smart-24d2011f-4d4c-425a-9570-cb90779894f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803672997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.803672997
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2352355094
Short name T615
Test name
Test status
Simulation time 420852264 ps
CPU time 34.25 seconds
Started Mar 21 02:30:43 PM PDT 24
Finished Mar 21 02:31:18 PM PDT 24
Peak memory 248880 kb
Host smart-d5e7132f-21de-4259-9a88-ee0fd2663d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23523
55094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2352355094
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2127795619
Short name T567
Test name
Test status
Simulation time 712892375 ps
CPU time 36.67 seconds
Started Mar 21 02:30:41 PM PDT 24
Finished Mar 21 02:31:18 PM PDT 24
Peak memory 247800 kb
Host smart-4bc1bd02-4b01-44dc-a226-bb932e3fcad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21277
95619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2127795619
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3258934213
Short name T473
Test name
Test status
Simulation time 86273390 ps
CPU time 9.29 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 02:30:51 PM PDT 24
Peak memory 254772 kb
Host smart-7d70403e-2162-4d49-81fd-a17e9db043c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
34213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3258934213
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.679589146
Short name T577
Test name
Test status
Simulation time 403707354 ps
CPU time 30.77 seconds
Started Mar 21 02:30:43 PM PDT 24
Finished Mar 21 02:31:14 PM PDT 24
Peak memory 248924 kb
Host smart-5823ce62-55a5-4667-a507-17afd3f774d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67958
9146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.679589146
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1896126586
Short name T579
Test name
Test status
Simulation time 20787179945 ps
CPU time 1122.8 seconds
Started Mar 21 02:30:44 PM PDT 24
Finished Mar 21 02:49:27 PM PDT 24
Peak memory 284452 kb
Host smart-a4ec3b5e-2b3e-426e-aef4-0e4456e9b23e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896126586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1896126586
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.445475547
Short name T109
Test name
Test status
Simulation time 2180336451 ps
CPU time 258.57 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 02:35:01 PM PDT 24
Peak memory 265352 kb
Host smart-56d70ad4-b878-48d0-9f80-c8a9122c776b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445475547 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.445475547
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3461527970
Short name T5
Test name
Test status
Simulation time 80965652012 ps
CPU time 913.67 seconds
Started Mar 21 02:30:40 PM PDT 24
Finished Mar 21 02:45:54 PM PDT 24
Peak memory 273420 kb
Host smart-c9a84aaf-67a0-40a7-9daa-5645ece0c788
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461527970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3461527970
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1562664526
Short name T66
Test name
Test status
Simulation time 9980793856 ps
CPU time 148.09 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 02:33:13 PM PDT 24
Peak memory 249028 kb
Host smart-f52303ea-b54a-43ed-8f7e-cd6a66b71ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
64526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1562664526
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.971318897
Short name T619
Test name
Test status
Simulation time 1377102188 ps
CPU time 45.33 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 02:31:28 PM PDT 24
Peak memory 255648 kb
Host smart-0ab0bbd6-c81f-4e99-bad5-8b216d037082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97131
8897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.971318897
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3580710627
Short name T527
Test name
Test status
Simulation time 18569968183 ps
CPU time 1365.53 seconds
Started Mar 21 02:31:31 PM PDT 24
Finished Mar 21 02:54:17 PM PDT 24
Peak memory 265320 kb
Host smart-8270f6e1-36e8-4d94-a415-eb6b4312421f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580710627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3580710627
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.566808887
Short name T320
Test name
Test status
Simulation time 50328583904 ps
CPU time 539.94 seconds
Started Mar 21 02:30:43 PM PDT 24
Finished Mar 21 02:39:44 PM PDT 24
Peak memory 248080 kb
Host smart-442b9ad5-8b5f-40d4-b302-af9d7d9bd3d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566808887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.566808887
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.58724750
Short name T431
Test name
Test status
Simulation time 154378406 ps
CPU time 5.88 seconds
Started Mar 21 02:30:42 PM PDT 24
Finished Mar 21 02:30:48 PM PDT 24
Peak memory 248860 kb
Host smart-fd4f37a1-14e8-4438-bf05-8bcf673d27ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58724
750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.58724750
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3469284352
Short name T412
Test name
Test status
Simulation time 1016609891 ps
CPU time 22.06 seconds
Started Mar 21 02:30:43 PM PDT 24
Finished Mar 21 02:31:05 PM PDT 24
Peak memory 247660 kb
Host smart-88b7afd5-ba8f-4d58-9e89-532d6d886883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
84352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3469284352
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.979373227
Short name T564
Test name
Test status
Simulation time 461092248 ps
CPU time 26.66 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 02:31:11 PM PDT 24
Peak memory 248880 kb
Host smart-8e774a81-9b7a-489b-8df0-a4603b83cc6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97937
3227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.979373227
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2797606200
Short name T571
Test name
Test status
Simulation time 556489853 ps
CPU time 37.73 seconds
Started Mar 21 02:30:44 PM PDT 24
Finished Mar 21 02:31:22 PM PDT 24
Peak memory 248724 kb
Host smart-10d93e14-8ddd-453a-90ff-56d1eab49f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27976
06200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2797606200
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1480576645
Short name T626
Test name
Test status
Simulation time 30623888795 ps
CPU time 1947.89 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 03:03:13 PM PDT 24
Peak memory 273520 kb
Host smart-46e75ff7-a87c-47d1-8ab7-761de4fe7330
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480576645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1480576645
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.615969342
Short name T200
Test name
Test status
Simulation time 200463951097 ps
CPU time 3233.44 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 03:24:39 PM PDT 24
Peak memory 305952 kb
Host smart-a0dd53ce-5efe-41e9-b01f-ae6a0be5f313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615969342 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.615969342
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.829324667
Short name T444
Test name
Test status
Simulation time 4657771747 ps
CPU time 144.6 seconds
Started Mar 21 02:30:41 PM PDT 24
Finished Mar 21 02:33:06 PM PDT 24
Peak memory 256868 kb
Host smart-4da97236-7512-4720-bd9a-691581096566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82932
4667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.829324667
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3338127773
Short name T178
Test name
Test status
Simulation time 280857706 ps
CPU time 21.93 seconds
Started Mar 21 02:30:41 PM PDT 24
Finished Mar 21 02:31:03 PM PDT 24
Peak memory 255988 kb
Host smart-8caf24ef-ed8f-42bc-9f5b-c1dd791b4356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33381
27773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3338127773
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2563867281
Short name T339
Test name
Test status
Simulation time 102107156365 ps
CPU time 3314.1 seconds
Started Mar 21 02:30:57 PM PDT 24
Finished Mar 21 03:26:12 PM PDT 24
Peak memory 289336 kb
Host smart-b4da040c-ec67-4e38-8376-935c83c877a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563867281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2563867281
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.678066629
Short name T196
Test name
Test status
Simulation time 158517596850 ps
CPU time 2690.02 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 03:15:48 PM PDT 24
Peak memory 289396 kb
Host smart-8b2f28f8-91c8-4b96-885a-a861b00dca01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678066629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.678066629
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1008814530
Short name T111
Test name
Test status
Simulation time 1667974980 ps
CPU time 42.09 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 02:31:27 PM PDT 24
Peak memory 255996 kb
Host smart-dce223c1-a5f4-4757-bd01-e5f61d6f4ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10088
14530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1008814530
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3083362586
Short name T548
Test name
Test status
Simulation time 3541152066 ps
CPU time 28.57 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 02:31:13 PM PDT 24
Peak memory 255280 kb
Host smart-4f92b059-1402-4aa4-8002-4bcd23690591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30833
62586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3083362586
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1587394260
Short name T486
Test name
Test status
Simulation time 467333054 ps
CPU time 34.34 seconds
Started Mar 21 02:30:45 PM PDT 24
Finished Mar 21 02:31:19 PM PDT 24
Peak memory 254008 kb
Host smart-df53b781-18de-400b-95a5-d4aa1a2eaa0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
94260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1587394260
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2503490062
Short name T695
Test name
Test status
Simulation time 308322747 ps
CPU time 25.71 seconds
Started Mar 21 02:30:41 PM PDT 24
Finished Mar 21 02:31:07 PM PDT 24
Peak memory 255376 kb
Host smart-85c2fa7a-dffc-450c-bbaf-5b3b67d95bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
90062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2503490062
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.209313818
Short name T707
Test name
Test status
Simulation time 41335493452 ps
CPU time 2774.87 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 03:17:14 PM PDT 24
Peak memory 289432 kb
Host smart-800c74a4-4402-4a97-b1b7-c8db07f0ff1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209313818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.209313818
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1399084072
Short name T528
Test name
Test status
Simulation time 59208856354 ps
CPU time 1798.98 seconds
Started Mar 21 02:30:56 PM PDT 24
Finished Mar 21 03:00:56 PM PDT 24
Peak memory 273284 kb
Host smart-da2495f1-f9cf-4bc1-b5d9-a1cefd076443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399084072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1399084072
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2150492754
Short name T453
Test name
Test status
Simulation time 11915613842 ps
CPU time 190.21 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 02:34:08 PM PDT 24
Peak memory 257072 kb
Host smart-98c2f49c-d6fa-490b-93ad-fc18950c9526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504
92754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2150492754
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1422716913
Short name T607
Test name
Test status
Simulation time 1044846908 ps
CPU time 18.13 seconds
Started Mar 21 02:30:56 PM PDT 24
Finished Mar 21 02:31:15 PM PDT 24
Peak memory 252924 kb
Host smart-4833a6e1-81ac-4442-82af-a0eaafc313c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227
16913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1422716913
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1302492424
Short name T336
Test name
Test status
Simulation time 30868537960 ps
CPU time 1769.96 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 03:00:28 PM PDT 24
Peak memory 268316 kb
Host smart-bff2825a-23e5-4eb0-ac99-45d63201233c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302492424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1302492424
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.4219195248
Short name T371
Test name
Test status
Simulation time 34221139442 ps
CPU time 1890.49 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 03:02:29 PM PDT 24
Peak memory 289460 kb
Host smart-47c97f0c-170f-407f-be15-596aa9796579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219195248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.4219195248
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2149764858
Short name T503
Test name
Test status
Simulation time 878649428 ps
CPU time 19.35 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 02:31:19 PM PDT 24
Peak memory 248884 kb
Host smart-b49ae38c-3eda-4ab6-8c62-ae8011be1817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21497
64858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2149764858
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.840580616
Short name T79
Test name
Test status
Simulation time 332721100 ps
CPU time 16.42 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 02:31:16 PM PDT 24
Peak memory 252952 kb
Host smart-2c15cbe0-1658-490a-9156-2a7e59546205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84058
0616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.840580616
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3341956298
Short name T385
Test name
Test status
Simulation time 1736682606 ps
CPU time 36.06 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 02:31:35 PM PDT 24
Peak memory 255624 kb
Host smart-6fd474ab-323a-4a5c-b72b-1d698399ea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33419
56298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3341956298
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.4279146400
Short name T103
Test name
Test status
Simulation time 63775381705 ps
CPU time 2296 seconds
Started Mar 21 02:31:00 PM PDT 24
Finished Mar 21 03:09:16 PM PDT 24
Peak memory 289952 kb
Host smart-89b62adb-5659-470e-be35-9ea600623a67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279146400 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.4279146400
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3370262085
Short name T234
Test name
Test status
Simulation time 46861358162 ps
CPU time 3051.3 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 03:21:51 PM PDT 24
Peak memory 281588 kb
Host smart-14ad73c0-d2e8-4fd6-b1fd-aec0e31f1f4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370262085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3370262085
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1351760281
Short name T398
Test name
Test status
Simulation time 3385310129 ps
CPU time 127.68 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 02:33:06 PM PDT 24
Peak memory 256856 kb
Host smart-1dd4c38b-1e9b-4ef6-b567-d08f308467b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13517
60281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1351760281
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.33462921
Short name T480
Test name
Test status
Simulation time 1443112485 ps
CPU time 32.06 seconds
Started Mar 21 02:30:57 PM PDT 24
Finished Mar 21 02:31:29 PM PDT 24
Peak memory 255312 kb
Host smart-5a07cab9-801b-4376-8e94-473ad08ccaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33462
921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.33462921
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3551643849
Short name T337
Test name
Test status
Simulation time 308913594856 ps
CPU time 1636.87 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 02:58:16 PM PDT 24
Peak memory 267348 kb
Host smart-b966116c-3603-46d9-ae52-ef234d624555
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551643849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3551643849
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3778366678
Short name T262
Test name
Test status
Simulation time 43073512314 ps
CPU time 1086.6 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 02:49:05 PM PDT 24
Peak memory 273460 kb
Host smart-b72b6c6f-0c07-4b1d-a1fe-69b70d7edb4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778366678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3778366678
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1219001593
Short name T462
Test name
Test status
Simulation time 7469757426 ps
CPU time 291.32 seconds
Started Mar 21 02:30:56 PM PDT 24
Finished Mar 21 02:35:48 PM PDT 24
Peak memory 247824 kb
Host smart-69cfe7e1-412f-43ab-b66a-ccb26fb4fd0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219001593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1219001593
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2935299633
Short name T38
Test name
Test status
Simulation time 282574164 ps
CPU time 16.09 seconds
Started Mar 21 02:31:02 PM PDT 24
Finished Mar 21 02:31:19 PM PDT 24
Peak memory 254076 kb
Host smart-96bde8e7-7aae-45ba-b025-6278e20e9d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29352
99633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2935299633
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3950716960
Short name T55
Test name
Test status
Simulation time 639899702 ps
CPU time 26.61 seconds
Started Mar 21 02:30:57 PM PDT 24
Finished Mar 21 02:31:24 PM PDT 24
Peak memory 255440 kb
Host smart-eb05af3a-17e4-4c71-82c7-099a0a792a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39507
16960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3950716960
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1482830218
Short name T667
Test name
Test status
Simulation time 230692808 ps
CPU time 15.27 seconds
Started Mar 21 02:30:57 PM PDT 24
Finished Mar 21 02:31:12 PM PDT 24
Peak memory 253100 kb
Host smart-7a0250a3-44d2-4057-b46c-87fe96eab62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14828
30218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1482830218
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.972501334
Short name T227
Test name
Test status
Simulation time 724907786 ps
CPU time 39.91 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 02:31:38 PM PDT 24
Peak memory 248916 kb
Host smart-0239f5b8-8a54-440a-8a48-95cba9643578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97250
1334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.972501334
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2104645968
Short name T257
Test name
Test status
Simulation time 191843516368 ps
CPU time 3548.63 seconds
Started Mar 21 02:31:00 PM PDT 24
Finished Mar 21 03:30:09 PM PDT 24
Peak memory 302916 kb
Host smart-e0efa689-d50a-4f95-b230-1aafeccdc333
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104645968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2104645968
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2494905051
Short name T217
Test name
Test status
Simulation time 26802917 ps
CPU time 2.59 seconds
Started Mar 21 02:27:48 PM PDT 24
Finished Mar 21 02:27:52 PM PDT 24
Peak memory 249088 kb
Host smart-d7024a62-b67b-420b-a243-8bedd944f3dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2494905051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2494905051
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.816719496
Short name T65
Test name
Test status
Simulation time 9879075555 ps
CPU time 793.04 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:41:05 PM PDT 24
Peak memory 283840 kb
Host smart-687c93f7-f027-4dc8-bb1a-0a751adf977e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816719496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.816719496
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3243787566
Short name T435
Test name
Test status
Simulation time 1377193847 ps
CPU time 31.96 seconds
Started Mar 21 02:27:53 PM PDT 24
Finished Mar 21 02:28:27 PM PDT 24
Peak memory 248868 kb
Host smart-fdd9456a-2b6a-48f0-910f-7748e299d0af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3243787566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3243787566
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2128303638
Short name T463
Test name
Test status
Simulation time 20185420970 ps
CPU time 289.26 seconds
Started Mar 21 02:27:55 PM PDT 24
Finished Mar 21 02:32:45 PM PDT 24
Peak memory 255660 kb
Host smart-3c7779e9-64f4-4018-b494-f65775fdd756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21283
03638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2128303638
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2793782344
Short name T529
Test name
Test status
Simulation time 193498258 ps
CPU time 9.95 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:28:01 PM PDT 24
Peak memory 254880 kb
Host smart-1ab75703-405a-4486-8a16-64a73c1dd818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27937
82344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2793782344
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.301101136
Short name T11
Test name
Test status
Simulation time 11379016723 ps
CPU time 1042.2 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 02:45:13 PM PDT 24
Peak memory 273436 kb
Host smart-237a75e6-7102-4f4a-868c-aa2dca5f55e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301101136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.301101136
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2634200464
Short name T418
Test name
Test status
Simulation time 50879968917 ps
CPU time 1127.29 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:46:37 PM PDT 24
Peak memory 289448 kb
Host smart-22f6ceb6-35e3-4f89-b4e6-da82f4d85ae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634200464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2634200464
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2244336353
Short name T304
Test name
Test status
Simulation time 7965597172 ps
CPU time 353.68 seconds
Started Mar 21 02:27:52 PM PDT 24
Finished Mar 21 02:33:46 PM PDT 24
Peak memory 247964 kb
Host smart-a1bb3f6f-1e67-483d-87e8-62fd0f4e9692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244336353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2244336353
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3057142561
Short name T706
Test name
Test status
Simulation time 9420353003 ps
CPU time 50.03 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:28:40 PM PDT 24
Peak memory 257088 kb
Host smart-0e6298f4-a68b-4d1b-8a03-b30e2fc58ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30571
42561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3057142561
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2368263741
Short name T461
Test name
Test status
Simulation time 757050306 ps
CPU time 45.02 seconds
Started Mar 21 02:27:48 PM PDT 24
Finished Mar 21 02:28:34 PM PDT 24
Peak memory 248860 kb
Host smart-140fe15b-bb4c-4f9c-aa84-d22d46cd6962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23682
63741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2368263741
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.201801633
Short name T240
Test name
Test status
Simulation time 745341237 ps
CPU time 47.77 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 02:28:39 PM PDT 24
Peak memory 255072 kb
Host smart-a5b6a0fa-783f-4105-b9a1-cb94ade22711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
1633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.201801633
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1124916323
Short name T428
Test name
Test status
Simulation time 193638228 ps
CPU time 19.23 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 02:28:09 PM PDT 24
Peak memory 248864 kb
Host smart-54d3d94b-b880-46e1-ae85-d1c553eefc83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249
16323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1124916323
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2922971558
Short name T624
Test name
Test status
Simulation time 99971948172 ps
CPU time 1808.84 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:58:00 PM PDT 24
Peak memory 289804 kb
Host smart-ef16a7a6-fde2-4a8b-8320-4044bdd7a0a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922971558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2922971558
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3174267419
Short name T77
Test name
Test status
Simulation time 74377398233 ps
CPU time 2623.04 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 03:14:58 PM PDT 24
Peak memory 289260 kb
Host smart-7ad99731-5bca-45fd-ae10-effe1bf4331e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174267419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3174267419
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.335620452
Short name T686
Test name
Test status
Simulation time 5643838237 ps
CPU time 155.68 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 02:33:35 PM PDT 24
Peak memory 256772 kb
Host smart-a8a41bf2-4733-4fdd-bff1-5c03c65e190b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
0452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.335620452
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.640577221
Short name T553
Test name
Test status
Simulation time 1239638496 ps
CPU time 31.73 seconds
Started Mar 21 02:30:59 PM PDT 24
Finished Mar 21 02:31:31 PM PDT 24
Peak memory 249104 kb
Host smart-66c2195f-2aa9-43f1-9181-293b087ed955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64057
7221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.640577221
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1442263924
Short name T100
Test name
Test status
Simulation time 230985216851 ps
CPU time 1651.23 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 02:58:46 PM PDT 24
Peak memory 272968 kb
Host smart-befbbae6-367d-4c96-9f7b-4734c6e3de73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442263924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1442263924
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1220531427
Short name T179
Test name
Test status
Simulation time 13475402223 ps
CPU time 535.38 seconds
Started Mar 21 02:31:13 PM PDT 24
Finished Mar 21 02:40:09 PM PDT 24
Peak memory 248152 kb
Host smart-4d08abca-5919-4861-8971-7366e03c4054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220531427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1220531427
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.217380152
Short name T182
Test name
Test status
Simulation time 1845924633 ps
CPU time 22.34 seconds
Started Mar 21 02:31:03 PM PDT 24
Finished Mar 21 02:31:25 PM PDT 24
Peak memory 248888 kb
Host smart-ba1260de-be03-4f6f-8e76-46532da5fa46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738
0152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.217380152
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2724283978
Short name T525
Test name
Test status
Simulation time 446045562 ps
CPU time 26.13 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 02:31:24 PM PDT 24
Peak memory 247684 kb
Host smart-fe8d6e3c-d491-4804-ae22-bd0d877db6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27242
83978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2724283978
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1430372973
Short name T647
Test name
Test status
Simulation time 257313162 ps
CPU time 32.46 seconds
Started Mar 21 02:30:57 PM PDT 24
Finished Mar 21 02:31:29 PM PDT 24
Peak memory 254816 kb
Host smart-c144209f-bae7-4e97-84ff-569ee5a8922e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
72973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1430372973
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2108340356
Short name T700
Test name
Test status
Simulation time 1240976230 ps
CPU time 39.35 seconds
Started Mar 21 02:30:58 PM PDT 24
Finished Mar 21 02:31:37 PM PDT 24
Peak memory 248848 kb
Host smart-85ba8838-99b4-4a41-97ae-8c2d5bb31669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
40356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2108340356
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3913683566
Short name T426
Test name
Test status
Simulation time 60906045774 ps
CPU time 3821.21 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 03:34:57 PM PDT 24
Peak memory 289632 kb
Host smart-94f0bd98-6aea-4b44-8047-67e66777f794
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913683566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3913683566
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2756149403
Short name T699
Test name
Test status
Simulation time 137744475656 ps
CPU time 6663.76 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 04:22:21 PM PDT 24
Peak memory 354300 kb
Host smart-43c1f6c2-06ce-4ba2-aa90-cd746469a8aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756149403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2756149403
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1956526630
Short name T52
Test name
Test status
Simulation time 412238738502 ps
CPU time 2630.11 seconds
Started Mar 21 02:31:48 PM PDT 24
Finished Mar 21 03:15:38 PM PDT 24
Peak memory 289244 kb
Host smart-d4cac7d9-157d-4dbd-9d87-fd29e5410f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956526630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1956526630
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3441920653
Short name T416
Test name
Test status
Simulation time 107559898 ps
CPU time 5.46 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 02:31:19 PM PDT 24
Peak memory 240696 kb
Host smart-747b2900-9d9c-469d-a53b-9f73ba048826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34419
20653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3441920653
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.4165914756
Short name T569
Test name
Test status
Simulation time 147399987 ps
CPU time 13.25 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:31:30 PM PDT 24
Peak memory 249208 kb
Host smart-27f12a95-29b2-4d19-bffe-69d75487f2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41659
14756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.4165914756
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4049771532
Short name T202
Test name
Test status
Simulation time 215299569047 ps
CPU time 1491.43 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:56:07 PM PDT 24
Peak memory 265308 kb
Host smart-80fa3c46-e8e8-4590-8c4c-8172ca45d90a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049771532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4049771532
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2449026900
Short name T613
Test name
Test status
Simulation time 62499702463 ps
CPU time 1220.15 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 02:51:35 PM PDT 24
Peak memory 281624 kb
Host smart-5f5bcdce-d604-411f-8607-1189db1f090e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449026900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2449026900
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.39017078
Short name T604
Test name
Test status
Simulation time 7495140972 ps
CPU time 70.22 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 02:32:24 PM PDT 24
Peak memory 256028 kb
Host smart-b1fb258e-47d6-4bfb-8eb1-6b4cd1bd72a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39017
078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.39017078
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1993413062
Short name T46
Test name
Test status
Simulation time 1121502981 ps
CPU time 35.75 seconds
Started Mar 21 02:31:13 PM PDT 24
Finished Mar 21 02:31:49 PM PDT 24
Peak memory 255448 kb
Host smart-263940b2-c8b3-40ed-a85b-a885d3a27e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19934
13062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1993413062
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2422800245
Short name T547
Test name
Test status
Simulation time 52012302 ps
CPU time 4.42 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:31:20 PM PDT 24
Peak memory 240696 kb
Host smart-f102860a-0204-4896-b08b-d9130cca39e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228
00245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2422800245
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2820694650
Short name T609
Test name
Test status
Simulation time 439363518 ps
CPU time 13.09 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:31:30 PM PDT 24
Peak memory 248884 kb
Host smart-10f9e1c8-9b54-4d7f-bb33-b90332d376f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28206
94650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2820694650
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.597443212
Short name T28
Test name
Test status
Simulation time 46594940546 ps
CPU time 6033 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 04:11:51 PM PDT 24
Peak memory 354900 kb
Host smart-afa5e336-88ee-4077-b8a9-80d625797834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597443212 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.597443212
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4290226844
Short name T504
Test name
Test status
Simulation time 103595326986 ps
CPU time 1688.53 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:59:24 PM PDT 24
Peak memory 273524 kb
Host smart-d3d9f3a2-df1e-4bef-9d29-ac7ec063b193
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290226844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4290226844
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.137520852
Short name T497
Test name
Test status
Simulation time 11796832442 ps
CPU time 101.39 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 02:32:56 PM PDT 24
Peak memory 257092 kb
Host smart-318a0ed5-f8d4-4216-bc2d-6dd7c2637a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
0852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.137520852
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2980500696
Short name T73
Test name
Test status
Simulation time 1609983731 ps
CPU time 27.96 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:31:43 PM PDT 24
Peak memory 255968 kb
Host smart-24ec2054-af51-4642-b8b8-88c7d2565ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29805
00696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2980500696
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2032164831
Short name T338
Test name
Test status
Simulation time 89589560292 ps
CPU time 1226.33 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:51:43 PM PDT 24
Peak memory 265328 kb
Host smart-14fff333-b27f-4da1-af83-ca53d71c56e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032164831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2032164831
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2116771246
Short name T507
Test name
Test status
Simulation time 19132930543 ps
CPU time 1191.74 seconds
Started Mar 21 02:31:12 PM PDT 24
Finished Mar 21 02:51:04 PM PDT 24
Peak memory 289472 kb
Host smart-c6645ce6-b9f4-4c86-b184-297d7e4dce8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116771246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2116771246
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3792250741
Short name T680
Test name
Test status
Simulation time 25631765862 ps
CPU time 552.61 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:40:28 PM PDT 24
Peak memory 248152 kb
Host smart-fa9d302c-0563-46b2-b51d-c3f1887095d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792250741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3792250741
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2459940377
Short name T438
Test name
Test status
Simulation time 78537587 ps
CPU time 6.98 seconds
Started Mar 21 02:31:14 PM PDT 24
Finished Mar 21 02:31:21 PM PDT 24
Peak memory 252980 kb
Host smart-c3eb949f-fc68-4ac3-9d80-bcb64c7ebd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24599
40377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2459940377
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2071388710
Short name T510
Test name
Test status
Simulation time 600571990 ps
CPU time 43.09 seconds
Started Mar 21 02:31:13 PM PDT 24
Finished Mar 21 02:31:56 PM PDT 24
Peak memory 255188 kb
Host smart-75a6a447-def7-4803-a3b3-d830b745c5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20713
88710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2071388710
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2643971745
Short name T515
Test name
Test status
Simulation time 1094259985 ps
CPU time 31.88 seconds
Started Mar 21 02:31:18 PM PDT 24
Finished Mar 21 02:31:50 PM PDT 24
Peak memory 255916 kb
Host smart-5c788c24-73d9-406f-9d53-e1890dda5356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26439
71745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2643971745
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1336437551
Short name T359
Test name
Test status
Simulation time 290637844 ps
CPU time 28.82 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:31:45 PM PDT 24
Peak memory 255592 kb
Host smart-dd8f98b7-618a-4c68-a14f-38a4b3d4f84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13364
37551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1336437551
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3995289854
Short name T194
Test name
Test status
Simulation time 6208170937 ps
CPU time 541.17 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:40:17 PM PDT 24
Peak memory 265344 kb
Host smart-690137f1-d394-4473-ad59-ae2c8287f2c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995289854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3995289854
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3859991379
Short name T640
Test name
Test status
Simulation time 25324944510 ps
CPU time 1545.58 seconds
Started Mar 21 02:31:27 PM PDT 24
Finished Mar 21 02:57:13 PM PDT 24
Peak memory 273260 kb
Host smart-8e905704-c9b2-42de-af1b-07f182bb8fc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859991379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3859991379
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3980440018
Short name T457
Test name
Test status
Simulation time 2915006083 ps
CPU time 57.86 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:32:14 PM PDT 24
Peak memory 256536 kb
Host smart-6ea9119b-af77-455c-bc9f-0b00d1dc9bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804
40018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3980440018
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3334531861
Short name T691
Test name
Test status
Simulation time 337492687 ps
CPU time 21.03 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:31:38 PM PDT 24
Peak memory 255608 kb
Host smart-39ce5511-fd00-4312-9ea4-dba84a772957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33345
31861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3334531861
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.466796070
Short name T291
Test name
Test status
Simulation time 12788810616 ps
CPU time 1316.62 seconds
Started Mar 21 02:31:28 PM PDT 24
Finished Mar 21 02:53:25 PM PDT 24
Peak memory 273492 kb
Host smart-52b3d880-f10a-4f45-b3da-fbbe545b08ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466796070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.466796070
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4010178436
Short name T206
Test name
Test status
Simulation time 210833656368 ps
CPU time 3209.8 seconds
Started Mar 21 02:31:32 PM PDT 24
Finished Mar 21 03:25:02 PM PDT 24
Peak memory 289420 kb
Host smart-eb97c5ad-fd63-412e-b8e0-7472609c5f41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010178436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4010178436
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2630593705
Short name T308
Test name
Test status
Simulation time 16832659283 ps
CPU time 315.58 seconds
Started Mar 21 02:31:29 PM PDT 24
Finished Mar 21 02:36:45 PM PDT 24
Peak memory 248044 kb
Host smart-370f4d6b-45c2-49aa-923d-00a9a895fa81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630593705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2630593705
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1750814106
Short name T358
Test name
Test status
Simulation time 1039188839 ps
CPU time 54.15 seconds
Started Mar 21 02:31:15 PM PDT 24
Finished Mar 21 02:32:09 PM PDT 24
Peak memory 256820 kb
Host smart-065c3ae6-4c00-44af-b5b3-3af6dbac0be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
14106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1750814106
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2353195661
Short name T660
Test name
Test status
Simulation time 138497110 ps
CPU time 17.49 seconds
Started Mar 21 02:31:16 PM PDT 24
Finished Mar 21 02:31:34 PM PDT 24
Peak memory 247588 kb
Host smart-4b781df9-747e-44d2-bde1-05b45f626347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
95661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2353195661
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1970700838
Short name T653
Test name
Test status
Simulation time 63706314 ps
CPU time 5.11 seconds
Started Mar 21 02:31:30 PM PDT 24
Finished Mar 21 02:31:35 PM PDT 24
Peak memory 239252 kb
Host smart-6aa8cdc1-5b9c-46b6-9623-383032dd7197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19707
00838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1970700838
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3473967130
Short name T376
Test name
Test status
Simulation time 87218296 ps
CPU time 3.58 seconds
Started Mar 21 02:31:17 PM PDT 24
Finished Mar 21 02:31:21 PM PDT 24
Peak memory 240684 kb
Host smart-b5ae266e-6d76-4ece-a833-b4cc9bb2d78c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34739
67130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3473967130
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1797901121
Short name T658
Test name
Test status
Simulation time 30770192961 ps
CPU time 1295.68 seconds
Started Mar 21 02:31:32 PM PDT 24
Finished Mar 21 02:53:08 PM PDT 24
Peak memory 286480 kb
Host smart-5a469b78-d824-417e-8f92-c70ba3eb768e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797901121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1797901121
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1108548725
Short name T393
Test name
Test status
Simulation time 900790543 ps
CPU time 52.99 seconds
Started Mar 21 02:31:30 PM PDT 24
Finished Mar 21 02:32:23 PM PDT 24
Peak memory 248740 kb
Host smart-ff6e0428-b002-4507-9f33-a760b4aacf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11085
48725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1108548725
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.965667825
Short name T570
Test name
Test status
Simulation time 496838515 ps
CPU time 10.68 seconds
Started Mar 21 02:31:27 PM PDT 24
Finished Mar 21 02:31:38 PM PDT 24
Peak memory 252000 kb
Host smart-6bdf132a-77cc-4501-aa77-560eaa493c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96566
7825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.965667825
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.216220355
Short name T328
Test name
Test status
Simulation time 87629328650 ps
CPU time 778.45 seconds
Started Mar 21 02:31:32 PM PDT 24
Finished Mar 21 02:44:31 PM PDT 24
Peak memory 268716 kb
Host smart-bab18633-9368-418c-93bb-36de6d717b31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216220355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.216220355
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.164064688
Short name T424
Test name
Test status
Simulation time 5956231165 ps
CPU time 749.02 seconds
Started Mar 21 02:31:28 PM PDT 24
Finished Mar 21 02:43:58 PM PDT 24
Peak memory 273052 kb
Host smart-b07ca92c-0c45-473e-ba94-4f318991bc4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164064688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.164064688
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2988790346
Short name T587
Test name
Test status
Simulation time 16216609749 ps
CPU time 341.2 seconds
Started Mar 21 02:31:33 PM PDT 24
Finished Mar 21 02:37:14 PM PDT 24
Peak memory 248536 kb
Host smart-9bf420fd-3dce-4b4f-a4be-78f4af906c5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988790346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2988790346
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3972139334
Short name T357
Test name
Test status
Simulation time 553697835 ps
CPU time 33.95 seconds
Started Mar 21 02:31:27 PM PDT 24
Finished Mar 21 02:32:01 PM PDT 24
Peak memory 256068 kb
Host smart-ee6bf73b-e7fb-4928-a5c6-473924a93c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39721
39334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3972139334
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1133851596
Short name T229
Test name
Test status
Simulation time 574373308 ps
CPU time 22.84 seconds
Started Mar 21 02:31:29 PM PDT 24
Finished Mar 21 02:31:52 PM PDT 24
Peak memory 256108 kb
Host smart-bc79ee65-745a-4b44-88a2-8fa36e6a9e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11338
51596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1133851596
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.678184521
Short name T530
Test name
Test status
Simulation time 977664710 ps
CPU time 36.14 seconds
Started Mar 21 02:31:28 PM PDT 24
Finished Mar 21 02:32:05 PM PDT 24
Peak memory 247612 kb
Host smart-0d07427f-142b-4439-80a6-9e8e33cb710b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67818
4521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.678184521
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3663424922
Short name T490
Test name
Test status
Simulation time 3363376936 ps
CPU time 51.3 seconds
Started Mar 21 02:31:29 PM PDT 24
Finished Mar 21 02:32:21 PM PDT 24
Peak memory 248932 kb
Host smart-f4153652-7303-4105-be01-512b86b18721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
24922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3663424922
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2189154545
Short name T467
Test name
Test status
Simulation time 13860047320 ps
CPU time 378.9 seconds
Started Mar 21 02:31:28 PM PDT 24
Finished Mar 21 02:37:47 PM PDT 24
Peak memory 256852 kb
Host smart-8869e94d-946e-418c-82c8-dbc35acfd525
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189154545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2189154545
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.264292289
Short name T184
Test name
Test status
Simulation time 13608585301 ps
CPU time 850.11 seconds
Started Mar 21 02:31:28 PM PDT 24
Finished Mar 21 02:45:39 PM PDT 24
Peak memory 268408 kb
Host smart-169436dc-8add-4607-bbc4-0717bc625a4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264292289 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.264292289
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4025705984
Short name T93
Test name
Test status
Simulation time 410270483281 ps
CPU time 3021.03 seconds
Started Mar 21 02:31:45 PM PDT 24
Finished Mar 21 03:22:06 PM PDT 24
Peak memory 286012 kb
Host smart-8623c6fe-afdf-4806-aa35-965596bae621
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025705984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4025705984
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2916028247
Short name T454
Test name
Test status
Simulation time 1039286468 ps
CPU time 101.08 seconds
Started Mar 21 02:31:40 PM PDT 24
Finished Mar 21 02:33:21 PM PDT 24
Peak memory 256712 kb
Host smart-a7369d23-5b99-41e6-8a2b-360563acb0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
28247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2916028247
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3892884671
Short name T600
Test name
Test status
Simulation time 7023260357 ps
CPU time 57.38 seconds
Started Mar 21 02:31:30 PM PDT 24
Finished Mar 21 02:32:28 PM PDT 24
Peak memory 256904 kb
Host smart-6dc8213d-850e-40f6-a2a8-05478256b3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38928
84671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3892884671
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.964943542
Short name T322
Test name
Test status
Simulation time 60464917294 ps
CPU time 3570.55 seconds
Started Mar 21 02:31:41 PM PDT 24
Finished Mar 21 03:31:12 PM PDT 24
Peak memory 289428 kb
Host smart-76b39a04-dacd-4f76-aaa0-0f4284a6e167
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964943542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.964943542
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2410256736
Short name T489
Test name
Test status
Simulation time 128309901986 ps
CPU time 2372.11 seconds
Started Mar 21 02:31:41 PM PDT 24
Finished Mar 21 03:11:14 PM PDT 24
Peak memory 281788 kb
Host smart-026e2443-e474-4aa5-8478-b0b7a921dcfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410256736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2410256736
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3152122676
Short name T42
Test name
Test status
Simulation time 2809511934 ps
CPU time 43.42 seconds
Started Mar 21 02:31:33 PM PDT 24
Finished Mar 21 02:32:16 PM PDT 24
Peak memory 257324 kb
Host smart-6cad7ab9-a505-4f7b-aa2d-1cc7cfe47ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
22676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3152122676
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.637996695
Short name T80
Test name
Test status
Simulation time 1170001783 ps
CPU time 44.53 seconds
Started Mar 21 02:31:29 PM PDT 24
Finished Mar 21 02:32:14 PM PDT 24
Peak memory 247652 kb
Host smart-49b63291-d128-455a-a698-20bdee40c73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63799
6695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.637996695
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.464213388
Short name T701
Test name
Test status
Simulation time 979772020 ps
CPU time 38.71 seconds
Started Mar 21 02:31:40 PM PDT 24
Finished Mar 21 02:32:19 PM PDT 24
Peak memory 256084 kb
Host smart-428c4391-a1da-4f3f-80f5-c4078b62a1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46421
3388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.464213388
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2015448489
Short name T242
Test name
Test status
Simulation time 180819869 ps
CPU time 13.15 seconds
Started Mar 21 02:31:33 PM PDT 24
Finished Mar 21 02:31:46 PM PDT 24
Peak memory 254524 kb
Host smart-86005ec1-9a53-4eff-869d-19a953bc244d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20154
48489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2015448489
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3639865411
Short name T85
Test name
Test status
Simulation time 158965681891 ps
CPU time 2398.63 seconds
Started Mar 21 02:31:40 PM PDT 24
Finished Mar 21 03:11:39 PM PDT 24
Peak memory 281704 kb
Host smart-f33012a6-a906-4353-b476-f502a59656d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639865411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3639865411
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1873140424
Short name T447
Test name
Test status
Simulation time 16145127995 ps
CPU time 1506.42 seconds
Started Mar 21 02:31:40 PM PDT 24
Finished Mar 21 02:56:47 PM PDT 24
Peak memory 289944 kb
Host smart-f26fab99-e88c-4578-923a-ce7a94e162fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873140424 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1873140424
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3373082899
Short name T595
Test name
Test status
Simulation time 26801742860 ps
CPU time 1707.25 seconds
Started Mar 21 02:31:56 PM PDT 24
Finished Mar 21 03:00:24 PM PDT 24
Peak memory 273160 kb
Host smart-ec27a598-c14f-4a8b-aad2-864befdb1d43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373082899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3373082899
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1858608746
Short name T610
Test name
Test status
Simulation time 19118968 ps
CPU time 2.99 seconds
Started Mar 21 02:31:41 PM PDT 24
Finished Mar 21 02:31:44 PM PDT 24
Peak memory 239152 kb
Host smart-e0558e49-b56e-435d-a84e-b119e4d4d25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18586
08746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1858608746
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1783986401
Short name T459
Test name
Test status
Simulation time 143173504 ps
CPU time 12.2 seconds
Started Mar 21 02:31:47 PM PDT 24
Finished Mar 21 02:31:59 PM PDT 24
Peak memory 253060 kb
Host smart-5bae97c4-0691-42c3-9524-352b1f7fd83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17839
86401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1783986401
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1072955035
Short name T292
Test name
Test status
Simulation time 35011855243 ps
CPU time 1604.77 seconds
Started Mar 21 02:31:58 PM PDT 24
Finished Mar 21 02:58:43 PM PDT 24
Peak memory 289068 kb
Host smart-70786211-a07d-4f12-b764-31bf83e1c979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072955035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1072955035
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3229730260
Short name T668
Test name
Test status
Simulation time 79077329273 ps
CPU time 1369.67 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 02:54:44 PM PDT 24
Peak memory 289144 kb
Host smart-0d0d0b4c-0752-4062-b5a5-b148c3195eb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229730260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3229730260
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2250302539
Short name T299
Test name
Test status
Simulation time 11530974395 ps
CPU time 484.08 seconds
Started Mar 21 02:31:53 PM PDT 24
Finished Mar 21 02:39:58 PM PDT 24
Peak memory 247960 kb
Host smart-0fbc9c8f-343b-4326-9c5b-3b91ecdf7e99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250302539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2250302539
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3392209717
Short name T475
Test name
Test status
Simulation time 2024643761 ps
CPU time 35.56 seconds
Started Mar 21 02:31:45 PM PDT 24
Finished Mar 21 02:32:20 PM PDT 24
Peak memory 256492 kb
Host smart-9cc69e5f-9f21-4cb0-a83b-fad76c9ea0eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33922
09717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3392209717
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1795581683
Short name T47
Test name
Test status
Simulation time 702061143 ps
CPU time 47.02 seconds
Started Mar 21 02:31:48 PM PDT 24
Finished Mar 21 02:32:35 PM PDT 24
Peak memory 248656 kb
Host smart-cc89b263-c24d-4f38-a0cd-44f1160a83d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17955
81683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1795581683
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2054403712
Short name T563
Test name
Test status
Simulation time 62889014 ps
CPU time 3.35 seconds
Started Mar 21 02:31:53 PM PDT 24
Finished Mar 21 02:31:57 PM PDT 24
Peak memory 239216 kb
Host smart-d541c1c0-b4f1-4dda-b7f1-e7ec7fa18305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20544
03712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2054403712
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.37850295
Short name T230
Test name
Test status
Simulation time 260677450 ps
CPU time 19 seconds
Started Mar 21 02:31:42 PM PDT 24
Finished Mar 21 02:32:01 PM PDT 24
Peak memory 254684 kb
Host smart-06ba45dd-3e9f-4faa-a0bc-88a276016945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37850
295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.37850295
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1576755167
Short name T264
Test name
Test status
Simulation time 38534933906 ps
CPU time 1931.54 seconds
Started Mar 21 02:31:56 PM PDT 24
Finished Mar 21 03:04:08 PM PDT 24
Peak memory 289544 kb
Host smart-eb507303-4087-4068-a756-3e49480297a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576755167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1576755167
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3059204705
Short name T207
Test name
Test status
Simulation time 49402819218 ps
CPU time 2992.05 seconds
Started Mar 21 02:31:56 PM PDT 24
Finished Mar 21 03:21:48 PM PDT 24
Peak memory 281696 kb
Host smart-ed1fae3d-7c5a-4d2c-8858-74d5bcfcb075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059204705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3059204705
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1474449847
Short name T678
Test name
Test status
Simulation time 2849420821 ps
CPU time 38.85 seconds
Started Mar 21 02:31:56 PM PDT 24
Finished Mar 21 02:32:35 PM PDT 24
Peak memory 256192 kb
Host smart-2e05b23e-72e2-4830-a36e-67dd65a94834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14744
49847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1474449847
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4272233699
Short name T479
Test name
Test status
Simulation time 3368636269 ps
CPU time 38.22 seconds
Started Mar 21 02:31:53 PM PDT 24
Finished Mar 21 02:32:32 PM PDT 24
Peak memory 248924 kb
Host smart-11e8f269-bae9-4442-978e-23110213060f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42722
33699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4272233699
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.39209493
Short name T669
Test name
Test status
Simulation time 29253822268 ps
CPU time 1367.41 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 02:54:42 PM PDT 24
Peak memory 285660 kb
Host smart-38a13ff6-2aa4-4d87-8070-31c440a0a1dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39209493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.39209493
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.439838878
Short name T401
Test name
Test status
Simulation time 126909578513 ps
CPU time 1887.55 seconds
Started Mar 21 02:31:56 PM PDT 24
Finished Mar 21 03:03:24 PM PDT 24
Peak memory 270708 kb
Host smart-a69d9ed0-61fc-4e95-8fa9-c76cde1f409d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439838878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.439838878
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.4172700974
Short name T559
Test name
Test status
Simulation time 32358045874 ps
CPU time 385.57 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 02:38:19 PM PDT 24
Peak memory 256336 kb
Host smart-345ffd00-ff7f-4914-851a-8f68f4abed73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172700974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.4172700974
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3926929695
Short name T645
Test name
Test status
Simulation time 1854778079 ps
CPU time 60.48 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 02:32:55 PM PDT 24
Peak memory 255924 kb
Host smart-62725418-ea33-4554-ba19-1b2a7ed94e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39269
29695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3926929695
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.938890254
Short name T440
Test name
Test status
Simulation time 2563185768 ps
CPU time 36.65 seconds
Started Mar 21 02:31:55 PM PDT 24
Finished Mar 21 02:32:31 PM PDT 24
Peak memory 255480 kb
Host smart-8d59db90-4a55-4c23-a636-e0fc92ee4e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93889
0254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.938890254
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4117444839
Short name T197
Test name
Test status
Simulation time 696356687 ps
CPU time 38.82 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 02:32:33 PM PDT 24
Peak memory 248856 kb
Host smart-c5dd6ce1-8a51-4083-9288-e044669866d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41174
44839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4117444839
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2094600165
Short name T599
Test name
Test status
Simulation time 1292688814 ps
CPU time 26.99 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 02:32:22 PM PDT 24
Peak memory 248860 kb
Host smart-10ea6b75-7dc5-4503-b143-742ff75910b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
00165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2094600165
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3264864786
Short name T580
Test name
Test status
Simulation time 3248536966 ps
CPU time 51.11 seconds
Started Mar 21 02:31:55 PM PDT 24
Finished Mar 21 02:32:46 PM PDT 24
Peak memory 255316 kb
Host smart-4bd13336-f4ec-477e-a756-d766492f6e72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264864786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3264864786
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3007039461
Short name T508
Test name
Test status
Simulation time 75100539862 ps
CPU time 3393.79 seconds
Started Mar 21 02:31:54 PM PDT 24
Finished Mar 21 03:28:28 PM PDT 24
Peak memory 289984 kb
Host smart-f4bca88f-5375-4078-baa5-cc806c6966e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007039461 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3007039461
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3288757910
Short name T366
Test name
Test status
Simulation time 10369558095 ps
CPU time 970.65 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:48:23 PM PDT 24
Peak memory 273508 kb
Host smart-22843619-530c-48bb-a78a-c382b9e3f0de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288757910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3288757910
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1595979619
Short name T506
Test name
Test status
Simulation time 3194858573 ps
CPU time 200.26 seconds
Started Mar 21 02:32:17 PM PDT 24
Finished Mar 21 02:35:37 PM PDT 24
Peak memory 256988 kb
Host smart-f71ba094-ce00-4923-9a88-71ac7df0a4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15959
79619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1595979619
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2185878030
Short name T255
Test name
Test status
Simulation time 140979286 ps
CPU time 10.71 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:32:23 PM PDT 24
Peak memory 251012 kb
Host smart-1f837b53-1a50-4ca0-b026-e7da23002a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21858
78030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2185878030
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2934810861
Short name T335
Test name
Test status
Simulation time 581423222483 ps
CPU time 2563.84 seconds
Started Mar 21 02:32:13 PM PDT 24
Finished Mar 21 03:14:57 PM PDT 24
Peak memory 284896 kb
Host smart-f154b1b4-378c-4a3a-808d-efdda07c9a6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934810861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2934810861
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.943530
Short name T305
Test name
Test status
Simulation time 12178361230 ps
CPU time 518.16 seconds
Started Mar 21 02:32:14 PM PDT 24
Finished Mar 21 02:40:52 PM PDT 24
Peak memory 248180 kb
Host smart-cb825cfe-e5da-45be-b022-395427eeb27b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.943530
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3373993549
Short name T576
Test name
Test status
Simulation time 905999412 ps
CPU time 13.27 seconds
Started Mar 21 02:32:13 PM PDT 24
Finished Mar 21 02:32:26 PM PDT 24
Peak memory 248916 kb
Host smart-7dd0dffc-15db-473c-9cd6-fce4eb10baf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33739
93549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3373993549
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2233211040
Short name T460
Test name
Test status
Simulation time 682504840 ps
CPU time 19.37 seconds
Started Mar 21 02:32:17 PM PDT 24
Finished Mar 21 02:32:36 PM PDT 24
Peak memory 248896 kb
Host smart-fadee9b5-1f52-4b41-a45c-c0df12b045e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
11040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2233211040
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2600383928
Short name T276
Test name
Test status
Simulation time 1004182456 ps
CPU time 63.56 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:33:16 PM PDT 24
Peak memory 248832 kb
Host smart-2ba28d70-a170-4265-8053-8575249155ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003
83928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2600383928
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1396956535
Short name T367
Test name
Test status
Simulation time 146156627 ps
CPU time 17.34 seconds
Started Mar 21 02:32:12 PM PDT 24
Finished Mar 21 02:32:29 PM PDT 24
Peak memory 248880 kb
Host smart-49e40802-3989-44ea-b40f-048e0541dbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13969
56535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1396956535
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2999058644
Short name T589
Test name
Test status
Simulation time 30066649065 ps
CPU time 1992.64 seconds
Started Mar 21 02:32:13 PM PDT 24
Finished Mar 21 03:05:26 PM PDT 24
Peak memory 287088 kb
Host smart-e2efd4fa-6a3c-4bea-86dc-f163bea9f268
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999058644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2999058644
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.403280827
Short name T568
Test name
Test status
Simulation time 148879010816 ps
CPU time 2777.26 seconds
Started Mar 21 02:32:20 PM PDT 24
Finished Mar 21 03:18:38 PM PDT 24
Peak memory 289196 kb
Host smart-eea2ee47-e417-463b-8bf6-7bcb5edecbf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403280827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.403280827
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3628482634
Short name T450
Test name
Test status
Simulation time 3229637137 ps
CPU time 88.53 seconds
Started Mar 21 02:32:13 PM PDT 24
Finished Mar 21 02:33:42 PM PDT 24
Peak memory 256560 kb
Host smart-d48b0814-141f-485a-afac-c693a3928170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36284
82634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3628482634
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3165152046
Short name T674
Test name
Test status
Simulation time 813630471 ps
CPU time 63.02 seconds
Started Mar 21 02:32:14 PM PDT 24
Finished Mar 21 02:33:17 PM PDT 24
Peak memory 254972 kb
Host smart-62d565b7-cf4a-43ac-9f32-f48049654995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31651
52046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3165152046
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2402925423
Short name T327
Test name
Test status
Simulation time 20134054978 ps
CPU time 1457.28 seconds
Started Mar 21 02:32:11 PM PDT 24
Finished Mar 21 02:56:29 PM PDT 24
Peak memory 285684 kb
Host smart-8020e3e7-9006-43de-9fd0-8ce3b8e33234
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402925423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2402925423
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1211960480
Short name T90
Test name
Test status
Simulation time 78193554509 ps
CPU time 2621.54 seconds
Started Mar 21 02:32:14 PM PDT 24
Finished Mar 21 03:15:56 PM PDT 24
Peak memory 288656 kb
Host smart-bc65fa0f-d7fe-45bb-b2d8-b8a5aba15b73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211960480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1211960480
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.634007768
Short name T317
Test name
Test status
Simulation time 9658633125 ps
CPU time 385.33 seconds
Started Mar 21 02:32:11 PM PDT 24
Finished Mar 21 02:38:37 PM PDT 24
Peak memory 247996 kb
Host smart-a48d0331-1de5-4cf6-8f16-367e872c9c86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634007768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.634007768
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1866797235
Short name T419
Test name
Test status
Simulation time 115036169 ps
CPU time 8.68 seconds
Started Mar 21 02:32:13 PM PDT 24
Finished Mar 21 02:32:22 PM PDT 24
Peak memory 248860 kb
Host smart-b77db978-f570-464d-84ed-7ac5682c0623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
97235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1866797235
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.79123645
Short name T108
Test name
Test status
Simulation time 3260415580 ps
CPU time 50.67 seconds
Started Mar 21 02:32:13 PM PDT 24
Finished Mar 21 02:33:04 PM PDT 24
Peak memory 254936 kb
Host smart-cd0740ea-e5c6-4546-a568-c5e8b1c37011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79123
645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.79123645
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4189533058
Short name T87
Test name
Test status
Simulation time 133678076 ps
CPU time 10.55 seconds
Started Mar 21 02:32:17 PM PDT 24
Finished Mar 21 02:32:27 PM PDT 24
Peak memory 247428 kb
Host smart-141ecedf-56af-4964-a572-b25c6ecdf910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41895
33058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4189533058
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1667830250
Short name T433
Test name
Test status
Simulation time 4453444428 ps
CPU time 37.39 seconds
Started Mar 21 02:32:11 PM PDT 24
Finished Mar 21 02:32:48 PM PDT 24
Peak memory 248944 kb
Host smart-2a38f3e6-d888-4c14-84ad-c6a4afb5bcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16678
30250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1667830250
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.982507750
Short name T25
Test name
Test status
Simulation time 59174353416 ps
CPU time 2055.37 seconds
Started Mar 21 02:32:14 PM PDT 24
Finished Mar 21 03:06:30 PM PDT 24
Peak memory 281764 kb
Host smart-6b0a0c63-735b-4653-b883-4d253418088e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982507750 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.982507750
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2554198433
Short name T224
Test name
Test status
Simulation time 41848820 ps
CPU time 2.61 seconds
Started Mar 21 02:27:55 PM PDT 24
Finished Mar 21 02:27:58 PM PDT 24
Peak memory 249036 kb
Host smart-e6f4f7de-5852-496e-aaab-9de1fc307000
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2554198433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2554198433
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1384381983
Short name T565
Test name
Test status
Simulation time 182083928409 ps
CPU time 2546.1 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 03:10:17 PM PDT 24
Peak memory 288764 kb
Host smart-873ad3b0-e742-45b4-bc9a-32c489cbc731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384381983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1384381983
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2246783099
Short name T241
Test name
Test status
Simulation time 500173150 ps
CPU time 8.82 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:27:59 PM PDT 24
Peak memory 240644 kb
Host smart-bafb203c-d029-43ed-9844-3efe63ade00f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2246783099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2246783099
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2231192338
Short name T397
Test name
Test status
Simulation time 2016836880 ps
CPU time 45.45 seconds
Started Mar 21 02:27:54 PM PDT 24
Finished Mar 21 02:28:41 PM PDT 24
Peak memory 248616 kb
Host smart-651a3f59-2814-4f61-80a8-f9667506ef02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22311
92338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2231192338
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3913986477
Short name T646
Test name
Test status
Simulation time 1148466261 ps
CPU time 23.63 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:28:14 PM PDT 24
Peak memory 255332 kb
Host smart-cf6773d9-68d3-4810-8cbd-e6f869c6c2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39139
86477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3913986477
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1290329030
Short name T176
Test name
Test status
Simulation time 53240784878 ps
CPU time 3035.89 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 03:18:28 PM PDT 24
Peak memory 288284 kb
Host smart-64f57f6c-3345-48d7-a51d-094b60ea8d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290329030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1290329030
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3650103422
Short name T237
Test name
Test status
Simulation time 32844680492 ps
CPU time 2200.02 seconds
Started Mar 21 02:27:53 PM PDT 24
Finished Mar 21 03:04:34 PM PDT 24
Peak memory 283644 kb
Host smart-445f4ea7-8d03-4333-929b-8a6a4808bddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650103422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3650103422
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1458419040
Short name T321
Test name
Test status
Simulation time 40417907659 ps
CPU time 445.18 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:35:17 PM PDT 24
Peak memory 248096 kb
Host smart-0506455f-86f1-4219-858c-65fddc284638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458419040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1458419040
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1356271129
Short name T452
Test name
Test status
Simulation time 149975853 ps
CPU time 4.8 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 02:27:56 PM PDT 24
Peak memory 251088 kb
Host smart-11bc594d-071e-41ed-8f58-22f266c1dbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13562
71129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1356271129
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1018178167
Short name T557
Test name
Test status
Simulation time 1492414783 ps
CPU time 47.47 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 02:28:38 PM PDT 24
Peak memory 255708 kb
Host smart-608e0c2c-ca8b-43d7-92cc-f1b58fbcdf4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10181
78167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1018178167
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2957330294
Short name T673
Test name
Test status
Simulation time 592466853 ps
CPU time 16.34 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:28:07 PM PDT 24
Peak memory 255936 kb
Host smart-17f76006-9848-405a-9909-e3d168d3bbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29573
30294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2957330294
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2477608642
Short name T603
Test name
Test status
Simulation time 1027657478 ps
CPU time 14.29 seconds
Started Mar 21 02:28:01 PM PDT 24
Finished Mar 21 02:28:15 PM PDT 24
Peak memory 248852 kb
Host smart-97c2d360-2148-48e1-a9bb-31c1f2cadd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24776
08642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2477608642
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2292316232
Short name T531
Test name
Test status
Simulation time 1316557182 ps
CPU time 79.5 seconds
Started Mar 21 02:27:51 PM PDT 24
Finished Mar 21 02:29:11 PM PDT 24
Peak memory 256228 kb
Host smart-b4b9d82f-ca8d-4493-8fcc-a9fd7e665523
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292316232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2292316232
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2270499435
Short name T258
Test name
Test status
Simulation time 53218492926 ps
CPU time 5432.3 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 03:58:24 PM PDT 24
Peak memory 330892 kb
Host smart-f4cc104d-3eb7-4e1b-a8c7-5d92a33423fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270499435 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2270499435
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2238770796
Short name T191
Test name
Test status
Simulation time 57886053 ps
CPU time 3.35 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:28:12 PM PDT 24
Peak memory 249076 kb
Host smart-683565d7-e4c1-4cc9-9862-0daad0df9c49
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2238770796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2238770796
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1907713167
Short name T472
Test name
Test status
Simulation time 3186283163 ps
CPU time 48.96 seconds
Started Mar 21 02:28:06 PM PDT 24
Finished Mar 21 02:28:55 PM PDT 24
Peak memory 240712 kb
Host smart-fce7b696-7342-4803-b279-dd079af04078
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1907713167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1907713167
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.761338343
Short name T471
Test name
Test status
Simulation time 110462804969 ps
CPU time 339.58 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:33:29 PM PDT 24
Peak memory 257116 kb
Host smart-98b8ec8a-5edf-4460-8779-1efe65762fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76133
8343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.761338343
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1691553524
Short name T40
Test name
Test status
Simulation time 2784813259 ps
CPU time 72.67 seconds
Started Mar 21 02:27:54 PM PDT 24
Finished Mar 21 02:29:07 PM PDT 24
Peak memory 255604 kb
Host smart-8d742c61-65ba-4d7b-ae8b-dc35bd8655e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16915
53524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1691553524
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.4050350300
Short name T655
Test name
Test status
Simulation time 19393536783 ps
CPU time 1110.35 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:46:39 PM PDT 24
Peak memory 265368 kb
Host smart-8df47f54-29b4-427e-9382-0c241d3607c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050350300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4050350300
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2229577545
Short name T105
Test name
Test status
Simulation time 118058551403 ps
CPU time 1771.4 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:57:39 PM PDT 24
Peak memory 273504 kb
Host smart-ac6915fc-f98f-4a2d-9d0b-663f3a790e6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229577545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2229577545
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3277191331
Short name T319
Test name
Test status
Simulation time 16429127210 ps
CPU time 180.07 seconds
Started Mar 21 02:28:06 PM PDT 24
Finished Mar 21 02:31:07 PM PDT 24
Peak memory 248148 kb
Host smart-bec57560-0ca4-47d1-92ea-17208612e61c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277191331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3277191331
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.790781175
Short name T360
Test name
Test status
Simulation time 2470984104 ps
CPU time 31.7 seconds
Started Mar 21 02:27:49 PM PDT 24
Finished Mar 21 02:28:21 PM PDT 24
Peak memory 249096 kb
Host smart-6fbefab9-4a8d-4b34-9fd5-e2c48680ff29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79078
1175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.790781175
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1465825449
Short name T21
Test name
Test status
Simulation time 1120465626 ps
CPU time 18.79 seconds
Started Mar 21 02:27:53 PM PDT 24
Finished Mar 21 02:28:12 PM PDT 24
Peak memory 254824 kb
Host smart-4e4493bf-684b-47e5-b5de-4edef2fd58b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14658
25449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1465825449
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3157377585
Short name T488
Test name
Test status
Simulation time 2802643650 ps
CPU time 50.22 seconds
Started Mar 21 02:28:09 PM PDT 24
Finished Mar 21 02:28:59 PM PDT 24
Peak memory 248944 kb
Host smart-c03c49c9-22ac-481e-b548-9cf7e10b05ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31573
77585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3157377585
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1876773072
Short name T249
Test name
Test status
Simulation time 1417860077 ps
CPU time 14.81 seconds
Started Mar 21 02:27:50 PM PDT 24
Finished Mar 21 02:28:06 PM PDT 24
Peak memory 248476 kb
Host smart-451e230a-99a7-4c36-ae84-8df8052f3d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18767
73072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1876773072
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3601806357
Short name T445
Test name
Test status
Simulation time 58014591566 ps
CPU time 2032.92 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 03:02:00 PM PDT 24
Peak memory 281668 kb
Host smart-e5ba7ee5-8610-450a-8ac7-4bc9b15fa2f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601806357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3601806357
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.4166601253
Short name T211
Test name
Test status
Simulation time 44506701 ps
CPU time 3.72 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:28:11 PM PDT 24
Peak memory 249120 kb
Host smart-c890dc94-7aac-4470-b4f7-320fa2e08f2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4166601253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.4166601253
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4165237926
Short name T470
Test name
Test status
Simulation time 18960891700 ps
CPU time 1317.61 seconds
Started Mar 21 02:28:09 PM PDT 24
Finished Mar 21 02:50:07 PM PDT 24
Peak memory 272544 kb
Host smart-0983fc3c-1196-48c1-bcad-beb503f881b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165237926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4165237926
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1951530718
Short name T682
Test name
Test status
Simulation time 272303739 ps
CPU time 16.2 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:28:24 PM PDT 24
Peak memory 251640 kb
Host smart-f0c6e41c-1ea2-4c3c-81fe-30c9e079a248
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1951530718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1951530718
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3285788046
Short name T391
Test name
Test status
Simulation time 89474031 ps
CPU time 3.65 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:28:12 PM PDT 24
Peak memory 239188 kb
Host smart-bd918490-9bd5-40ee-892e-6bfc757157f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32857
88046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3285788046
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1561176446
Short name T656
Test name
Test status
Simulation time 404194231 ps
CPU time 34.01 seconds
Started Mar 21 02:28:10 PM PDT 24
Finished Mar 21 02:28:44 PM PDT 24
Peak memory 248816 kb
Host smart-4e8380c8-8701-42fd-95ca-e899656d6b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15611
76446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1561176446
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.417645022
Short name T231
Test name
Test status
Simulation time 29110401100 ps
CPU time 1728.08 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:56:55 PM PDT 24
Peak memory 265304 kb
Host smart-6414c7a5-cf6f-4667-9cfe-a2ceb39d2c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417645022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.417645022
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.355695346
Short name T70
Test name
Test status
Simulation time 123170541140 ps
CPU time 912.31 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:43:19 PM PDT 24
Peak memory 268508 kb
Host smart-f4955d86-fc5a-41d2-9da6-13aea2b8d1bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355695346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.355695346
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2463756166
Short name T306
Test name
Test status
Simulation time 15240035345 ps
CPU time 328.54 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:33:37 PM PDT 24
Peak memory 247876 kb
Host smart-5bffcd3e-8893-444c-ae33-a79dc5e6b4a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463756166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2463756166
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2751497628
Short name T704
Test name
Test status
Simulation time 1312112164 ps
CPU time 20.1 seconds
Started Mar 21 02:28:09 PM PDT 24
Finished Mar 21 02:28:29 PM PDT 24
Peak memory 257076 kb
Host smart-9c7e8725-0328-43d3-840c-d79c0928a8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
97628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2751497628
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4083781043
Short name T581
Test name
Test status
Simulation time 448843179 ps
CPU time 23.38 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:28:31 PM PDT 24
Peak memory 247292 kb
Host smart-a4c785d2-93fd-4d02-be47-c0a2e35798cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40837
81043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4083781043
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1773436037
Short name T554
Test name
Test status
Simulation time 96286567 ps
CPU time 12.54 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:28:20 PM PDT 24
Peak memory 247328 kb
Host smart-8bb9736d-8f2f-4181-969d-f51255b09f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
36037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1773436037
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1088269778
Short name T662
Test name
Test status
Simulation time 7341553790 ps
CPU time 54.14 seconds
Started Mar 21 02:28:12 PM PDT 24
Finished Mar 21 02:29:06 PM PDT 24
Peak memory 249000 kb
Host smart-c03e0d70-8f0a-4a86-88ba-2d0991d571f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10882
69778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1088269778
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2749599472
Short name T106
Test name
Test status
Simulation time 42789509161 ps
CPU time 769.98 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:40:58 PM PDT 24
Peak memory 265324 kb
Host smart-206298e5-019d-46e3-889f-7c9394a0f87b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749599472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2749599472
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1855722780
Short name T226
Test name
Test status
Simulation time 180533611 ps
CPU time 3.85 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:28:11 PM PDT 24
Peak memory 249068 kb
Host smart-4e340696-fce9-4683-9b91-a3ce388f61ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1855722780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1855722780
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.140802013
Short name T683
Test name
Test status
Simulation time 19006812773 ps
CPU time 1203.87 seconds
Started Mar 21 02:28:09 PM PDT 24
Finished Mar 21 02:48:13 PM PDT 24
Peak memory 273512 kb
Host smart-77cc7e84-5885-44a1-9f75-c4de3bd3aad8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140802013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.140802013
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2630159603
Short name T631
Test name
Test status
Simulation time 3820293670 ps
CPU time 37.5 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:28:46 PM PDT 24
Peak memory 240732 kb
Host smart-3454d7de-c576-405b-82b1-c428d8b3b7e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2630159603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2630159603
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.256645175
Short name T251
Test name
Test status
Simulation time 1235204515 ps
CPU time 97.71 seconds
Started Mar 21 02:28:09 PM PDT 24
Finished Mar 21 02:29:47 PM PDT 24
Peak memory 256672 kb
Host smart-b6c54813-6547-41f4-9c0e-7fe2187f758b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25664
5175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.256645175
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3976911467
Short name T394
Test name
Test status
Simulation time 1192785585 ps
CPU time 71.02 seconds
Started Mar 21 02:28:12 PM PDT 24
Finished Mar 21 02:29:23 PM PDT 24
Peak memory 254868 kb
Host smart-7373854d-b1e2-4051-9bc6-db82d819d0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39769
11467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3976911467
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3872011355
Short name T238
Test name
Test status
Simulation time 272434981309 ps
CPU time 2941.48 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 03:17:10 PM PDT 24
Peak memory 288992 kb
Host smart-239a2c7c-15ef-4222-8ea1-2c4725f86666
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872011355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3872011355
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2831098331
Short name T236
Test name
Test status
Simulation time 20932453680 ps
CPU time 1292.06 seconds
Started Mar 21 02:28:09 PM PDT 24
Finished Mar 21 02:49:42 PM PDT 24
Peak memory 272456 kb
Host smart-25023983-9143-49b8-9324-87c538785cb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831098331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2831098331
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3009424928
Short name T13
Test name
Test status
Simulation time 6242176636 ps
CPU time 114.81 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:30:02 PM PDT 24
Peak memory 247068 kb
Host smart-b7a1c521-6b7e-4105-a586-9ee7ad5a85f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009424928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3009424928
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1563185622
Short name T491
Test name
Test status
Simulation time 2771564438 ps
CPU time 46.08 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:28:54 PM PDT 24
Peak memory 248912 kb
Host smart-40d0a4a6-6733-4d30-8f05-9e72ded08920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15631
85622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1563185622
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2364259392
Short name T417
Test name
Test status
Simulation time 1160876741 ps
CPU time 39.1 seconds
Started Mar 21 02:28:07 PM PDT 24
Finished Mar 21 02:28:46 PM PDT 24
Peak memory 254800 kb
Host smart-106207ce-f3a0-4855-abf4-51e1fa0c4f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
59392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2364259392
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3431734512
Short name T84
Test name
Test status
Simulation time 320036851 ps
CPU time 26.02 seconds
Started Mar 21 02:28:02 PM PDT 24
Finished Mar 21 02:28:28 PM PDT 24
Peak memory 247376 kb
Host smart-0960d2cc-fabb-44d7-88f7-d8c4862c7671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34317
34512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3431734512
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2598354406
Short name T617
Test name
Test status
Simulation time 220644951 ps
CPU time 19.11 seconds
Started Mar 21 02:28:06 PM PDT 24
Finished Mar 21 02:28:26 PM PDT 24
Peak memory 248892 kb
Host smart-7d690fa6-eb1f-4712-ba25-843750c7bbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
54406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2598354406
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2626391826
Short name T44
Test name
Test status
Simulation time 4350048488 ps
CPU time 67.79 seconds
Started Mar 21 02:28:12 PM PDT 24
Finished Mar 21 02:29:20 PM PDT 24
Peak memory 255812 kb
Host smart-d654d348-9ac3-457a-a119-05eaa75868ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626391826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2626391826
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1365361338
Short name T213
Test name
Test status
Simulation time 20869322 ps
CPU time 3.29 seconds
Started Mar 21 02:28:21 PM PDT 24
Finished Mar 21 02:28:25 PM PDT 24
Peak memory 249088 kb
Host smart-58cc2afc-b002-4b84-9a63-637924492c2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1365361338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1365361338
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1059713824
Short name T618
Test name
Test status
Simulation time 33059832646 ps
CPU time 2157.36 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 03:04:17 PM PDT 24
Peak memory 281696 kb
Host smart-8f15070b-f1b2-4943-ae7c-5dd64aea043c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059713824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1059713824
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2650815204
Short name T501
Test name
Test status
Simulation time 2232931129 ps
CPU time 26.81 seconds
Started Mar 21 02:28:20 PM PDT 24
Finished Mar 21 02:28:47 PM PDT 24
Peak memory 248888 kb
Host smart-0df38d2b-48a9-4d67-9a0a-f48f0af2dbec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2650815204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2650815204
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3702498643
Short name T481
Test name
Test status
Simulation time 3891389083 ps
CPU time 238.78 seconds
Started Mar 21 02:28:17 PM PDT 24
Finished Mar 21 02:32:16 PM PDT 24
Peak memory 257096 kb
Host smart-2972149d-08db-4c9a-a663-e4003ceb7f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37024
98643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3702498643
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2430082612
Short name T72
Test name
Test status
Simulation time 888447970 ps
CPU time 57.87 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:29:18 PM PDT 24
Peak memory 255300 kb
Host smart-3e83facc-4811-4c2a-850c-9aedf7373ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24300
82612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2430082612
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2203026932
Short name T685
Test name
Test status
Simulation time 59744019852 ps
CPU time 1889.66 seconds
Started Mar 21 02:28:18 PM PDT 24
Finished Mar 21 02:59:48 PM PDT 24
Peak memory 272764 kb
Host smart-061e7899-53eb-4ef3-8579-be9e2078149d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203026932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2203026932
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.4137670873
Short name T709
Test name
Test status
Simulation time 22323162780 ps
CPU time 1503.06 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:53:22 PM PDT 24
Peak memory 273524 kb
Host smart-31a8368e-6335-4591-96f4-ef82cb978a6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137670873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.4137670873
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1005702763
Short name T183
Test name
Test status
Simulation time 20338434108 ps
CPU time 435.19 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:35:35 PM PDT 24
Peak memory 248084 kb
Host smart-4c9d99da-489b-426c-a672-1db229a42b08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005702763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1005702763
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3846258494
Short name T657
Test name
Test status
Simulation time 4120669260 ps
CPU time 66.29 seconds
Started Mar 21 02:28:06 PM PDT 24
Finished Mar 21 02:29:13 PM PDT 24
Peak memory 248960 kb
Host smart-89c64584-bfcd-4af0-b5a0-9ba37448067a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38462
58494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3846258494
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2796690353
Short name T407
Test name
Test status
Simulation time 115988827 ps
CPU time 12.58 seconds
Started Mar 21 02:28:06 PM PDT 24
Finished Mar 21 02:28:19 PM PDT 24
Peak memory 247400 kb
Host smart-ee31017a-13b9-43f4-93b3-9c8cc1d8a7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27966
90353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2796690353
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1839855707
Short name T386
Test name
Test status
Simulation time 53873900 ps
CPU time 4.93 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:28:25 PM PDT 24
Peak memory 239220 kb
Host smart-921dcc95-e800-424d-b731-b00b789b8d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
55707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1839855707
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2684973671
Short name T468
Test name
Test status
Simulation time 221750084 ps
CPU time 25.27 seconds
Started Mar 21 02:28:08 PM PDT 24
Finished Mar 21 02:28:33 PM PDT 24
Peak memory 256084 kb
Host smart-1fb4517a-cebb-458c-8d4f-126f6b689368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26849
73671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2684973671
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1359315399
Short name T283
Test name
Test status
Simulation time 19404281782 ps
CPU time 772.45 seconds
Started Mar 21 02:28:19 PM PDT 24
Finished Mar 21 02:41:13 PM PDT 24
Peak memory 273076 kb
Host smart-840ee1e9-cd72-44cf-9966-677f6b14d177
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359315399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1359315399
Directory /workspace/9.alert_handler_stress_all/latest
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