Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	89100	1			T3	2718		T5	39		T12	9
class_i[0x1]	42476	1			T5	255		T12	39		T7	4
class_i[0x2]	62029	1			T2	3980		T5	2		T12	39
class_i[0x3]	62696	1			T3	7		T6	5		T5	17

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	61284	1			T2	909		T3	746		T6	1
alert[0x1]	71251	1			T2	1099		T3	634		T6	1
alert[0x2]	62292	1			T2	964		T3	647		T6	1
alert[0x3]	61474	1			T2	1008		T3	698		T6	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

256031

1

T2

3980

T3

2725

T5

313

esc_ping_fail

270

1

T6

5

T7

4

T8

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61199	1			T2	909		T3	746		T5	130
esc_integrity_fail	alert[0x1]	71184	1			T2	1099		T3	634		T5	28
esc_integrity_fail	alert[0x2]	62226	1			T2	964		T3	647		T5	129
esc_integrity_fail	alert[0x3]	61422	1			T2	1008		T3	698		T5	26
esc_ping_fail	alert[0x0]	85	1			T6	1		T7	2		T8	4
esc_ping_fail	alert[0x1]	67	1			T6	1		T7	1		T8	1
esc_ping_fail	alert[0x2]	66	1			T6	1		T7	1		T8	1
esc_ping_fail	alert[0x3]	52	1			T6	2		T8	2		T79	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	89039	1			T3	2718		T5	39		T12	9
esc_integrity_fail	class_i[0x1]	42389	1			T5	255		T12	39		T7	1
esc_integrity_fail	class_i[0x2]	61954	1			T2	3980		T5	2		T12	39
esc_integrity_fail	class_i[0x3]	62649	1			T3	7		T5	17		T12	9
esc_ping_fail	class_i[0x0]	61	1			T8	8		T79	7		T311	4
esc_ping_fail	class_i[0x1]	87	1			T7	3		T323	4		T314	2
esc_ping_fail	class_i[0x2]	75	1			T7	1		T71	6		T316	11
esc_ping_fail	class_i[0x3]	47	1			T6	5		T311	2		T241	1