Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	671533363	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	671533363	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	671533363	671361992	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	671533363	671361992	0	0
tb.dut.EdnKnownO_A	0	0	671533363	671361992	0	0
tb.dut.EscPKnownO_A	0	0	671533363	671361992	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	671533363	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	671533363	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	671533363	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	671533363	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	671533363	80	0	0
tb.dut.IrqAKnownO_A	0	0	671533363	671361992	0	0
tb.dut.IrqBKnownO_A	0	0	671533363	671361992	0	0
tb.dut.IrqCKnownO_A	0	0	671533363	671361992	0	0
tb.dut.IrqDKnownO_A	0	0	671533363	671361992	0	0
tb.dut.TlAReadyKnownO_A	0	0	671533363	671361992	0	0
tb.dut.TlDValidKnownO_A	0	0	671533363	671361992	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	692591353	3230685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	692591353	12419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	692591353	11420	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	692591353	11945	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	692591353	11025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	692591353	11319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	692591353	11112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	692591353	11026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	692591353	11428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	692591353	11082	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	692591353	12361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	692591353	12262	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	692591353	10863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	692591353	12203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	692591353	10986	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	692591353	12348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	692591353	11255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	692591353	11194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	692591353	11179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	692591353	11216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	692591353	11274	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	692591353	11077	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	692591353	11023	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	692591353	11187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	692591353	10919	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	692591353	11142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	692591353	12131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	692591353	11272	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	692591353	11415	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	692591353	12139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	692591353	11235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	692591353	11164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	692591353	11145	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	692591353	11177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	692591353	10970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	692591353	12449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	692591353	11106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	692591353	12191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	692591353	11080	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	692591353	11085	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	692591353	12181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	692591353	11053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	692591353	12442	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	692591353	12361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	692591353	12199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	692591353	12357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	692591353	12480	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	692591353	10865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	692591353	11165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	692591353	10926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	692591353	10950	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	692591353	11020	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	692591353	11075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	692591353	12217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	692591353	11118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	692591353	12130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	692591353	11129	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	692591353	11131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	692591353	10993	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	692591353	10931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	692591353	12001	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	692591353	10906	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	692591353	11991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	692591353	10908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	692591353	11114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	692591353	11250	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	692591353	11184	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	692591353	11230	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	692591353	11348	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	692591353	11053	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	692591353	20483	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	692591353	12278	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	692591353	10893	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	692591353	12534	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	692591353	11441	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	692591353	11272	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	692591353	10985	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	692591353	11021	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	692591353	11244	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	671533363	3526	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	671533363	230251	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	671533363	323841639	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	671533363	276	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	671533363	787	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	671533363	47	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	671533363	380	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	670865601	228413558	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	671533363	904	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	671533363	889	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	671533363	875	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	671533363	866	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	671533363	1127	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	671533363	119778	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	671533363	994	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	671533363	84	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671533363	1441	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	671533363	1201	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	671533363	671361992	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	671533363	3350	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	671533363	195214	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	671533363	390227832	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	671533363	308	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	671533363	488	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	671533363	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	671533363	224	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	670865601	307854971	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	671533363	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	671533363	556	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	671533363	543	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	671533363	532	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	671533363	1023	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	671533363	113744	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	671533363	930	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	671533363	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671533363	1464	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	671533363	1224	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	671533363	671361992	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	671533363	3152	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	671533363	166220	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	671533363	375962011	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	671533363	262	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	671533363	491	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	671533363	19	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	671533363	211	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	670865601	330622728	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	671533363	548	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	671533363	538	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	671533363	526	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	671533363	522	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	671533363	1111	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	671533363	102859	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	671533363	1039	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	671533363	52	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671533363	1466	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	671533363	1226	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	671533363	671361992	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	671533363	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	671533363	5596	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	671533363	165905	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	671533363	387952376	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	671533363	303	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	671533363	458	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	671533363	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	671533363	193	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	670865601	317512768	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	671533363	527	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	671533363	511	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	671533363	504	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	671533363	501	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	671533363	857	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	671533363	92258	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	671533363	780	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	671533363	59	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671533363	1490	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	671533363	1250	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	671533363	671361992	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	692591353	136257256	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	692591353	691927063	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	692591353	691927063	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	692591353	185342490	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	692591353	691927063	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	692591353	691927063	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	827	827	0	0
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