Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	182	1			T5	1		T18	1		T14	2
index[0x1]	169	1			T3	1		T12	1		T14	2
index[0x2]	162	1			T2	1		T5	4		T17	1
index[0x3]	161	1			T1	1		T5	2		T12	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	221	1			T5	3		T12	1		T21	1
lens_less_than_1000[1]	145	1			T2	1		T3	1		T17	1
lens_less_than_1000[2]	92	1			T5	2		T18	1		T12	1
lens_less_than_1000[3]	52	1			T14	1		T22	1		T44	1
lens_less_than_1000[4]	53	1			T1	1		T14	3		T20	2
lens_less_than_1000[5]	40	1			T5	1		T76	2		T82	1
lens_less_than_1000[6]	29	1			T29	1		T288	3		T289	1
lens_less_than_1000[7]	19	1			T5	1		T77	1		T290	1
lens_less_than_1000[8]	8	1			T26	1		T291	1		T117	2
lens_less_than_1000[9]	5	1			T106	1		T117	2		T216	1
len_2	10	1			T21	1		T76	1		T27	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T66	1		T76	1		T78	1
index[0x0]	lens_less_than_1000[1]	41	1			T21	1		T47	1		T30	1
index[0x0]	lens_less_than_1000[2]	30	1			T5	1		T18	1		T21	1
index[0x0]	lens_less_than_1000[3]	12	1			T14	1		T83	1		T54	1
index[0x0]	lens_less_than_1000[4]	15	1			T14	1		T20	1		T82	1
index[0x0]	lens_less_than_1000[5]	6	1			T189	1		T193	1		T292	2
index[0x0]	lens_less_than_1000[6]	6	1			T289	1		T293	1		T116	1
index[0x0]	lens_less_than_1000[7]	6	1			T104	1		T215	1		T61	1
index[0x0]	lens_less_than_1000[9]	2	1			T106	1		T216	1		-	-
index[0x0]	len_2	2	1			T27	2		-	-		-	-
index[0x1]	lens_less_than_1000[0]	57	1			T12	1		T76	1		T83	3
index[0x1]	lens_less_than_1000[1]	32	1			T3	1		T25	1		T83	1
index[0x1]	lens_less_than_1000[2]	24	1			T75	1		T89	1		T260	1
index[0x1]	lens_less_than_1000[3]	8	1			T22	1		T44	1		T237	1
index[0x1]	lens_less_than_1000[4]	17	1			T14	2		T76	1		T96	1
index[0x1]	lens_less_than_1000[5]	8	1			T82	1		T94	1		T294	1
index[0x1]	lens_less_than_1000[6]	7	1			T295	1		T194	1		T275	1
index[0x1]	lens_less_than_1000[7]	6	1			T77	1		T189	1		T283	1
index[0x1]	lens_less_than_1000[8]	2	1			T291	1		T117	1		-	-
index[0x1]	lens_less_than_1000[9]	2	1			T117	2		-	-		-	-
index[0x1]	len_2	6	1			T21	1		T76	1		T61	1
index[0x2]	lens_less_than_1000[0]	51	1			T5	1		T76	1		T83	1
index[0x2]	lens_less_than_1000[1]	33	1			T2	1		T17	1		T25	1
index[0x2]	lens_less_than_1000[2]	24	1			T5	1		T76	1		T249	1
index[0x2]	lens_less_than_1000[3]	19	1			T76	2		T77	1		T24	1
index[0x2]	lens_less_than_1000[4]	14	1			T20	1		T24	1		T91	1
index[0x2]	lens_less_than_1000[5]	12	1			T5	1		T76	2		T288	1
index[0x2]	lens_less_than_1000[6]	3	1			T296	1		T280	1		T297	1
index[0x2]	lens_less_than_1000[7]	3	1			T5	1		T298	1		T299	1
index[0x2]	lens_less_than_1000[8]	2	1			T26	1		T117	1		-	-
index[0x2]	len_2	1	1			T300	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	51	1			T5	2		T21	1		T22	1
index[0x3]	lens_less_than_1000[1]	39	1			T14	1		T77	1		T25	1
index[0x3]	lens_less_than_1000[2]	14	1			T12	1		T24	1		T190	1
index[0x3]	lens_less_than_1000[3]	13	1			T88	1		T70	1		T34	1
index[0x3]	lens_less_than_1000[4]	7	1			T1	1		T278	1		T301	1
index[0x3]	lens_less_than_1000[5]	14	1			T48	1		T302	8		T303	1
index[0x3]	lens_less_than_1000[6]	13	1			T29	1		T288	3		T55	1
index[0x3]	lens_less_than_1000[7]	4	1			T290	1		T215	1		T304	1
index[0x3]	lens_less_than_1000[8]	4	1			T305	3		T306	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T285	1		-	-		-	-
index[0x3]	len_2	1	1			T38	1		-	-		-	-