Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	84	1			T5	1		T76	2		T80	1
class_index[0x1]	69	1			T20	1		T75	2		T76	1
class_index[0x2]	52	1			T5	1		T75	1		T76	1
class_index[0x3]	59	1			T3	1		T5	1		T12	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T3	1		T5	2		T12	1
intr_timeout_cnt[1]	61	1			T76	1		T77	1		T82	1
intr_timeout_cnt[2]	23	1			T75	2		T85	1		T88	1
intr_timeout_cnt[3]	16	1			T75	1		T83	1		T47	1
intr_timeout_cnt[4]	12	1			T5	1		T20	1		T76	1
intr_timeout_cnt[5]	16	1			T76	1		T24	2		T121	1
intr_timeout_cnt[6]	17	1			T70	2		T98	1		T215	1
intr_timeout_cnt[7]	8	1			T88	1		T270	1		T271	1
intr_timeout_cnt[8]	6	1			T70	1		T48	2		T52	1
intr_timeout_cnt[9]	3	1			T27	1		T215	1		T272	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T5	1		T80	1		T77	1
class_index[0x0]	intr_timeout_cnt[1]	23	1			T27	2		T52	1		T98	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T88	1		T59	1		T98	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T267	1		T93	1		T273	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T76	1		T215	1		T274	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T76	1		T121	1		T98	1
class_index[0x0]	intr_timeout_cnt[6]	8	1			T61	1		T275	1		T276	1
class_index[0x0]	intr_timeout_cnt[7]	3	1			T271	1		T215	1		T277	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T52	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	26	1			T76	1		T87	1		T270	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T77	1		T47	1		T70	1
class_index[0x1]	intr_timeout_cnt[2]	11	1			T75	2		T85	1		T27	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T70	1		T52	1		T276	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T20	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T52	1		T278	1		T279	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T98	1		T215	1		T280	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T88	1		T270	1		T281	1
class_index[0x1]	intr_timeout_cnt[8]	1	1			T48	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T215	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T5	1		T91	1		T106	3
class_index[0x2]	intr_timeout_cnt[1]	14	1			T76	1		T47	1		T91	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T278	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	6	1			T75	1		T47	1		T92	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T92	1		T282	1		T283	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T284	1		T215	1		T285	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T115	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T48	1		T279	1		T286	1
class_index[0x3]	intr_timeout_cnt[0]	26	1			T3	1		T12	1		T76	2
class_index[0x3]	intr_timeout_cnt[1]	9	1			T82	1		T37	1		T56	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T92	1		T275	1		T287	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T83	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T5	1		T93	1		T283	1
class_index[0x3]	intr_timeout_cnt[5]	7	1			T24	2		T270	1		T52	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T70	2		T263	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T281	1		T283	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T70	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T27	1		T272	1		-	-