Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	349277	1			T1	11		T2	1529		T3	1275
all_values[1]	349277	1			T1	11		T2	1529		T3	1275
all_values[2]	349277	1			T1	11		T2	1529		T3	1275
all_values[3]	349277	1			T1	11		T2	1529		T3	1275

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694747

1

T1

17

T2

3160

T3

2575

auto[1]

702361

1

T1

27

T2

2956

T3

2525

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

830684

1

T1

40

T2

3085

T3

3119

auto[1]

566424

1

T1

4

T2

3031

T3

1981

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	98453	1			T1	5		T2	409		T3	392
all_values[0]	auto[0]	auto[1]	74815	1			T1	2		T2	382		T3	267
all_values[0]	auto[1]	auto[0]	100524	1			T1	2		T2	379		T3	356
all_values[0]	auto[1]	auto[1]	75485	1			T1	2		T2	359		T3	260
all_values[1]	auto[0]	auto[0]	103770	1			T1	5		T2	381		T3	390
all_values[1]	auto[0]	auto[1]	69690	1			T2	380		T3	245		T4	38
all_values[1]	auto[1]	auto[0]	105384	1			T1	6		T2	384		T3	383
all_values[1]	auto[1]	auto[1]	70433	1			T2	384		T3	257		T4	52
all_values[2]	auto[0]	auto[0]	105201	1			T1	3		T2	406		T3	404
all_values[2]	auto[0]	auto[1]	68524	1			T2	405		T3	222		T4	37
all_values[2]	auto[1]	auto[0]	107005	1			T1	8		T2	359		T3	403
all_values[2]	auto[1]	auto[1]	68547	1			T2	359		T3	246		T4	48
all_values[3]	auto[0]	auto[0]	104565	1			T1	2		T2	399		T3	411
all_values[3]	auto[0]	auto[1]	69729	1			T2	398		T3	244		T4	38
all_values[3]	auto[1]	auto[0]	105782	1			T1	9		T2	368		T3	380
all_values[3]	auto[1]	auto[1]	69201	1			T2	364		T3	240		T4	52