Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	349277	1			T1	11		T2	1529		T3	1275
all_pins[1]	349277	1			T1	11		T2	1529		T3	1275
all_pins[2]	349277	1			T1	11		T2	1529		T3	1275
all_pins[3]	349277	1			T1	11		T2	1529		T3	1275

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1113442	1			T1	42		T2	4650		T3	4097
values[0x1]	283666	1			T1	2		T2	1466		T3	1003
transitions[0x0=>0x1]	188981	1			T1	1		T2	939		T3	641
transitions[0x1=>0x0]	189238	1			T1	2		T2	939		T3	641

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	273792	1			T1	9		T2	1170		T3	1015
all_pins[0]	values[0x1]	75485	1			T1	2		T2	359		T3	260
all_pins[0]	transitions[0x0=>0x1]	74833	1			T1	1		T2	359		T3	260
all_pins[0]	transitions[0x1=>0x0]	68806	1			T2	364		T3	240		T4	52
all_pins[1]	values[0x0]	278844	1			T1	11		T2	1145		T3	1018
all_pins[1]	values[0x1]	70433	1			T2	384		T3	257		T4	52
all_pins[1]	transitions[0x0=>0x1]	38366	1			T2	200		T3	131		T4	28
all_pins[1]	transitions[0x1=>0x0]	43418	1			T1	2		T2	175		T3	134
all_pins[2]	values[0x0]	280730	1			T1	11		T2	1170		T3	1029
all_pins[2]	values[0x1]	68547	1			T2	359		T3	246		T4	48
all_pins[2]	transitions[0x0=>0x1]	37417	1			T2	182		T3	120		T4	22
all_pins[2]	transitions[0x1=>0x0]	39303	1			T2	207		T3	131		T4	26
all_pins[3]	values[0x0]	280076	1			T1	11		T2	1165		T3	1035
all_pins[3]	values[0x1]	69201	1			T2	364		T3	240		T4	52
all_pins[3]	transitions[0x0=>0x1]	38365	1			T2	198		T3	130		T4	22
all_pins[3]	transitions[0x1=>0x0]	37711	1			T2	193		T3	136		T4	18