Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90475	1			T2	654		T5	229		T12	366
accum_cnt_1000	236766	1			T2	925		T3	606		T4	88
accum_cnt_100	29036	1			T2	64		T3	92		T4	43
accum_cnt_50	62351	1			T2	1192		T3	111		T4	33
accum_cnt_10	168620	1			T1	2		T2	1168		T3	907
accum_cnt_0	400347	1			T1	26		T2	3		T3	1956

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	257112	1			T1	7		T2	1153		T3	918
class_index[0x1]	257112	1			T1	7		T2	1153		T3	918
class_index[0x2]	257112	1			T1	7		T2	1153		T3	918
class_index[0x3]	257112	1			T1	7		T2	1153		T3	918

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26256	1			T2	383		T5	229		T12	218
class_index[0x0]	accum_cnt_1000	73552	1			T2	690		T4	31		T5	538
class_index[0x0]	accum_cnt_100	9058	1			T2	42		T4	27		T5	24
class_index[0x0]	accum_cnt_50	17957	1			T2	29		T3	8		T4	20
class_index[0x0]	accum_cnt_10	45178	1			T1	2		T2	8		T3	140
class_index[0x0]	accum_cnt_0	73045	1			T1	5		T2	1		T3	770
class_index[0x1]	accum_cnt_2000	20803	1			T2	271		T14	446		T15	478
class_index[0x1]	accum_cnt_1000	55856	1			T2	235		T3	6		T4	57
class_index[0x1]	accum_cnt_100	7860	1			T2	22		T3	22		T4	16
class_index[0x1]	accum_cnt_50	14566	1			T2	17		T3	15		T4	13
class_index[0x1]	accum_cnt_10	45198	1			T2	2		T3	729		T4	4
class_index[0x1]	accum_cnt_0	102318	1			T1	7		T3	146		T16	19
class_index[0x2]	accum_cnt_2000	21346	1			T29	192		T77	380		T25	328
class_index[0x2]	accum_cnt_1000	56012	1			T5	26		T12	711		T21	28
class_index[0x2]	accum_cnt_100	6729	1			T3	11		T5	31		T12	36
class_index[0x2]	accum_cnt_50	10891	1			T3	33		T5	50		T18	2
class_index[0x2]	accum_cnt_10	35981	1			T2	1153		T3	20		T5	72
class_index[0x2]	accum_cnt_0	117939	1			T1	7		T3	854		T16	19
class_index[0x3]	accum_cnt_2000	22070	1			T12	148		T21	432		T24	243
class_index[0x3]	accum_cnt_1000	51346	1			T3	600		T12	565		T13	684
class_index[0x3]	accum_cnt_100	5389	1			T3	59		T12	30		T13	88
class_index[0x3]	accum_cnt_50	18937	1			T2	1146		T3	55		T5	30
class_index[0x3]	accum_cnt_10	42263	1			T2	5		T3	18		T5	59
class_index[0x3]	accum_cnt_0	107045	1			T1	7		T2	2		T3	186