Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4177	1			T6	1		T85	2		T88	1
alert[0x1]	3807	1			T7	1		T8	1		T66	710
alert[0x2]	2501	1			T2	272		T3	36		T8	1
alert[0x3]	3613	1			T3	399		T6	1		T77	14
alert[0x4]	8197	1			T76	30		T29	17		T79	1
alert[0x5]	2283	1			T66	74		T77	7		T83	39
alert[0x6]	3369	1			T24	236		T83	128		T260	168
alert[0x7]	5767	1			T2	3		T3	88		T66	127
alert[0x8]	3757	1			T2	87		T7	1		T66	102
alert[0x9]	7744	1			T2	30		T77	1		T24	1372
alert[0xa]	1883	1			T66	170		T76	222		T24	119
alert[0xb]	5184	1			T6	1		T77	4		T83	121
alert[0xc]	8689	1			T2	1512		T3	19		T12	1
alert[0xd]	1648	1			T8	1		T66	41		T76	151
alert[0xe]	3574	1			T2	232		T3	58		T7	1
alert[0xf]	2462	1			T66	11		T77	592		T311	1
alert[0x10]	5748	1			T24	51		T79	1		T311	1
alert[0x11]	3693	1			T2	191		T66	32		T83	35
alert[0x12]	5754	1			T79	1		T83	87		T85	10
alert[0x13]	9775	1			T7	1		T66	4		T29	6
alert[0x14]	11393	1			T2	204		T3	2		T8	1
alert[0x15]	5476	1			T2	420		T77	257		T24	5
alert[0x16]	2335	1			T6	1		T8	2		T66	89
alert[0x17]	3958	1			T6	1		T12	2		T311	1
alert[0x18]	5428	1			T8	1		T83	466		T88	7
alert[0x19]	3222	1			T3	12		T29	2		T261	5
alert[0x1a]	7609	1			T2	32		T3	25		T8	1
alert[0x1b]	3265	1			T12	4		T66	864		T77	28
alert[0x1c]	12618	1			T3	223		T8	1		T66	445
alert[0x1d]	5856	1			T6	1		T66	99		T76	117
alert[0x1e]	11224	1			T2	92		T3	3		T77	20
alert[0x1f]	3319	1			T2	8		T12	1		T24	376
alert[0x20]	10559	1			T2	2		T3	8		T66	789
alert[0x21]	6695	1			T2	12		T3	1615		T66	18
alert[0x22]	4389	1			T2	37		T7	1		T66	140
alert[0x23]	2986	1			T3	2		T76	47		T77	4
alert[0x24]	4546	1			T2	81		T3	345		T76	9
alert[0x25]	4348	1			T6	1		T76	3		T260	17
alert[0x26]	2081	1			T66	117		T24	64		T79	2
alert[0x27]	7113	1			T77	7		T24	163		T79	1
alert[0x28]	2925	1			T2	33		T6	2		T8	1
alert[0x29]	3193	1			T2	61		T66	135		T77	29
alert[0x2a]	4820	1			T2	162		T6	1		T7	1
alert[0x2b]	7321	1			T3	8		T8	1		T45	1
alert[0x2c]	2227	1			T2	28		T8	1		T66	109
alert[0x2d]	1834	1			T6	1		T8	1		T76	3
alert[0x2e]	6769	1			T66	9		T76	1		T260	315
alert[0x2f]	7459	1			T2	9		T66	16		T77	3
alert[0x30]	5999	1			T66	112		T77	111		T24	2
alert[0x31]	7001	1			T2	387		T21	2		T79	2
alert[0x32]	1164	1			T3	41		T6	1		T12	2
alert[0x33]	8549	1			T66	31		T24	697		T83	1239
alert[0x34]	2710	1			T8	1		T66	6		T77	173
alert[0x35]	2299	1			T6	1		T66	21		T24	81
alert[0x36]	4735	1			T3	16		T8	1		T66	26
alert[0x37]	8534	1			T2	14		T66	129		T77	3
alert[0x38]	3620	1			T2	7		T6	2		T8	1
alert[0x39]	2480	1			T2	159		T66	224		T76	1
alert[0x3a]	6339	1			T7	1		T8	1		T77	16
alert[0x3b]	4636	1			T2	11		T3	10		T8	1
alert[0x3c]	9424	1			T2	113		T83	510		T260	151
alert[0x3d]	1854	1			T3	30		T7	1		T8	2
alert[0x3e]	2534	1			T2	10		T5	3		T24	70
alert[0x3f]	8602	1			T66	71		T77	62		T24	139
alert[0x40]	4900	1			T2	20		T3	22		T7	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	48525	1			T3	2961		T7	3		T8	1
class_i[0x1]	98882	1			T2	4229		T6	13		T5	3
class_i[0x2]	79369	1			T6	1		T12	3		T7	2
class_i[0x3]	107197	1			T3	1		T6	1		T12	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

333334

1

T2

4229

T3

2962

T5

3

alert_ping_fail

639

1

T6

15

T7

9

T8

20

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4171	1			T85	2		T88	1		T72	29
alert_integrity_fail	alert[0x1]	3792	1			T66	710		T77	7		T83	32
alert_integrity_fail	alert[0x2]	2492	1			T2	272		T3	36		T77	4
alert_integrity_fail	alert[0x3]	3604	1			T3	399		T77	14		T83	9
alert_integrity_fail	alert[0x4]	8189	1			T76	30		T29	17		T83	395
alert_integrity_fail	alert[0x5]	2275	1			T66	74		T77	7		T83	39
alert_integrity_fail	alert[0x6]	3362	1			T24	236		T83	128		T260	168
alert_integrity_fail	alert[0x7]	5754	1			T2	3		T3	88		T66	127
alert_integrity_fail	alert[0x8]	3744	1			T2	87		T66	102		T83	345
alert_integrity_fail	alert[0x9]	7731	1			T2	30		T77	1		T24	1372
alert_integrity_fail	alert[0xa]	1874	1			T66	170		T76	222		T24	119
alert_integrity_fail	alert[0xb]	5178	1			T77	4		T83	121		T70	1
alert_integrity_fail	alert[0xc]	8683	1			T2	1512		T3	19		T12	1
alert_integrity_fail	alert[0xd]	1636	1			T66	41		T76	151		T70	4
alert_integrity_fail	alert[0xe]	3563	1			T2	232		T3	58		T76	21
alert_integrity_fail	alert[0xf]	2454	1			T66	11		T77	592		T26	6
alert_integrity_fail	alert[0x10]	5743	1			T24	51		T260	77		T70	3
alert_integrity_fail	alert[0x11]	3689	1			T2	191		T66	32		T83	35
alert_integrity_fail	alert[0x12]	5748	1			T83	87		T85	10		T260	1318
alert_integrity_fail	alert[0x13]	9750	1			T66	4		T29	6		T24	78
alert_integrity_fail	alert[0x14]	11381	1			T2	204		T3	2		T66	163
alert_integrity_fail	alert[0x15]	5466	1			T2	420		T77	257		T24	5
alert_integrity_fail	alert[0x16]	2315	1			T66	89		T88	4		T26	49
alert_integrity_fail	alert[0x17]	3950	1			T12	2		T312	57		T91	1817
alert_integrity_fail	alert[0x18]	5423	1			T83	466		T88	7		T260	35
alert_integrity_fail	alert[0x19]	3213	1			T3	12		T29	2		T261	5
alert_integrity_fail	alert[0x1a]	7597	1			T2	32		T3	25		T76	61
alert_integrity_fail	alert[0x1b]	3250	1			T12	4		T66	864		T77	28
alert_integrity_fail	alert[0x1c]	12606	1			T3	223		T66	445		T76	6
alert_integrity_fail	alert[0x1d]	5846	1			T66	99		T76	117		T77	28
alert_integrity_fail	alert[0x1e]	11212	1			T2	92		T3	3		T77	20
alert_integrity_fail	alert[0x1f]	3309	1			T2	8		T12	1		T24	376
alert_integrity_fail	alert[0x20]	10545	1			T2	2		T3	8		T66	789
alert_integrity_fail	alert[0x21]	6690	1			T2	12		T3	1615		T66	18
alert_integrity_fail	alert[0x22]	4378	1			T2	37		T66	140		T75	1
alert_integrity_fail	alert[0x23]	2981	1			T3	2		T76	47		T77	4
alert_integrity_fail	alert[0x24]	4535	1			T2	81		T3	345		T76	9
alert_integrity_fail	alert[0x25]	4337	1			T76	3		T260	17		T91	650
alert_integrity_fail	alert[0x26]	2068	1			T66	117		T24	64		T260	37
alert_integrity_fail	alert[0x27]	7102	1			T77	7		T24	163		T83	213
alert_integrity_fail	alert[0x28]	2913	1			T2	33		T66	29		T76	2
alert_integrity_fail	alert[0x29]	3187	1			T2	61		T66	135		T77	29
alert_integrity_fail	alert[0x2a]	4810	1			T2	162		T77	2		T26	2
alert_integrity_fail	alert[0x2b]	7312	1			T3	8		T66	40		T76	34
alert_integrity_fail	alert[0x2c]	2215	1			T2	28		T66	109		T77	2
alert_integrity_fail	alert[0x2d]	1820	1			T76	3		T29	1		T77	35
alert_integrity_fail	alert[0x2e]	6762	1			T66	9		T76	1		T260	315
alert_integrity_fail	alert[0x2f]	7446	1			T2	9		T66	16		T77	3
alert_integrity_fail	alert[0x30]	5986	1			T66	112		T77	111		T24	2
alert_integrity_fail	alert[0x31]	6991	1			T2	387		T21	2		T83	128
alert_integrity_fail	alert[0x32]	1157	1			T3	41		T12	2		T76	53
alert_integrity_fail	alert[0x33]	8542	1			T66	31		T24	697		T83	1239
alert_integrity_fail	alert[0x34]	2694	1			T66	6		T77	173		T24	94
alert_integrity_fail	alert[0x35]	2293	1			T66	21		T24	81		T251	2
alert_integrity_fail	alert[0x36]	4726	1			T3	16		T66	26		T77	75
alert_integrity_fail	alert[0x37]	8530	1			T2	14		T66	129		T77	3
alert_integrity_fail	alert[0x38]	3604	1			T2	7		T21	3		T66	13
alert_integrity_fail	alert[0x39]	2474	1			T2	159		T66	224		T76	1
alert_integrity_fail	alert[0x3a]	6327	1			T77	16		T83	21		T70	1
alert_integrity_fail	alert[0x3b]	4628	1			T2	11		T3	10		T66	26
alert_integrity_fail	alert[0x3c]	9410	1			T2	113		T83	510		T260	151
alert_integrity_fail	alert[0x3d]	1847	1			T3	30		T77	21		T83	62
alert_integrity_fail	alert[0x3e]	2529	1			T2	10		T5	3		T24	70
alert_integrity_fail	alert[0x3f]	8599	1			T66	71		T77	62		T24	139
alert_integrity_fail	alert[0x40]	4896	1			T2	20		T3	22		T66	1033
alert_ping_fail	alert[0x0]	6	1			T6	1		T241	1		T313	1
alert_ping_fail	alert[0x1]	15	1			T7	1		T8	1		T101	1
alert_ping_fail	alert[0x2]	9	1			T8	1		T314	1		T313	1
alert_ping_fail	alert[0x3]	9	1			T6	1		T101	1		T315	1
alert_ping_fail	alert[0x4]	8	1			T79	1		T241	1		T101	2
alert_ping_fail	alert[0x5]	8	1			T71	1		T316	1		T241	1
alert_ping_fail	alert[0x6]	7	1			T309	1		T314	1		T317	1
alert_ping_fail	alert[0x7]	13	1			T241	1		T244	3		T308	1
alert_ping_fail	alert[0x8]	13	1			T7	1		T79	1		T241	1
alert_ping_fail	alert[0x9]	13	1			T79	1		T311	1		T71	1
alert_ping_fail	alert[0xa]	9	1			T316	1		T241	1		T307	1
alert_ping_fail	alert[0xb]	6	1			T6	1		T316	1		T318	2
alert_ping_fail	alert[0xc]	6	1			T319	1		T320	1		T321	1
alert_ping_fail	alert[0xd]	12	1			T8	1		T79	1		T71	1
alert_ping_fail	alert[0xe]	11	1			T7	1		T79	1		T319	1
alert_ping_fail	alert[0xf]	8	1			T311	1		T71	1		T316	1
alert_ping_fail	alert[0x10]	5	1			T79	1		T311	1		T101	1
alert_ping_fail	alert[0x11]	4	1			T316	1		T319	1		T315	1
alert_ping_fail	alert[0x12]	6	1			T79	1		T241	1		T319	1
alert_ping_fail	alert[0x13]	25	1			T7	1		T79	1		T311	1
alert_ping_fail	alert[0x14]	12	1			T8	1		T322	1		T319	2
alert_ping_fail	alert[0x15]	10	1			T79	1		T311	1		T307	1
alert_ping_fail	alert[0x16]	20	1			T6	1		T8	2		T79	1
alert_ping_fail	alert[0x17]	8	1			T6	1		T311	1		T313	1
alert_ping_fail	alert[0x18]	5	1			T8	1		T313	1		T317	1
alert_ping_fail	alert[0x19]	9	1			T71	1		T321	1		T213	1
alert_ping_fail	alert[0x1a]	12	1			T8	1		T79	1		T311	1
alert_ping_fail	alert[0x1b]	15	1			T79	2		T71	1		T313	1
alert_ping_fail	alert[0x1c]	12	1			T8	1		T316	1		T101	1
alert_ping_fail	alert[0x1d]	10	1			T6	1		T311	1		T307	1
alert_ping_fail	alert[0x1e]	12	1			T311	1		T101	1		T323	1
alert_ping_fail	alert[0x1f]	10	1			T79	1		T71	1		T323	1
alert_ping_fail	alert[0x20]	14	1			T41	1		T241	1		T101	1
alert_ping_fail	alert[0x21]	5	1			T316	2		T324	1		T325	1
alert_ping_fail	alert[0x22]	11	1			T7	1		T311	1		T241	1
alert_ping_fail	alert[0x23]	5	1			T316	1		T241	1		T315	1
alert_ping_fail	alert[0x24]	11	1			T323	1		T314	1		T313	1
alert_ping_fail	alert[0x25]	11	1			T6	1		T316	1		T241	2
alert_ping_fail	alert[0x26]	13	1			T79	2		T71	1		T321	1
alert_ping_fail	alert[0x27]	11	1			T79	1		T319	1		T326	1
alert_ping_fail	alert[0x28]	12	1			T6	2		T8	1		T320	1
alert_ping_fail	alert[0x29]	6	1			T101	1		T313	1		T327	1
alert_ping_fail	alert[0x2a]	10	1			T6	1		T7	1		T313	1
alert_ping_fail	alert[0x2b]	9	1			T8	1		T45	1		T71	1
alert_ping_fail	alert[0x2c]	12	1			T8	1		T311	1		T101	1
alert_ping_fail	alert[0x2d]	14	1			T6	1		T8	1		T311	1
alert_ping_fail	alert[0x2e]	7	1			T241	1		T213	1		T328	1
alert_ping_fail	alert[0x2f]	13	1			T311	1		T101	2		T319	2
alert_ping_fail	alert[0x30]	13	1			T101	1		T244	1		T319	1
alert_ping_fail	alert[0x31]	10	1			T79	2		T101	1		T315	3
alert_ping_fail	alert[0x32]	7	1			T6	1		T213	1		T318	1
alert_ping_fail	alert[0x33]	7	1			T326	1		T327	1		T321	1
alert_ping_fail	alert[0x34]	16	1			T8	1		T79	1		T311	1
alert_ping_fail	alert[0x35]	6	1			T6	1		T71	1		T329	1
alert_ping_fail	alert[0x36]	9	1			T8	1		T313	1		T319	1
alert_ping_fail	alert[0x37]	4	1			T329	1		T330	1		T331	1
alert_ping_fail	alert[0x38]	16	1			T6	2		T8	1		T79	1
alert_ping_fail	alert[0x39]	6	1			T79	1		T71	1		T316	1
alert_ping_fail	alert[0x3a]	12	1			T7	1		T8	1		T241	1
alert_ping_fail	alert[0x3b]	8	1			T8	1		T313	1		T332	1
alert_ping_fail	alert[0x3c]	14	1			T323	2		T327	1		T321	2
alert_ping_fail	alert[0x3d]	7	1			T7	1		T8	2		T79	1
alert_ping_fail	alert[0x3e]	5	1			T101	1		T333	1		T330	1
alert_ping_fail	alert[0x3f]	3	1			T316	1		T334	1		T335	1
alert_ping_fail	alert[0x40]	4	1			T7	1		T241	1		T213	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	48425	1			T3	2961		T21	5		T66	6086
alert_integrity_fail	class_i[0x1]	98668	1			T2	4229		T5	3		T76	1858
alert_integrity_fail	class_i[0x2]	79179	1			T12	3		T76	7		T24	7781
alert_integrity_fail	class_i[0x3]	107062	1			T3	1		T12	7		T66	3
alert_ping_fail	class_i[0x0]	100	1			T7	3		T8	1		T311	3
alert_ping_fail	class_i[0x1]	214	1			T6	13		T7	2		T311	7
alert_ping_fail	class_i[0x2]	190	1			T6	1		T7	2		T79	22
alert_ping_fail	class_i[0x3]	135	1			T6	1		T7	2		T8	19