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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.68 100.00 100.00 100.00 99.38 99.48


Total test records in report: 827
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T155 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3856423575 Mar 24 01:09:48 PM PDT 24 Mar 24 01:14:44 PM PDT 24 9550594525 ps
T768 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4153949435 Mar 24 01:09:46 PM PDT 24 Mar 24 01:09:54 PM PDT 24 408029499 ps
T769 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2481340205 Mar 24 01:09:12 PM PDT 24 Mar 24 01:09:13 PM PDT 24 9875685 ps
T770 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.229936115 Mar 24 01:09:58 PM PDT 24 Mar 24 01:10:00 PM PDT 24 9311239 ps
T771 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3941311820 Mar 24 01:09:23 PM PDT 24 Mar 24 01:09:29 PM PDT 24 247173956 ps
T772 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.368615218 Mar 24 01:09:23 PM PDT 24 Mar 24 01:09:28 PM PDT 24 31364975 ps
T773 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3796860293 Mar 24 01:09:43 PM PDT 24 Mar 24 01:09:48 PM PDT 24 119797096 ps
T774 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3926383751 Mar 24 01:09:54 PM PDT 24 Mar 24 01:09:56 PM PDT 24 9506619 ps
T775 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2352649455 Mar 24 01:09:51 PM PDT 24 Mar 24 01:09:53 PM PDT 24 10326368 ps
T776 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.373233155 Mar 24 01:09:53 PM PDT 24 Mar 24 01:09:55 PM PDT 24 13476560 ps
T160 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3176455508 Mar 24 01:09:24 PM PDT 24 Mar 24 01:10:55 PM PDT 24 2897585074 ps
T777 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1085715571 Mar 24 01:09:42 PM PDT 24 Mar 24 01:09:43 PM PDT 24 8049309 ps
T778 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1515752032 Mar 24 01:09:48 PM PDT 24 Mar 24 01:09:53 PM PDT 24 120583287 ps
T779 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3167215194 Mar 24 01:09:38 PM PDT 24 Mar 24 01:09:49 PM PDT 24 81036191 ps
T188 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.43107762 Mar 24 01:09:24 PM PDT 24 Mar 24 01:09:28 PM PDT 24 190271974 ps
T780 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2456919760 Mar 24 01:09:18 PM PDT 24 Mar 24 01:09:27 PM PDT 24 102974522 ps
T363 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2221379180 Mar 24 01:09:37 PM PDT 24 Mar 24 01:18:01 PM PDT 24 24705511592 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2272409989 Mar 24 01:09:25 PM PDT 24 Mar 24 01:09:36 PM PDT 24 606149270 ps
T782 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1075406109 Mar 24 01:09:37 PM PDT 24 Mar 24 01:09:45 PM PDT 24 2072633807 ps
T783 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1944156866 Mar 24 01:09:26 PM PDT 24 Mar 24 01:09:30 PM PDT 24 21575395 ps
T784 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4037144034 Mar 24 01:09:28 PM PDT 24 Mar 24 01:09:31 PM PDT 24 19014168 ps
T785 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1527283496 Mar 24 01:09:13 PM PDT 24 Mar 24 01:11:11 PM PDT 24 6281940227 ps
T172 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3733567666 Mar 24 01:09:27 PM PDT 24 Mar 24 01:09:31 PM PDT 24 95167154 ps
T153 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1495028201 Mar 24 01:09:39 PM PDT 24 Mar 24 01:12:23 PM PDT 24 2888526329 ps
T786 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3079148728 Mar 24 01:09:21 PM PDT 24 Mar 24 01:09:27 PM PDT 24 69543338 ps
T787 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2811104018 Mar 24 01:09:46 PM PDT 24 Mar 24 01:09:50 PM PDT 24 20530463 ps
T788 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.641582709 Mar 24 01:09:52 PM PDT 24 Mar 24 01:09:53 PM PDT 24 12876990 ps
T154 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.316356457 Mar 24 01:09:40 PM PDT 24 Mar 24 01:20:36 PM PDT 24 22962461134 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4189867781 Mar 24 01:09:43 PM PDT 24 Mar 24 01:10:04 PM PDT 24 1069697916 ps
T790 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2756383899 Mar 24 01:10:00 PM PDT 24 Mar 24 01:10:02 PM PDT 24 9525974 ps
T159 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.295348055 Mar 24 01:09:30 PM PDT 24 Mar 24 01:15:26 PM PDT 24 6412507943 ps
T163 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1170946516 Mar 24 01:09:25 PM PDT 24 Mar 24 01:12:59 PM PDT 24 1730027467 ps
T791 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2164477109 Mar 24 01:09:41 PM PDT 24 Mar 24 01:09:43 PM PDT 24 9292410 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.722144950 Mar 24 01:09:19 PM PDT 24 Mar 24 01:12:07 PM PDT 24 1637782074 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4002754024 Mar 24 01:09:22 PM PDT 24 Mar 24 01:10:34 PM PDT 24 910680292 ps
T794 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3793661728 Mar 24 01:09:42 PM PDT 24 Mar 24 01:09:47 PM PDT 24 69060231 ps
T173 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2834498775 Mar 24 01:09:29 PM PDT 24 Mar 24 01:09:52 PM PDT 24 156545361 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2031505278 Mar 24 01:09:27 PM PDT 24 Mar 24 01:10:10 PM PDT 24 1367810576 ps
T185 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.407374291 Mar 24 01:09:47 PM PDT 24 Mar 24 01:10:25 PM PDT 24 459869303 ps
T796 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2717251347 Mar 24 01:09:49 PM PDT 24 Mar 24 01:09:51 PM PDT 24 18617224 ps
T797 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2357072203 Mar 24 01:09:20 PM PDT 24 Mar 24 01:09:22 PM PDT 24 9156525 ps
T798 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1058963987 Mar 24 01:09:46 PM PDT 24 Mar 24 01:09:52 PM PDT 24 179295342 ps
T799 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2063697846 Mar 24 01:09:54 PM PDT 24 Mar 24 01:09:56 PM PDT 24 6894016 ps
T182 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1210554826 Mar 24 01:09:12 PM PDT 24 Mar 24 01:09:15 PM PDT 24 48925255 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2209916058 Mar 24 01:09:19 PM PDT 24 Mar 24 01:09:24 PM PDT 24 218217218 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.277485890 Mar 24 01:09:52 PM PDT 24 Mar 24 01:10:31 PM PDT 24 503975291 ps
T802 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1756565727 Mar 24 01:09:33 PM PDT 24 Mar 24 01:10:26 PM PDT 24 2721645598 ps
T803 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.646473862 Mar 24 01:09:18 PM PDT 24 Mar 24 01:09:30 PM PDT 24 362733678 ps
T804 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.170978430 Mar 24 01:09:23 PM PDT 24 Mar 24 01:09:36 PM PDT 24 89730068 ps
T805 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2255223529 Mar 24 01:09:39 PM PDT 24 Mar 24 01:09:44 PM PDT 24 33148810 ps
T806 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3087101207 Mar 24 01:09:42 PM PDT 24 Mar 24 01:09:47 PM PDT 24 70744123 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1317634934 Mar 24 01:09:12 PM PDT 24 Mar 24 01:09:14 PM PDT 24 15916774 ps
T808 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3165402215 Mar 24 01:09:43 PM PDT 24 Mar 24 01:09:44 PM PDT 24 28018974 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2584582312 Mar 24 01:09:18 PM PDT 24 Mar 24 01:12:49 PM PDT 24 1705184348 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1472967577 Mar 24 01:09:23 PM PDT 24 Mar 24 01:09:49 PM PDT 24 169644916 ps
T811 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2618984181 Mar 24 01:09:38 PM PDT 24 Mar 24 01:09:40 PM PDT 24 33573638 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1937014010 Mar 24 01:09:22 PM PDT 24 Mar 24 01:09:35 PM PDT 24 89895895 ps
T813 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1455267600 Mar 24 01:09:24 PM PDT 24 Mar 24 01:09:25 PM PDT 24 18752429 ps
T165 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1183936017 Mar 24 01:09:40 PM PDT 24 Mar 24 01:11:28 PM PDT 24 1761922978 ps
T814 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3543253653 Mar 24 01:10:00 PM PDT 24 Mar 24 01:10:01 PM PDT 24 12885138 ps
T815 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1297754800 Mar 24 01:09:29 PM PDT 24 Mar 24 01:18:23 PM PDT 24 7593123497 ps
T816 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2804886363 Mar 24 01:09:24 PM PDT 24 Mar 24 01:09:25 PM PDT 24 26589631 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2423325814 Mar 24 01:09:18 PM PDT 24 Mar 24 01:16:40 PM PDT 24 74532321109 ps
T818 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2994395466 Mar 24 01:09:17 PM PDT 24 Mar 24 01:11:32 PM PDT 24 2775366542 ps
T164 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3041988339 Mar 24 01:09:41 PM PDT 24 Mar 24 01:17:48 PM PDT 24 6396574018 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4221085314 Mar 24 01:09:38 PM PDT 24 Mar 24 01:09:44 PM PDT 24 35101000 ps
T175 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3665311833 Mar 24 01:09:18 PM PDT 24 Mar 24 01:09:21 PM PDT 24 247581614 ps
T820 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2677426853 Mar 24 01:09:35 PM PDT 24 Mar 24 01:09:38 PM PDT 24 37265064 ps
T162 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3859185095 Mar 24 01:09:24 PM PDT 24 Mar 24 01:15:05 PM PDT 24 10016631786 ps
T158 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.486193450 Mar 24 01:09:23 PM PDT 24 Mar 24 01:12:52 PM PDT 24 1672234586 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3809473144 Mar 24 01:09:20 PM PDT 24 Mar 24 01:09:24 PM PDT 24 22344958 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.156251991 Mar 24 01:09:42 PM PDT 24 Mar 24 01:09:57 PM PDT 24 217788974 ps
T823 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1973413297 Mar 24 01:09:16 PM PDT 24 Mar 24 01:09:18 PM PDT 24 9122069 ps
T824 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.835186725 Mar 24 01:09:46 PM PDT 24 Mar 24 01:09:56 PM PDT 24 718683495 ps
T825 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1202807985 Mar 24 01:09:39 PM PDT 24 Mar 24 01:10:01 PM PDT 24 653158507 ps
T826 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.908896045 Mar 24 01:09:47 PM PDT 24 Mar 24 01:10:08 PM PDT 24 530805174 ps
T827 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1271896844 Mar 24 01:09:20 PM PDT 24 Mar 24 01:09:26 PM PDT 24 47160237 ps

Test location /workspace/coverage/default/40.alert_handler_stress_all.2811414222
Short name T5
Test name
Test status
Simulation time 101586316351 ps
CPU time 1793.99 seconds
Started Mar 24 02:56:54 PM PDT 24
Finished Mar 24 03:26:48 PM PDT 24
Peak memory 281704 kb
Host smart-ad875f82-d483-4188-879e-92e07ff2cec7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811414222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2811414222
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.500516731
Short name T9
Test name
Test status
Simulation time 706898060 ps
CPU time 37.33 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 02:54:36 PM PDT 24
Peak memory 272284 kb
Host smart-0c102242-f049-4fc2-9ae8-d76e1b451c72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=500516731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.500516731
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2913955355
Short name T47
Test name
Test status
Simulation time 38489505995 ps
CPU time 2680.42 seconds
Started Mar 24 02:56:27 PM PDT 24
Finished Mar 24 03:41:08 PM PDT 24
Peak memory 289360 kb
Host smart-82e679f3-0316-41e6-8b7f-01ffb8f0a45f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913955355 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2913955355
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1402671060
Short name T24
Test name
Test status
Simulation time 179739786845 ps
CPU time 3283.85 seconds
Started Mar 24 02:56:23 PM PDT 24
Finished Mar 24 03:51:07 PM PDT 24
Peak memory 289208 kb
Host smart-40fac300-0c92-4977-9943-7a9a11639123
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402671060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1402671060
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2296181569
Short name T167
Test name
Test status
Simulation time 10985283042 ps
CPU time 71.69 seconds
Started Mar 24 01:09:30 PM PDT 24
Finished Mar 24 01:10:41 PM PDT 24
Peak memory 237980 kb
Host smart-ddd6d3ba-5527-4dac-adf3-72705dd7d99c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2296181569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2296181569
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3322666517
Short name T70
Test name
Test status
Simulation time 52765793389 ps
CPU time 3385.16 seconds
Started Mar 24 02:54:28 PM PDT 24
Finished Mar 24 03:50:53 PM PDT 24
Peak memory 289488 kb
Host smart-f2a94bfe-2c2e-44fc-ba4d-b9ed0b841c55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322666517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3322666517
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.143471369
Short name T13
Test name
Test status
Simulation time 13444839951 ps
CPU time 1214.29 seconds
Started Mar 24 02:55:19 PM PDT 24
Finished Mar 24 03:15:34 PM PDT 24
Peak memory 269428 kb
Host smart-39422d20-8984-4163-ba9b-bd8c66f348ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143471369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.143471369
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4025275361
Short name T134
Test name
Test status
Simulation time 8841995213 ps
CPU time 640.91 seconds
Started Mar 24 01:09:26 PM PDT 24
Finished Mar 24 01:20:07 PM PDT 24
Peak memory 265160 kb
Host smart-a83907da-29d1-44fc-b84e-8aa73e54d8f0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025275361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4025275361
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2004379119
Short name T109
Test name
Test status
Simulation time 79508487861 ps
CPU time 2635.49 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 03:38:14 PM PDT 24
Peak memory 281676 kb
Host smart-e2e01b78-54ff-4611-8724-ee41fc31299d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004379119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2004379119
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.4053558226
Short name T83
Test name
Test status
Simulation time 49935734949 ps
CPU time 3537.7 seconds
Started Mar 24 02:57:05 PM PDT 24
Finished Mar 24 03:56:04 PM PDT 24
Peak memory 297944 kb
Host smart-52418b7f-b258-4ba3-807e-82d26b8a50fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053558226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.4053558226
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3461043195
Short name T98
Test name
Test status
Simulation time 14953931466 ps
CPU time 1071.7 seconds
Started Mar 24 02:57:39 PM PDT 24
Finished Mar 24 03:15:31 PM PDT 24
Peak memory 282752 kb
Host smart-047f0452-7d0d-44f7-9bd9-22179ddaba39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461043195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3461043195
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3009593778
Short name T106
Test name
Test status
Simulation time 22244514210 ps
CPU time 2175.14 seconds
Started Mar 24 02:56:49 PM PDT 24
Finished Mar 24 03:33:04 PM PDT 24
Peak memory 298616 kb
Host smart-2ba2e260-6cbf-4af0-9326-3141358c5114
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009593778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3009593778
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.195211084
Short name T133
Test name
Test status
Simulation time 4353681173 ps
CPU time 292.18 seconds
Started Mar 24 01:09:38 PM PDT 24
Finished Mar 24 01:14:31 PM PDT 24
Peak memory 272692 kb
Host smart-d263a98d-1ebe-4881-b254-608d247f2fc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=195211084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.195211084
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1070331640
Short name T132
Test name
Test status
Simulation time 11590273900 ps
CPU time 592.67 seconds
Started Mar 24 01:09:29 PM PDT 24
Finished Mar 24 01:19:22 PM PDT 24
Peak memory 271280 kb
Host smart-b79cd1b7-55ce-4c6e-b5df-e1fb28212eed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070331640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1070331640
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1140406290
Short name T300
Test name
Test status
Simulation time 81076569025 ps
CPU time 4424.18 seconds
Started Mar 24 02:54:23 PM PDT 24
Finished Mar 24 04:08:08 PM PDT 24
Peak memory 313940 kb
Host smart-161a9729-eac4-4adb-867f-a061473695f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140406290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1140406290
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3387717361
Short name T45
Test name
Test status
Simulation time 28126187414 ps
CPU time 1883.52 seconds
Started Mar 24 02:53:56 PM PDT 24
Finished Mar 24 03:25:20 PM PDT 24
Peak memory 273504 kb
Host smart-87bed158-c815-41e8-b8c3-0418eddf74da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387717361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3387717361
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3638277412
Short name T649
Test name
Test status
Simulation time 33072598375 ps
CPU time 2666.14 seconds
Started Mar 24 02:54:38 PM PDT 24
Finished Mar 24 03:39:04 PM PDT 24
Peak memory 302636 kb
Host smart-6c6527bd-c4e9-4941-8e22-7049d5662002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638277412 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3638277412
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.415957661
Short name T157
Test name
Test status
Simulation time 5876470192 ps
CPU time 615.7 seconds
Started Mar 24 01:09:45 PM PDT 24
Finished Mar 24 01:20:01 PM PDT 24
Peak memory 265168 kb
Host smart-9d39f59b-2ef9-4c6f-b1d2-e6092f97f0c3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415957661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.415957661
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1537170393
Short name T6
Test name
Test status
Simulation time 9505103400 ps
CPU time 413.56 seconds
Started Mar 24 02:54:10 PM PDT 24
Finished Mar 24 03:01:04 PM PDT 24
Peak memory 248240 kb
Host smart-372db9b7-3962-4fe6-9326-d67aa19848cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537170393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1537170393
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1753889511
Short name T355
Test name
Test status
Simulation time 7526456 ps
CPU time 1.53 seconds
Started Mar 24 01:09:52 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 235760 kb
Host smart-1eb8cf50-036c-42be-ad7e-4b69a64ce429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1753889511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1753889511
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3666367712
Short name T137
Test name
Test status
Simulation time 8813428374 ps
CPU time 685.21 seconds
Started Mar 24 01:09:38 PM PDT 24
Finished Mar 24 01:21:03 PM PDT 24
Peak memory 265376 kb
Host smart-579e3546-5ecc-421c-b5aa-e899e92d134c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666367712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3666367712
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3073117922
Short name T324
Test name
Test status
Simulation time 43918451229 ps
CPU time 2446.21 seconds
Started Mar 24 02:56:25 PM PDT 24
Finished Mar 24 03:37:12 PM PDT 24
Peak memory 281656 kb
Host smart-9bcd317d-2ed6-420d-8e34-8dbe5c3e9675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073117922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3073117922
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1334759742
Short name T21
Test name
Test status
Simulation time 33845395825 ps
CPU time 2516.03 seconds
Started Mar 24 02:57:26 PM PDT 24
Finished Mar 24 03:39:23 PM PDT 24
Peak memory 287956 kb
Host smart-febac554-c506-4b13-bb7f-72257c36e6b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334759742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1334759742
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3505484948
Short name T79
Test name
Test status
Simulation time 65016726902 ps
CPU time 623.42 seconds
Started Mar 24 02:54:33 PM PDT 24
Finished Mar 24 03:04:56 PM PDT 24
Peak memory 247832 kb
Host smart-e153e591-8a3b-4935-af62-0c07828071ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505484948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3505484948
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.295348055
Short name T159
Test name
Test status
Simulation time 6412507943 ps
CPU time 355.56 seconds
Started Mar 24 01:09:30 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 265116 kb
Host smart-ac9a1e97-b969-4c9d-a1e7-c13022cc40ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=295348055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.295348055
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1166129605
Short name T347
Test name
Test status
Simulation time 178041415174 ps
CPU time 1702.22 seconds
Started Mar 24 02:54:02 PM PDT 24
Finished Mar 24 03:22:24 PM PDT 24
Peak memory 289880 kb
Host smart-515ecbec-9355-4536-a149-2edc5754a6c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166129605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1166129605
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1467832833
Short name T313
Test name
Test status
Simulation time 51919335770 ps
CPU time 530.94 seconds
Started Mar 24 02:57:39 PM PDT 24
Finished Mar 24 03:06:30 PM PDT 24
Peak memory 247872 kb
Host smart-20e3193e-e3fb-4035-b470-b7e9cd6c7373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467832833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1467832833
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2214579688
Short name T215
Test name
Test status
Simulation time 70071133138 ps
CPU time 4342.83 seconds
Started Mar 24 02:55:21 PM PDT 24
Finished Mar 24 04:07:46 PM PDT 24
Peak memory 337928 kb
Host smart-da756e5b-3d47-4c69-8bfd-7e3a2add0430
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214579688 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2214579688
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3859185095
Short name T162
Test name
Test status
Simulation time 10016631786 ps
CPU time 341.54 seconds
Started Mar 24 01:09:24 PM PDT 24
Finished Mar 24 01:15:05 PM PDT 24
Peak memory 270284 kb
Host smart-964a8dee-2271-46b2-b75b-3a2c9cbb4780
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3859185095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3859185095
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1308238689
Short name T77
Test name
Test status
Simulation time 200981036520 ps
CPU time 3687.4 seconds
Started Mar 24 02:55:58 PM PDT 24
Finished Mar 24 03:57:26 PM PDT 24
Peak memory 332404 kb
Host smart-16073fae-7a76-405d-8961-5f027a859fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308238689 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1308238689
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.844940175
Short name T335
Test name
Test status
Simulation time 70307679085 ps
CPU time 497.23 seconds
Started Mar 24 02:58:01 PM PDT 24
Finished Mar 24 03:06:19 PM PDT 24
Peak memory 248128 kb
Host smart-4d9892c9-dc5c-4ba6-8fc7-82d33a57cbac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844940175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.844940175
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3842596649
Short name T342
Test name
Test status
Simulation time 20702748879 ps
CPU time 1677.91 seconds
Started Mar 24 02:54:39 PM PDT 24
Finished Mar 24 03:22:37 PM PDT 24
Peak memory 289224 kb
Host smart-c656cb86-69b2-4eec-9ad3-4cd36fe16b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842596649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3842596649
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.489693993
Short name T150
Test name
Test status
Simulation time 19465058548 ps
CPU time 1175.65 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:28:47 PM PDT 24
Peak memory 265092 kb
Host smart-d90eb1d1-f09d-4153-a453-a09f61fa7cb3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489693993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.489693993
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.759181556
Short name T356
Test name
Test status
Simulation time 20375856 ps
CPU time 1.45 seconds
Started Mar 24 01:09:38 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 236588 kb
Host smart-8fedb56f-cff8-4c0b-8805-3a2224564848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=759181556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.759181556
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.190334612
Short name T241
Test name
Test status
Simulation time 46900999743 ps
CPU time 488.3 seconds
Started Mar 24 02:56:26 PM PDT 24
Finished Mar 24 03:04:34 PM PDT 24
Peak memory 247360 kb
Host smart-40757c1d-f1ca-46df-9afe-65051049054f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190334612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.190334612
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.55215858
Short name T130
Test name
Test status
Simulation time 3286628162 ps
CPU time 101.25 seconds
Started Mar 24 01:09:19 PM PDT 24
Finished Mar 24 01:11:01 PM PDT 24
Peak memory 266076 kb
Host smart-1576e0cc-3aac-447c-bd44-c16e0a0d4283
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=55215858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors
.55215858
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2731092679
Short name T700
Test name
Test status
Simulation time 52100017516 ps
CPU time 3138.04 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 03:46:41 PM PDT 24
Peak memory 289096 kb
Host smart-b5b0f1a2-fe1d-4432-ab52-167c2d01f082
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731092679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2731092679
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3661140046
Short name T307
Test name
Test status
Simulation time 68996307713 ps
CPU time 2372.17 seconds
Started Mar 24 02:55:12 PM PDT 24
Finished Mar 24 03:34:44 PM PDT 24
Peak memory 289596 kb
Host smart-724ada8a-eae2-434d-ba4c-1d242906fa7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661140046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3661140046
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1409024547
Short name T117
Test name
Test status
Simulation time 36307860338 ps
CPU time 3824.9 seconds
Started Mar 24 02:56:48 PM PDT 24
Finished Mar 24 04:00:34 PM PDT 24
Peak memory 305876 kb
Host smart-5fc4ce6a-d6f8-45de-a9f6-2848e849cb91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409024547 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1409024547
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.276160926
Short name T52
Test name
Test status
Simulation time 56502214156 ps
CPU time 3570.2 seconds
Started Mar 24 02:54:08 PM PDT 24
Finished Mar 24 03:53:39 PM PDT 24
Peak memory 305900 kb
Host smart-bdcb66f5-49c9-487c-bd83-9bb2f469d1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276160926 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.276160926
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1526294168
Short name T27
Test name
Test status
Simulation time 200846264136 ps
CPU time 3400.6 seconds
Started Mar 24 02:54:08 PM PDT 24
Finished Mar 24 03:50:49 PM PDT 24
Peak memory 305320 kb
Host smart-973c91ac-5436-440d-b6d3-9d38ac87055c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526294168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1526294168
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2311090772
Short name T144
Test name
Test status
Simulation time 12560655634 ps
CPU time 938.79 seconds
Started Mar 24 01:09:45 PM PDT 24
Finished Mar 24 01:25:24 PM PDT 24
Peak memory 265248 kb
Host smart-70e03b2f-bbbb-44d3-b9b1-463099f5228e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311090772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2311090772
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3761915976
Short name T174
Test name
Test status
Simulation time 1127830146 ps
CPU time 65.41 seconds
Started Mar 24 01:09:40 PM PDT 24
Finished Mar 24 01:10:45 PM PDT 24
Peak memory 236756 kb
Host smart-e091fda0-8aa4-4685-8538-1bb92bace1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3761915976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3761915976
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3602359942
Short name T147
Test name
Test status
Simulation time 10183861902 ps
CPU time 693.03 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:20:56 PM PDT 24
Peak memory 265176 kb
Host smart-989c59fe-7514-4171-a0cc-f342aa1e988f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602359942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3602359942
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1063970226
Short name T48
Test name
Test status
Simulation time 68364966222 ps
CPU time 4419.54 seconds
Started Mar 24 02:54:37 PM PDT 24
Finished Mar 24 04:08:18 PM PDT 24
Peak memory 297456 kb
Host smart-3e06a963-2d21-44ea-b8c9-590891e8d0de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063970226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1063970226
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.728222972
Short name T244
Test name
Test status
Simulation time 80503317634 ps
CPU time 2441.09 seconds
Started Mar 24 02:54:55 PM PDT 24
Finished Mar 24 03:35:36 PM PDT 24
Peak memory 272656 kb
Host smart-72c0c3e0-2776-4c7d-adbb-5b71491ea69a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728222972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.728222972
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2135417806
Short name T653
Test name
Test status
Simulation time 8177592885 ps
CPU time 178.67 seconds
Started Mar 24 02:55:04 PM PDT 24
Finished Mar 24 02:58:04 PM PDT 24
Peak memory 248304 kb
Host smart-e28bce74-ee9f-4a88-b16f-4cb3a1c3582e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135417806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2135417806
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.610977070
Short name T344
Test name
Test status
Simulation time 55675994923 ps
CPU time 2033.17 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 03:28:06 PM PDT 24
Peak memory 273408 kb
Host smart-1eb63c32-9581-4445-bab3-fedb3d6f1677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610977070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.610977070
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3414114924
Short name T20
Test name
Test status
Simulation time 940874730 ps
CPU time 57.5 seconds
Started Mar 24 02:55:38 PM PDT 24
Finished Mar 24 02:56:35 PM PDT 24
Peak memory 255544 kb
Host smart-415e94aa-3f02-4d5f-a3a8-b94638c2a5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34141
14924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3414114924
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1170946516
Short name T163
Test name
Test status
Simulation time 1730027467 ps
CPU time 213.55 seconds
Started Mar 24 01:09:25 PM PDT 24
Finished Mar 24 01:12:59 PM PDT 24
Peak memory 271056 kb
Host smart-98be3d9f-73b3-4132-aa36-111af17fd0cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1170946516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1170946516
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3665311833
Short name T175
Test name
Test status
Simulation time 247581614 ps
CPU time 3.84 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 236664 kb
Host smart-c1076372-68de-473c-9ad3-68c9012a6dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3665311833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3665311833
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3051214036
Short name T222
Test name
Test status
Simulation time 378981649 ps
CPU time 3.13 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 02:53:49 PM PDT 24
Peak memory 249120 kb
Host smart-b5f89bb0-1f24-459a-832d-503ab72f2c3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3051214036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3051214036
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3589318598
Short name T226
Test name
Test status
Simulation time 14559607 ps
CPU time 2.57 seconds
Started Mar 24 02:53:54 PM PDT 24
Finished Mar 24 02:53:57 PM PDT 24
Peak memory 249056 kb
Host smart-ad72bdcd-3747-4be5-bb67-f10be11a8530
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3589318598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3589318598
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2604853609
Short name T224
Test name
Test status
Simulation time 32984047 ps
CPU time 2.97 seconds
Started Mar 24 02:54:27 PM PDT 24
Finished Mar 24 02:54:31 PM PDT 24
Peak memory 249144 kb
Host smart-17580037-facd-4e61-93c1-099351633abc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2604853609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2604853609
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2586055958
Short name T228
Test name
Test status
Simulation time 140500848 ps
CPU time 3.45 seconds
Started Mar 24 02:54:34 PM PDT 24
Finished Mar 24 02:54:38 PM PDT 24
Peak memory 249092 kb
Host smart-6d2056e0-2e44-410e-9042-a055ede9bd82
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2586055958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2586055958
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1672036890
Short name T283
Test name
Test status
Simulation time 198862316743 ps
CPU time 3682.29 seconds
Started Mar 24 02:54:31 PM PDT 24
Finished Mar 24 03:55:54 PM PDT 24
Peak memory 302832 kb
Host smart-5d0d9491-37a0-4a1c-b98d-1a8a71f43cdb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672036890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1672036890
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3193003205
Short name T194
Test name
Test status
Simulation time 294672649 ps
CPU time 16.31 seconds
Started Mar 24 02:54:41 PM PDT 24
Finished Mar 24 02:54:57 PM PDT 24
Peak memory 248820 kb
Host smart-1929720d-1756-4683-bb99-a4217359672f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31930
03205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3193003205
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2547674053
Short name T305
Test name
Test status
Simulation time 44845892149 ps
CPU time 2729.46 seconds
Started Mar 24 02:54:56 PM PDT 24
Finished Mar 24 03:40:26 PM PDT 24
Peak memory 289840 kb
Host smart-eaf140f4-1bef-4f0b-a202-884c6709dd52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547674053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2547674053
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.363195700
Short name T278
Test name
Test status
Simulation time 193261854793 ps
CPU time 3813.11 seconds
Started Mar 24 02:55:05 PM PDT 24
Finished Mar 24 03:58:39 PM PDT 24
Peak memory 305900 kb
Host smart-0be9bf44-7720-47b3-96ae-f5b32e05d5ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363195700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.363195700
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3102096271
Short name T635
Test name
Test status
Simulation time 228855754614 ps
CPU time 593.65 seconds
Started Mar 24 02:55:14 PM PDT 24
Finished Mar 24 03:05:08 PM PDT 24
Peak memory 247940 kb
Host smart-7289d464-b40d-40f9-a46f-b26b33bb9108
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102096271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3102096271
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.273153872
Short name T193
Test name
Test status
Simulation time 35925863048 ps
CPU time 4109.51 seconds
Started Mar 24 02:54:31 PM PDT 24
Finished Mar 24 04:03:02 PM PDT 24
Peak memory 338276 kb
Host smart-d70b9f74-c673-4e51-8a61-4cd18fbf186a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273153872 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.273153872
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4144819183
Short name T145
Test name
Test status
Simulation time 7229141871 ps
CPU time 212.71 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:13:19 PM PDT 24
Peak memory 266108 kb
Host smart-a4db291e-66b9-42d9-b34a-75d4a4b7b181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4144819183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.4144819183
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1183936017
Short name T165
Test name
Test status
Simulation time 1761922978 ps
CPU time 108.17 seconds
Started Mar 24 01:09:40 PM PDT 24
Finished Mar 24 01:11:28 PM PDT 24
Peak memory 265676 kb
Host smart-cc509231-cf9a-4ddd-8e51-a44dd651da4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1183936017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1183936017
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2878035243
Short name T131
Test name
Test status
Simulation time 3474684216 ps
CPU time 191.98 seconds
Started Mar 24 01:09:10 PM PDT 24
Finished Mar 24 01:12:22 PM PDT 24
Peak memory 265304 kb
Host smart-ea814fce-ae87-46aa-9d0e-d128bcd3138f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2878035243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2878035243
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2481340205
Short name T769
Test name
Test status
Simulation time 9875685 ps
CPU time 1.2 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:13 PM PDT 24
Peak memory 234752 kb
Host smart-ea386697-7850-44ca-809d-62c972904924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2481340205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2481340205
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.410955313
Short name T352
Test name
Test status
Simulation time 43153655362 ps
CPU time 2793.44 seconds
Started Mar 24 02:54:32 PM PDT 24
Finished Mar 24 03:41:06 PM PDT 24
Peak memory 289064 kb
Host smart-86ff7238-6bee-463f-bbf8-6bcb076834c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410955313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.410955313
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2860322098
Short name T36
Test name
Test status
Simulation time 67049222603 ps
CPU time 5369.66 seconds
Started Mar 24 02:54:56 PM PDT 24
Finished Mar 24 04:24:26 PM PDT 24
Peak memory 331948 kb
Host smart-be1fc299-cdbe-46cc-aeb1-7bf2d218cdf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860322098 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2860322098
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1000702227
Short name T555
Test name
Test status
Simulation time 41022284552 ps
CPU time 2621.05 seconds
Started Mar 24 02:55:01 PM PDT 24
Finished Mar 24 03:38:42 PM PDT 24
Peak memory 289428 kb
Host smart-e9a30550-e940-484e-b846-0031ba93cfca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000702227 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1000702227
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2900848175
Short name T297
Test name
Test status
Simulation time 2372112325 ps
CPU time 75.18 seconds
Started Mar 24 02:53:53 PM PDT 24
Finished Mar 24 02:55:08 PM PDT 24
Peak memory 256888 kb
Host smart-b01a7ddc-9d98-4903-a4a2-a7cd7716298d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900848175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2900848175
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2308377038
Short name T111
Test name
Test status
Simulation time 16363879965 ps
CPU time 691.11 seconds
Started Mar 24 02:55:03 PM PDT 24
Finished Mar 24 03:06:35 PM PDT 24
Peak memory 265388 kb
Host smart-7ced7504-8acd-4d77-851f-7a6a56d72703
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308377038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2308377038
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3837078411
Short name T285
Test name
Test status
Simulation time 3473906737 ps
CPU time 56.36 seconds
Started Mar 24 02:55:06 PM PDT 24
Finished Mar 24 02:56:02 PM PDT 24
Peak memory 248920 kb
Host smart-379fa5b6-951c-4e63-a9c4-5c242635b9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38370
78411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3837078411
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.649142871
Short name T281
Test name
Test status
Simulation time 770527061 ps
CPU time 52.09 seconds
Started Mar 24 02:55:05 PM PDT 24
Finished Mar 24 02:55:57 PM PDT 24
Peak memory 254840 kb
Host smart-d8483206-ee5e-4894-ad59-fdb418e6e21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64914
2871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.649142871
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2191604892
Short name T315
Test name
Test status
Simulation time 14945236454 ps
CPU time 603.41 seconds
Started Mar 24 02:55:37 PM PDT 24
Finished Mar 24 03:05:41 PM PDT 24
Peak memory 247056 kb
Host smart-3639989f-9209-4345-b908-cbfe29120ef7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191604892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2191604892
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2710626928
Short name T38
Test name
Test status
Simulation time 32699824638 ps
CPU time 864.79 seconds
Started Mar 24 02:57:03 PM PDT 24
Finished Mar 24 03:11:28 PM PDT 24
Peak memory 272764 kb
Host smart-f8fc9ecf-6691-446f-91b1-785d09ec2f42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710626928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2710626928
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3726842991
Short name T115
Test name
Test status
Simulation time 108885101740 ps
CPU time 4054.99 seconds
Started Mar 24 02:57:52 PM PDT 24
Finished Mar 24 04:05:28 PM PDT 24
Peak memory 297456 kb
Host smart-b0a7fc7e-7d82-48c7-a938-7c00590ed1ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726842991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3726842991
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2172864648
Short name T176
Test name
Test status
Simulation time 3615256015 ps
CPU time 41.98 seconds
Started Mar 24 01:09:44 PM PDT 24
Finished Mar 24 01:10:26 PM PDT 24
Peak memory 237896 kb
Host smart-4135f14d-e743-41b5-8872-1d699ed28bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2172864648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2172864648
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3733567666
Short name T172
Test name
Test status
Simulation time 95167154 ps
CPU time 3.97 seconds
Started Mar 24 01:09:27 PM PDT 24
Finished Mar 24 01:09:31 PM PDT 24
Peak memory 236588 kb
Host smart-03c419da-c6a9-4929-9afb-7269c6a7d18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3733567666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3733567666
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1210554826
Short name T182
Test name
Test status
Simulation time 48925255 ps
CPU time 2.63 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:15 PM PDT 24
Peak memory 236636 kb
Host smart-a165ec66-12a6-44d1-97f0-09be0bffdd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1210554826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1210554826
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2967893870
Short name T148
Test name
Test status
Simulation time 32017090279 ps
CPU time 575.01 seconds
Started Mar 24 01:09:13 PM PDT 24
Finished Mar 24 01:18:49 PM PDT 24
Peak memory 269088 kb
Host smart-6a1e739b-59de-4801-994c-a9ce39c8ba42
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967893870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2967893870
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3550317390
Short name T151
Test name
Test status
Simulation time 2161305345 ps
CPU time 143.76 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:11:52 PM PDT 24
Peak memory 256952 kb
Host smart-70085fd3-4758-4a19-a738-998e8a073b43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3550317390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3550317390
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.11702781
Short name T180
Test name
Test status
Simulation time 40716199 ps
CPU time 3.43 seconds
Started Mar 24 01:09:41 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 237012 kb
Host smart-8e4c588b-4116-4ef0-9a08-2a87ffbc67a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=11702781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.11702781
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3678078802
Short name T178
Test name
Test status
Simulation time 659754761 ps
CPU time 42.05 seconds
Started Mar 24 01:09:37 PM PDT 24
Finished Mar 24 01:10:20 PM PDT 24
Peak memory 245080 kb
Host smart-9addb343-647a-4f8d-8094-e7d6d81b53d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3678078802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3678078802
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2582310316
Short name T168
Test name
Test status
Simulation time 37322399 ps
CPU time 3.26 seconds
Started Mar 24 01:09:40 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 235704 kb
Host smart-883ac747-d997-4bd4-b4e4-e560f1c8d79c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2582310316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2582310316
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3856423575
Short name T155
Test name
Test status
Simulation time 9550594525 ps
CPU time 296.19 seconds
Started Mar 24 01:09:48 PM PDT 24
Finished Mar 24 01:14:44 PM PDT 24
Peak memory 269568 kb
Host smart-5a500dc8-89fc-4078-b0f0-2df55a0ee5ad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856423575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3856423575
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2011773307
Short name T183
Test name
Test status
Simulation time 99584310 ps
CPU time 4.88 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:09:16 PM PDT 24
Peak memory 237624 kb
Host smart-c182498b-dcc1-4b1d-b7d1-3e44bf9ce232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2011773307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2011773307
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1618126409
Short name T181
Test name
Test status
Simulation time 477777867 ps
CPU time 36.96 seconds
Started Mar 24 01:09:33 PM PDT 24
Finished Mar 24 01:10:11 PM PDT 24
Peak memory 239476 kb
Host smart-a20c2bb8-b7c6-4c84-8fcd-0a01a71b7b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1618126409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1618126409
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3759297953
Short name T184
Test name
Test status
Simulation time 35841361 ps
CPU time 3.08 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:49 PM PDT 24
Peak memory 236972 kb
Host smart-d5bf4425-2530-47ae-8ad0-a8fd9131c9ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3759297953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3759297953
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.407374291
Short name T185
Test name
Test status
Simulation time 459869303 ps
CPU time 38.45 seconds
Started Mar 24 01:09:47 PM PDT 24
Finished Mar 24 01:10:25 PM PDT 24
Peak memory 240348 kb
Host smart-2e1e32df-d065-4902-b087-562760b61850
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=407374291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.407374291
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2135693163
Short name T177
Test name
Test status
Simulation time 5156460483 ps
CPU time 83.27 seconds
Started Mar 24 01:09:50 PM PDT 24
Finished Mar 24 01:11:13 PM PDT 24
Peak memory 240424 kb
Host smart-7bf671df-f05c-4c4b-9294-2f84ad28ebf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2135693163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2135693163
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4048428481
Short name T166
Test name
Test status
Simulation time 1256449396 ps
CPU time 42 seconds
Started Mar 24 01:09:15 PM PDT 24
Finished Mar 24 01:09:58 PM PDT 24
Peak memory 240204 kb
Host smart-00868b1a-e58f-4e49-9749-6d8464e2ad13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4048428481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4048428481
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3997925341
Short name T187
Test name
Test status
Simulation time 106515690 ps
CPU time 5.73 seconds
Started Mar 24 01:09:20 PM PDT 24
Finished Mar 24 01:09:26 PM PDT 24
Peak memory 236632 kb
Host smart-a6e6c0b9-0e62-4dab-a1b7-5383f719b0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3997925341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3997925341
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.43107762
Short name T188
Test name
Test status
Simulation time 190271974 ps
CPU time 3.6 seconds
Started Mar 24 01:09:24 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 237092 kb
Host smart-55563aba-e399-4e28-a789-caacb70ca025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=43107762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.43107762
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1956245677
Short name T179
Test name
Test status
Simulation time 97061603 ps
CPU time 2.76 seconds
Started Mar 24 01:09:25 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 237144 kb
Host smart-35c2e950-0cde-471d-bf58-325733ace2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1956245677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1956245677
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2834498775
Short name T173
Test name
Test status
Simulation time 156545361 ps
CPU time 21.92 seconds
Started Mar 24 01:09:29 PM PDT 24
Finished Mar 24 01:09:52 PM PDT 24
Peak memory 239400 kb
Host smart-ea39f4f1-9ba9-4a97-b5d5-5decb3d5abd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2834498775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2834498775
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.813815467
Short name T760
Test name
Test status
Simulation time 547984637 ps
CPU time 67.57 seconds
Started Mar 24 01:09:14 PM PDT 24
Finished Mar 24 01:10:22 PM PDT 24
Peak memory 236428 kb
Host smart-128b3a5e-fc1c-4307-806b-560b02bfb132
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=813815467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.813815467
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.722144950
Short name T792
Test name
Test status
Simulation time 1637782074 ps
CPU time 168.08 seconds
Started Mar 24 01:09:19 PM PDT 24
Finished Mar 24 01:12:07 PM PDT 24
Peak memory 235624 kb
Host smart-b789ac9a-771a-4261-b442-cc1fe4a0ee01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=722144950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.722144950
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2259053915
Short name T709
Test name
Test status
Simulation time 392132949 ps
CPU time 8.28 seconds
Started Mar 24 01:09:13 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 240204 kb
Host smart-beb99a34-8aab-42b8-bfd7-c2de1ba42d24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2259053915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2259053915
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3378159214
Short name T265
Test name
Test status
Simulation time 272128559 ps
CPU time 10.01 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:09:21 PM PDT 24
Peak memory 238808 kb
Host smart-04eb8bf0-2556-434c-9a58-1b8f676b649e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378159214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3378159214
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1195737584
Short name T202
Test name
Test status
Simulation time 1025868154 ps
CPU time 9.48 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:22 PM PDT 24
Peak memory 236600 kb
Host smart-30cf2738-2068-4e9b-ab51-3793c04c6ff5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1195737584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1195737584
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1317634934
Short name T807
Test name
Test status
Simulation time 15916774 ps
CPU time 1.8 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:14 PM PDT 24
Peak memory 236628 kb
Host smart-1b91ccdc-f9c3-43ac-acd1-9b9d6d26fbd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1317634934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1317634934
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3464976484
Short name T733
Test name
Test status
Simulation time 375190046 ps
CPU time 15.53 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 244808 kb
Host smart-d6f76e46-132c-4ccb-a1fe-a78f03e1f729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3464976484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3464976484
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3340627255
Short name T707
Test name
Test status
Simulation time 58914981 ps
CPU time 7.59 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:09:18 PM PDT 24
Peak memory 246944 kb
Host smart-6caf9a28-746d-439c-97bf-20ca679d108f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3340627255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3340627255
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1568153628
Short name T205
Test name
Test status
Simulation time 6796457012 ps
CPU time 121.76 seconds
Started Mar 24 01:09:13 PM PDT 24
Finished Mar 24 01:11:15 PM PDT 24
Peak memory 236832 kb
Host smart-cb850ac0-19ef-4d3a-b544-7137c063e40c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1568153628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1568153628
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1527283496
Short name T785
Test name
Test status
Simulation time 6281940227 ps
CPU time 118.07 seconds
Started Mar 24 01:09:13 PM PDT 24
Finished Mar 24 01:11:11 PM PDT 24
Peak memory 236696 kb
Host smart-fb7af745-04bd-40a4-bb8c-535a25021d5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1527283496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1527283496
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4253903218
Short name T764
Test name
Test status
Simulation time 194716199 ps
CPU time 8.48 seconds
Started Mar 24 01:09:19 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 240172 kb
Host smart-20d0c863-7d99-4c57-b20f-536248dec1f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4253903218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4253903218
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3847503244
Short name T724
Test name
Test status
Simulation time 102490001 ps
CPU time 8.25 seconds
Started Mar 24 01:09:12 PM PDT 24
Finished Mar 24 01:09:20 PM PDT 24
Peak memory 239244 kb
Host smart-5789c5c2-c51d-4090-99a3-6c2d0baf9aad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847503244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3847503244
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1357087598
Short name T740
Test name
Test status
Simulation time 807760990 ps
CPU time 7.08 seconds
Started Mar 24 01:09:15 PM PDT 24
Finished Mar 24 01:09:23 PM PDT 24
Peak memory 235692 kb
Host smart-da43d7ba-26aa-4326-ab7c-a6927ed85529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1357087598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1357087598
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.101862941
Short name T756
Test name
Test status
Simulation time 673313368 ps
CPU time 19.22 seconds
Started Mar 24 01:09:13 PM PDT 24
Finished Mar 24 01:09:32 PM PDT 24
Peak memory 248700 kb
Host smart-43d53881-db8f-4121-ab58-7e180ae222a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=101862941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.101862941
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.681789534
Short name T161
Test name
Test status
Simulation time 864414606 ps
CPU time 100.31 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:10:52 PM PDT 24
Peak memory 265136 kb
Host smart-819a8947-8bd6-463e-8160-5f4cce938185
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681789534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.681789534
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2209916058
Short name T800
Test name
Test status
Simulation time 218217218 ps
CPU time 5.09 seconds
Started Mar 24 01:09:19 PM PDT 24
Finished Mar 24 01:09:24 PM PDT 24
Peak memory 240372 kb
Host smart-a0f22660-21ff-4f1b-8103-6403b95a5e96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2209916058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2209916058
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.572804651
Short name T736
Test name
Test status
Simulation time 193911690 ps
CPU time 9.08 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 238808 kb
Host smart-43649935-51ba-456e-848f-621148171cc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572804651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.572804651
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1741575051
Short name T725
Test name
Test status
Simulation time 904295850 ps
CPU time 5.36 seconds
Started Mar 24 01:09:29 PM PDT 24
Finished Mar 24 01:09:34 PM PDT 24
Peak memory 236432 kb
Host smart-e7186530-8fbf-49e2-a5f2-e2847e7584dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1741575051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1741575051
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4037144034
Short name T784
Test name
Test status
Simulation time 19014168 ps
CPU time 1.87 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:31 PM PDT 24
Peak memory 234984 kb
Host smart-aa7a8290-e270-45e1-a00e-c9eeb8681be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4037144034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4037144034
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1756565727
Short name T802
Test name
Test status
Simulation time 2721645598 ps
CPU time 52.53 seconds
Started Mar 24 01:09:33 PM PDT 24
Finished Mar 24 01:10:26 PM PDT 24
Peak memory 248600 kb
Host smart-d1a65207-1351-4810-992b-8779c1d732cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1756565727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1756565727
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3652273499
Short name T712
Test name
Test status
Simulation time 384597660 ps
CPU time 15.76 seconds
Started Mar 24 01:09:29 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 248276 kb
Host smart-109ddb48-4222-47dc-8223-01bd30145902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3652273499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3652273499
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1188869415
Short name T754
Test name
Test status
Simulation time 209339049 ps
CPU time 6.01 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 240324 kb
Host smart-d02c1b97-6fd5-4137-878c-78783384f158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188869415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1188869415
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1075406109
Short name T782
Test name
Test status
Simulation time 2072633807 ps
CPU time 7.55 seconds
Started Mar 24 01:09:37 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 235608 kb
Host smart-f9267271-2a6c-4482-9ba1-e9df6ee1a6cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1075406109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1075406109
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1477596498
Short name T201
Test name
Test status
Simulation time 173063772 ps
CPU time 14.38 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 244816 kb
Host smart-4c5497c7-2413-4304-9065-b59691f609dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1477596498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1477596498
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1495028201
Short name T153
Test name
Test status
Simulation time 2888526329 ps
CPU time 163.76 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:12:23 PM PDT 24
Peak memory 265128 kb
Host smart-f8bbcd7b-dcff-4bfd-b2c4-958424a2393e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1495028201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1495028201
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.237083680
Short name T706
Test name
Test status
Simulation time 495507538 ps
CPU time 9.95 seconds
Started Mar 24 01:09:41 PM PDT 24
Finished Mar 24 01:09:51 PM PDT 24
Peak memory 248128 kb
Host smart-6efd6de5-83d8-4630-b10d-62971dea044d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237083680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.237083680
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2677426853
Short name T820
Test name
Test status
Simulation time 37265064 ps
CPU time 2.45 seconds
Started Mar 24 01:09:35 PM PDT 24
Finished Mar 24 01:09:38 PM PDT 24
Peak memory 237112 kb
Host smart-498f66bd-c502-40a4-9c42-503db3b0d175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2677426853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2677426853
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3845650336
Short name T218
Test name
Test status
Simulation time 262637681 ps
CPU time 4.84 seconds
Started Mar 24 01:09:40 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 237112 kb
Host smart-14b44f36-d175-413d-9625-651c0de8776b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845650336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3845650336
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3831076300
Short name T364
Test name
Test status
Simulation time 436074145 ps
CPU time 7.91 seconds
Started Mar 24 01:09:37 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 240224 kb
Host smart-59f95387-61b6-422e-a378-1e28e685443d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3831076300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3831076300
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2618984181
Short name T811
Test name
Test status
Simulation time 33573638 ps
CPU time 1.42 seconds
Started Mar 24 01:09:38 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 236672 kb
Host smart-2499d8aa-fb08-46ee-9a9b-59cfb856d1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2618984181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2618984181
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1202807985
Short name T825
Test name
Test status
Simulation time 653158507 ps
CPU time 21.77 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 240336 kb
Host smart-5d0b1069-88fb-4a12-8756-e7df6109b511
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1202807985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1202807985
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.316356457
Short name T154
Test name
Test status
Simulation time 22962461134 ps
CPU time 656.36 seconds
Started Mar 24 01:09:40 PM PDT 24
Finished Mar 24 01:20:36 PM PDT 24
Peak memory 265128 kb
Host smart-abc3e688-067d-4993-ac12-74f9080dfdec
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316356457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.316356457
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4221085314
Short name T819
Test name
Test status
Simulation time 35101000 ps
CPU time 5.53 seconds
Started Mar 24 01:09:38 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 248104 kb
Host smart-19ab880e-5370-49d0-b1df-f24627e5c3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4221085314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4221085314
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.156251991
Short name T822
Test name
Test status
Simulation time 217788974 ps
CPU time 15.1 seconds
Started Mar 24 01:09:42 PM PDT 24
Finished Mar 24 01:09:57 PM PDT 24
Peak memory 250800 kb
Host smart-c73ea960-564b-42a8-a38c-e860332d60ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156251991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.156251991
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2255223529
Short name T805
Test name
Test status
Simulation time 33148810 ps
CPU time 5.77 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 240280 kb
Host smart-c95132e9-1449-4ebe-888e-f6e7df7bf5b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2255223529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2255223529
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.87368238
Short name T741
Test name
Test status
Simulation time 10146517 ps
CPU time 1.46 seconds
Started Mar 24 01:09:40 PM PDT 24
Finished Mar 24 01:09:42 PM PDT 24
Peak memory 236672 kb
Host smart-3b8319b2-fe07-4397-b7c0-0ff68c9269d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=87368238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.87368238
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4189867781
Short name T789
Test name
Test status
Simulation time 1069697916 ps
CPU time 20.54 seconds
Started Mar 24 01:09:43 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 244860 kb
Host smart-428cf268-c42e-43ad-ab38-64ba8d026b19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4189867781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4189867781
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2221379180
Short name T363
Test name
Test status
Simulation time 24705511592 ps
CPU time 503.97 seconds
Started Mar 24 01:09:37 PM PDT 24
Finished Mar 24 01:18:01 PM PDT 24
Peak memory 266204 kb
Host smart-4bb85665-fe48-4581-b276-0032ca824a88
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221379180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2221379180
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3167215194
Short name T779
Test name
Test status
Simulation time 81036191 ps
CPU time 10.93 seconds
Started Mar 24 01:09:38 PM PDT 24
Finished Mar 24 01:09:49 PM PDT 24
Peak memory 248680 kb
Host smart-fc97694e-b1a7-4d2b-8006-b825bf9f40df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167215194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3167215194
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3726758914
Short name T745
Test name
Test status
Simulation time 217909562 ps
CPU time 8.15 seconds
Started Mar 24 01:09:41 PM PDT 24
Finished Mar 24 01:09:49 PM PDT 24
Peak memory 248536 kb
Host smart-0719292a-6236-4ac8-b8a0-a5b74fba0a0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726758914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3726758914
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3796860293
Short name T773
Test name
Test status
Simulation time 119797096 ps
CPU time 5.53 seconds
Started Mar 24 01:09:43 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 240264 kb
Host smart-247bf1e1-de37-4c2d-a869-8e0aaecef544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3796860293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3796860293
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3165402215
Short name T808
Test name
Test status
Simulation time 28018974 ps
CPU time 1.68 seconds
Started Mar 24 01:09:43 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 235940 kb
Host smart-a06feff1-f1b0-4468-9fd7-e371fcc9dd87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3165402215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3165402215
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.669844964
Short name T734
Test name
Test status
Simulation time 670788347 ps
CPU time 11.98 seconds
Started Mar 24 01:09:41 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 244860 kb
Host smart-2791ecdb-ef30-454f-a95a-f30b0e7ae6fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=669844964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.669844964
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3769899642
Short name T136
Test name
Test status
Simulation time 767083087 ps
CPU time 87.33 seconds
Started Mar 24 01:09:39 PM PDT 24
Finished Mar 24 01:11:06 PM PDT 24
Peak memory 256576 kb
Host smart-fd363a3e-5aee-41b7-b5c4-4646af776866
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3769899642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3769899642
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1814040171
Short name T143
Test name
Test status
Simulation time 4894101520 ps
CPU time 684.79 seconds
Started Mar 24 01:09:43 PM PDT 24
Finished Mar 24 01:21:08 PM PDT 24
Peak memory 265316 kb
Host smart-858464de-9206-44d6-a648-c0e3c42dc92f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814040171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1814040171
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1885023799
Short name T735
Test name
Test status
Simulation time 235658852 ps
CPU time 18.02 seconds
Started Mar 24 01:09:44 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 248588 kb
Host smart-975e23c7-0350-428f-876c-cf12d19aef47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885023799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1885023799
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3087101207
Short name T806
Test name
Test status
Simulation time 70744123 ps
CPU time 4.93 seconds
Started Mar 24 01:09:42 PM PDT 24
Finished Mar 24 01:09:47 PM PDT 24
Peak memory 240408 kb
Host smart-9ea4b2bf-8495-4265-93e2-c6be314d63ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087101207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3087101207
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1281589827
Short name T186
Test name
Test status
Simulation time 20141516 ps
CPU time 3.38 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:49 PM PDT 24
Peak memory 239548 kb
Host smart-acd9c378-175a-486e-9ab5-64028cec3d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1281589827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1281589827
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2164477109
Short name T791
Test name
Test status
Simulation time 9292410 ps
CPU time 1.58 seconds
Started Mar 24 01:09:41 PM PDT 24
Finished Mar 24 01:09:43 PM PDT 24
Peak memory 235824 kb
Host smart-f3a9f903-5f9e-4bc0-a362-69a52fbdf3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2164477109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2164477109
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2938981440
Short name T204
Test name
Test status
Simulation time 973736180 ps
CPU time 20.13 seconds
Started Mar 24 01:09:44 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 243972 kb
Host smart-c0817c3a-c83c-43d3-b102-4fa33547173d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2938981440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2938981440
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.835186725
Short name T824
Test name
Test status
Simulation time 718683495 ps
CPU time 10.32 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:56 PM PDT 24
Peak memory 248172 kb
Host smart-94f1c8b4-74ac-4d21-95c6-9485e17de582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=835186725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.835186725
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1437001845
Short name T362
Test name
Test status
Simulation time 132440768 ps
CPU time 10.2 seconds
Started Mar 24 01:09:44 PM PDT 24
Finished Mar 24 01:09:55 PM PDT 24
Peak memory 252396 kb
Host smart-7cbf5f79-7c24-493d-ba00-f969b2ae7ee2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437001845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1437001845
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3793661728
Short name T794
Test name
Test status
Simulation time 69060231 ps
CPU time 5.51 seconds
Started Mar 24 01:09:42 PM PDT 24
Finished Mar 24 01:09:47 PM PDT 24
Peak memory 236612 kb
Host smart-18c6c35e-f46d-4abc-86b9-96c577c37e50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3793661728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3793661728
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1085715571
Short name T777
Test name
Test status
Simulation time 8049309 ps
CPU time 1.29 seconds
Started Mar 24 01:09:42 PM PDT 24
Finished Mar 24 01:09:43 PM PDT 24
Peak memory 236676 kb
Host smart-3000cae3-7029-49f8-992b-7a551be5baf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1085715571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1085715571
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3030014678
Short name T203
Test name
Test status
Simulation time 5461638631 ps
CPU time 46.14 seconds
Started Mar 24 01:09:42 PM PDT 24
Finished Mar 24 01:10:29 PM PDT 24
Peak memory 244924 kb
Host smart-a3a4989d-6845-46bb-a951-31f94702dfbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3030014678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3030014678
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2782063874
Short name T146
Test name
Test status
Simulation time 2042343276 ps
CPU time 192.1 seconds
Started Mar 24 01:09:44 PM PDT 24
Finished Mar 24 01:12:56 PM PDT 24
Peak memory 268716 kb
Host smart-154514d0-3823-4608-ae45-899eab44400a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2782063874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2782063874
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1058963987
Short name T798
Test name
Test status
Simulation time 179295342 ps
CPU time 6.08 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:52 PM PDT 24
Peak memory 247184 kb
Host smart-ce22d4dd-1295-4bc1-b1e1-66412f34255a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1058963987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1058963987
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1515752032
Short name T778
Test name
Test status
Simulation time 120583287 ps
CPU time 5.59 seconds
Started Mar 24 01:09:48 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 239408 kb
Host smart-2e3ba725-2f1d-4633-939e-3dca1dca5f53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515752032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1515752032
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2811104018
Short name T787
Test name
Test status
Simulation time 20530463 ps
CPU time 3.75 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:50 PM PDT 24
Peak memory 240148 kb
Host smart-08cf4f35-c7c1-41d4-bcfe-58abadbefa2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2811104018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2811104018
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2717251347
Short name T796
Test name
Test status
Simulation time 18617224 ps
CPU time 1.38 seconds
Started Mar 24 01:09:49 PM PDT 24
Finished Mar 24 01:09:51 PM PDT 24
Peak memory 236632 kb
Host smart-3432bb32-7e65-42a2-acbf-3a35f43ed151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2717251347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2717251347
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.908896045
Short name T826
Test name
Test status
Simulation time 530805174 ps
CPU time 21.04 seconds
Started Mar 24 01:09:47 PM PDT 24
Finished Mar 24 01:10:08 PM PDT 24
Peak memory 248552 kb
Host smart-f6a327c5-1973-45c9-9ba7-039b884907b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=908896045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.908896045
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1932751832
Short name T139
Test name
Test status
Simulation time 780305178 ps
CPU time 96.89 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:11:23 PM PDT 24
Peak memory 263280 kb
Host smart-9c61e942-1f08-4fc1-bcc9-428158603a92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1932751832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1932751832
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3041988339
Short name T164
Test name
Test status
Simulation time 6396574018 ps
CPU time 487.02 seconds
Started Mar 24 01:09:41 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 273276 kb
Host smart-06015a73-be04-43b9-920e-8bedc481f371
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041988339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3041988339
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2782135994
Short name T715
Test name
Test status
Simulation time 68874866 ps
CPU time 9.86 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:56 PM PDT 24
Peak memory 246976 kb
Host smart-d6fd74f7-05a3-4013-8528-551484f1fea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2782135994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2782135994
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1549648038
Short name T714
Test name
Test status
Simulation time 864660606 ps
CPU time 13.48 seconds
Started Mar 24 01:09:50 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 255400 kb
Host smart-0abc00b7-0d90-4e3a-8837-175ff8a5f89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549648038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1549648038
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.4153949435
Short name T768
Test name
Test status
Simulation time 408029499 ps
CPU time 8.13 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:54 PM PDT 24
Peak memory 240236 kb
Host smart-3303b844-0cfd-4730-9866-0e2866c8cb60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4153949435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4153949435
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2680150100
Short name T753
Test name
Test status
Simulation time 16031344 ps
CPU time 1.33 seconds
Started Mar 24 01:09:47 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 236656 kb
Host smart-ba449118-67e8-4efc-9066-b26e28f4f3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2680150100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2680150100
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3780686381
Short name T763
Test name
Test status
Simulation time 325817508 ps
CPU time 12.77 seconds
Started Mar 24 01:09:48 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 244752 kb
Host smart-2cd5f0df-e729-465b-8316-3c4f48ee518a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3780686381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3780686381
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3453335150
Short name T138
Test name
Test status
Simulation time 1127416328 ps
CPU time 121.6 seconds
Started Mar 24 01:09:48 PM PDT 24
Finished Mar 24 01:11:50 PM PDT 24
Peak memory 256780 kb
Host smart-dbe0a878-60dd-41a0-8dc6-23ddf3c9bd1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3453335150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3453335150
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3917911829
Short name T748
Test name
Test status
Simulation time 101425511 ps
CPU time 11.63 seconds
Started Mar 24 01:09:47 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 248552 kb
Host smart-23f2e7ee-a22b-4eb3-b141-65f67c00624e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3917911829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3917911829
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.832938567
Short name T742
Test name
Test status
Simulation time 54815314 ps
CPU time 4.76 seconds
Started Mar 24 01:09:51 PM PDT 24
Finished Mar 24 01:09:56 PM PDT 24
Peak memory 239656 kb
Host smart-fe872251-260c-48e3-b16d-ab16def0b046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832938567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.832938567
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.866522610
Short name T729
Test name
Test status
Simulation time 36399794 ps
CPU time 5.3 seconds
Started Mar 24 01:09:53 PM PDT 24
Finished Mar 24 01:09:58 PM PDT 24
Peak memory 240224 kb
Host smart-5266b5b2-3aea-4049-8724-cd3e06ef4cb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=866522610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.866522610
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.431088608
Short name T721
Test name
Test status
Simulation time 11172678 ps
CPU time 1.59 seconds
Started Mar 24 01:09:50 PM PDT 24
Finished Mar 24 01:09:51 PM PDT 24
Peak memory 236708 kb
Host smart-18eac87b-18dd-44ee-98d4-088e45488c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=431088608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.431088608
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.277485890
Short name T801
Test name
Test status
Simulation time 503975291 ps
CPU time 39.84 seconds
Started Mar 24 01:09:52 PM PDT 24
Finished Mar 24 01:10:31 PM PDT 24
Peak memory 244848 kb
Host smart-9eef116c-3966-4dd2-ab99-957aec1ce7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=277485890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.277485890
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4012876714
Short name T140
Test name
Test status
Simulation time 2175589403 ps
CPU time 150.34 seconds
Started Mar 24 01:09:48 PM PDT 24
Finished Mar 24 01:12:19 PM PDT 24
Peak memory 256964 kb
Host smart-53f3c2b1-58de-4330-8d85-7ddaa79ce653
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4012876714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4012876714
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2324356046
Short name T135
Test name
Test status
Simulation time 19543812141 ps
CPU time 565.48 seconds
Started Mar 24 01:09:48 PM PDT 24
Finished Mar 24 01:19:14 PM PDT 24
Peak memory 265124 kb
Host smart-66c9c632-01d0-4021-a599-2f8cca540a6c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324356046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2324356046
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.271378441
Short name T739
Test name
Test status
Simulation time 261621407 ps
CPU time 13.6 seconds
Started Mar 24 01:09:46 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 247664 kb
Host smart-aa5d9da2-412e-4c4d-acb3-54ebb23c0ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=271378441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.271378441
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2994395466
Short name T818
Test name
Test status
Simulation time 2775366542 ps
CPU time 135.25 seconds
Started Mar 24 01:09:17 PM PDT 24
Finished Mar 24 01:11:32 PM PDT 24
Peak memory 236600 kb
Host smart-2f712788-9510-411f-aa2a-e9c798ac037b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2994395466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2994395466
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2584582312
Short name T809
Test name
Test status
Simulation time 1705184348 ps
CPU time 210.14 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:12:49 PM PDT 24
Peak memory 236572 kb
Host smart-715406da-b5c0-45dc-aa0d-7ac223b2ff5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2584582312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2584582312
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.646473862
Short name T803
Test name
Test status
Simulation time 362733678 ps
CPU time 11.24 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:09:30 PM PDT 24
Peak memory 240276 kb
Host smart-0ef8bdbc-cf69-469c-91d8-57afe2b8a4d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=646473862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.646473862
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2456919760
Short name T780
Test name
Test status
Simulation time 102974522 ps
CPU time 8.5 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 239640 kb
Host smart-679df229-8065-4402-acfa-513cac1a63b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456919760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2456919760
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3079148728
Short name T786
Test name
Test status
Simulation time 69543338 ps
CPU time 5.09 seconds
Started Mar 24 01:09:21 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 235696 kb
Host smart-7217472b-79fb-491b-bab6-1037e286c14d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3079148728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3079148728
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2756799601
Short name T743
Test name
Test status
Simulation time 22815329 ps
CPU time 1.4 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:25 PM PDT 24
Peak memory 235812 kb
Host smart-06880bc7-c6bd-4bd0-844a-403e57b233b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2756799601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2756799601
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1472967577
Short name T810
Test name
Test status
Simulation time 169644916 ps
CPU time 26.22 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:49 PM PDT 24
Peak memory 244872 kb
Host smart-d66bce75-5f39-4e61-a128-17e20153e318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1472967577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1472967577
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1504583613
Short name T142
Test name
Test status
Simulation time 58308591207 ps
CPU time 200.37 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:12:31 PM PDT 24
Peak memory 265364 kb
Host smart-5b2ce7e1-417a-405d-bd95-02387b4c1926
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1504583613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1504583613
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1562649355
Short name T129
Test name
Test status
Simulation time 6121817572 ps
CPU time 517.71 seconds
Started Mar 24 01:09:11 PM PDT 24
Finished Mar 24 01:17:49 PM PDT 24
Peak memory 265196 kb
Host smart-fc5d2e6c-7788-445a-aac4-a92176d528e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562649355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1562649355
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.284377661
Short name T720
Test name
Test status
Simulation time 92068456 ps
CPU time 11.36 seconds
Started Mar 24 01:09:14 PM PDT 24
Finished Mar 24 01:09:26 PM PDT 24
Peak memory 246684 kb
Host smart-2d7964fb-f588-45d6-b7df-96239969545a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=284377661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.284377661
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.899406424
Short name T358
Test name
Test status
Simulation time 12033325 ps
CPU time 1.35 seconds
Started Mar 24 01:09:52 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 236588 kb
Host smart-84a0eccd-db9b-4b0b-8a1a-f31649fced74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=899406424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.899406424
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.373233155
Short name T776
Test name
Test status
Simulation time 13476560 ps
CPU time 1.4 seconds
Started Mar 24 01:09:53 PM PDT 24
Finished Mar 24 01:09:55 PM PDT 24
Peak memory 236672 kb
Host smart-cd6bc7b0-a918-4876-9698-8ff0a044f423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373233155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.373233155
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2352649455
Short name T775
Test name
Test status
Simulation time 10326368 ps
CPU time 1.5 seconds
Started Mar 24 01:09:51 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 236740 kb
Host smart-0847564c-4bcb-47f5-a16e-01d6ee0d9e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352649455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2352649455
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.280007118
Short name T713
Test name
Test status
Simulation time 13233320 ps
CPU time 1.7 seconds
Started Mar 24 01:10:02 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 234764 kb
Host smart-4e5abceb-0529-4f0f-8ffd-b8851ea87276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=280007118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.280007118
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.120448274
Short name T716
Test name
Test status
Simulation time 20513099 ps
CPU time 1.3 seconds
Started Mar 24 01:09:59 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 235772 kb
Host smart-5d9abcd1-937d-45bb-84dd-9df2bfbe8944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=120448274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.120448274
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.2063697846
Short name T799
Test name
Test status
Simulation time 6894016 ps
CPU time 1.42 seconds
Started Mar 24 01:09:54 PM PDT 24
Finished Mar 24 01:09:56 PM PDT 24
Peak memory 235748 kb
Host smart-2e093546-4b5c-44f7-b0f8-e3f96c18c3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2063697846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2063697846
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3926383751
Short name T774
Test name
Test status
Simulation time 9506619 ps
CPU time 1.53 seconds
Started Mar 24 01:09:54 PM PDT 24
Finished Mar 24 01:09:56 PM PDT 24
Peak memory 236692 kb
Host smart-ed9538fa-dac3-4a31-a2f9-e8d63142410d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3926383751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3926383751
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.864850107
Short name T746
Test name
Test status
Simulation time 12256773 ps
CPU time 1.33 seconds
Started Mar 24 01:09:52 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 235816 kb
Host smart-4ecb8864-32e0-42df-8059-2e092653e79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=864850107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.864850107
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.617755268
Short name T360
Test name
Test status
Simulation time 91203914 ps
CPU time 1.45 seconds
Started Mar 24 01:10:02 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 236492 kb
Host smart-5dff6ef0-5044-46ec-bff8-b03de3c529a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617755268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.617755268
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.285347198
Short name T208
Test name
Test status
Simulation time 529114245 ps
CPU time 73.86 seconds
Started Mar 24 01:09:20 PM PDT 24
Finished Mar 24 01:10:34 PM PDT 24
Peak memory 240272 kb
Host smart-74a9d6dc-6569-4650-a57b-97e2c5c71b06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=285347198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.285347198
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3185304553
Short name T762
Test name
Test status
Simulation time 8556752154 ps
CPU time 511.85 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:17:54 PM PDT 24
Peak memory 236672 kb
Host smart-8e213e98-1024-40b3-9045-b9af2f663e29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3185304553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3185304553
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3809473144
Short name T821
Test name
Test status
Simulation time 22344958 ps
CPU time 3.85 seconds
Started Mar 24 01:09:20 PM PDT 24
Finished Mar 24 01:09:24 PM PDT 24
Peak memory 240256 kb
Host smart-2f8fae30-5856-4de7-be5d-603b2ee146a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3809473144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3809473144
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1271896844
Short name T827
Test name
Test status
Simulation time 47160237 ps
CPU time 5.94 seconds
Started Mar 24 01:09:20 PM PDT 24
Finished Mar 24 01:09:26 PM PDT 24
Peak memory 256784 kb
Host smart-7c956588-8e5b-42c6-8cb1-dbe9a0e209f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271896844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1271896844
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.551973384
Short name T718
Test name
Test status
Simulation time 117218717 ps
CPU time 8.3 seconds
Started Mar 24 01:09:19 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 235684 kb
Host smart-cada4781-388b-4fb6-b1f9-cd4552468f26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=551973384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.551973384
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1973413297
Short name T823
Test name
Test status
Simulation time 9122069 ps
CPU time 1.47 seconds
Started Mar 24 01:09:16 PM PDT 24
Finished Mar 24 01:09:18 PM PDT 24
Peak memory 235836 kb
Host smart-c6e1d3b9-d0f5-42d1-adad-3cad693aa0f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1973413297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1973413297
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.170978430
Short name T804
Test name
Test status
Simulation time 89730068 ps
CPU time 12.7 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:36 PM PDT 24
Peak memory 239732 kb
Host smart-849359c0-82a8-481a-af8a-e9db1d2d49ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=170978430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.170978430
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1475874965
Short name T152
Test name
Test status
Simulation time 6733375569 ps
CPU time 227.2 seconds
Started Mar 24 01:09:21 PM PDT 24
Finished Mar 24 01:13:09 PM PDT 24
Peak memory 265200 kb
Host smart-d5f35df0-42ad-42cd-abbe-7f5947637129
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1475874965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1475874965
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3602970801
Short name T149
Test name
Test status
Simulation time 7839903995 ps
CPU time 558.32 seconds
Started Mar 24 01:09:17 PM PDT 24
Finished Mar 24 01:18:36 PM PDT 24
Peak memory 265188 kb
Host smart-18e7f709-a7e3-428e-baae-c4adcf5d2804
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602970801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3602970801
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3324945508
Short name T744
Test name
Test status
Simulation time 304498630 ps
CPU time 21.86 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:09:44 PM PDT 24
Peak memory 248608 kb
Host smart-d045feae-a7a2-45c1-a275-bab031eff3d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324945508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3324945508
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2494007108
Short name T710
Test name
Test status
Simulation time 10021055 ps
CPU time 1.41 seconds
Started Mar 24 01:10:02 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 235764 kb
Host smart-2410cb86-094f-4448-8cc2-c5c60782ea6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2494007108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2494007108
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2985587386
Short name T259
Test name
Test status
Simulation time 12300495 ps
CPU time 1.26 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 235784 kb
Host smart-9386ae16-2589-4fb5-af1b-6e46ed6219b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2985587386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2985587386
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.464315477
Short name T749
Test name
Test status
Simulation time 13934525 ps
CPU time 1.28 seconds
Started Mar 24 01:09:56 PM PDT 24
Finished Mar 24 01:09:57 PM PDT 24
Peak memory 234784 kb
Host smart-3576f6ac-9dfd-47c8-8995-e828821c55c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464315477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.464315477
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.641582709
Short name T788
Test name
Test status
Simulation time 12876990 ps
CPU time 1.28 seconds
Started Mar 24 01:09:52 PM PDT 24
Finished Mar 24 01:09:53 PM PDT 24
Peak memory 235832 kb
Host smart-89349a3e-359c-4134-9041-f9c31e39a8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=641582709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.641582709
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1186251297
Short name T730
Test name
Test status
Simulation time 6774735 ps
CPU time 1.51 seconds
Started Mar 24 01:10:02 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 236628 kb
Host smart-d8fa13c1-f1ee-4acb-9aa1-d5b145fa1eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1186251297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1186251297
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.229936115
Short name T770
Test name
Test status
Simulation time 9311239 ps
CPU time 1.54 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 234776 kb
Host smart-5895629e-50be-404c-b987-64de6b7706a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=229936115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.229936115
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3262050924
Short name T752
Test name
Test status
Simulation time 6214064 ps
CPU time 1.45 seconds
Started Mar 24 01:10:02 PM PDT 24
Finished Mar 24 01:10:04 PM PDT 24
Peak memory 234732 kb
Host smart-c995b3aa-c40c-46bc-87d4-bab453350717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3262050924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3262050924
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2352317860
Short name T761
Test name
Test status
Simulation time 6430295 ps
CPU time 1.46 seconds
Started Mar 24 01:09:57 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 236688 kb
Host smart-43c5ce0d-c5d8-47de-8aee-1fe0d0edc36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352317860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2352317860
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1794194138
Short name T727
Test name
Test status
Simulation time 24738419 ps
CPU time 1.39 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 235812 kb
Host smart-1609d416-d3bb-442a-bff8-cfc28ba460e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1794194138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1794194138
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2857961517
Short name T758
Test name
Test status
Simulation time 8911811 ps
CPU time 1.51 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 236692 kb
Host smart-dc72fe09-d6ed-422a-8179-f242104b791d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2857961517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2857961517
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4002754024
Short name T793
Test name
Test status
Simulation time 910680292 ps
CPU time 71.59 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:10:34 PM PDT 24
Peak memory 240164 kb
Host smart-390ba58f-92e8-482d-92f2-b16839cb9ae6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4002754024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4002754024
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1005381528
Short name T717
Test name
Test status
Simulation time 3271479978 ps
CPU time 106.26 seconds
Started Mar 24 01:09:15 PM PDT 24
Finished Mar 24 01:11:02 PM PDT 24
Peak memory 236636 kb
Host smart-4ffd49bd-9294-40a9-bce8-9f37f76b4c4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1005381528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1005381528
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3410206486
Short name T747
Test name
Test status
Simulation time 348252181 ps
CPU time 4 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:09:23 PM PDT 24
Peak memory 240224 kb
Host smart-101163e3-9a2a-45d0-be9b-e4410d965e2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3410206486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3410206486
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1496092536
Short name T361
Test name
Test status
Simulation time 58341707 ps
CPU time 8.68 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:09:31 PM PDT 24
Peak memory 256560 kb
Host smart-b6aa74ef-8f7b-4b7f-9b51-2f2db01d27e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496092536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1496092536
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2060753437
Short name T731
Test name
Test status
Simulation time 35645757 ps
CPU time 5.16 seconds
Started Mar 24 01:09:17 PM PDT 24
Finished Mar 24 01:09:23 PM PDT 24
Peak memory 235700 kb
Host smart-5cff6bf5-fee6-44a0-8bbb-02729765e527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2060753437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2060753437
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2357072203
Short name T797
Test name
Test status
Simulation time 9156525 ps
CPU time 1.25 seconds
Started Mar 24 01:09:20 PM PDT 24
Finished Mar 24 01:09:22 PM PDT 24
Peak memory 235756 kb
Host smart-a1965e2d-845c-4dd0-96e4-fc2b9d60255e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357072203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2357072203
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1937014010
Short name T812
Test name
Test status
Simulation time 89895895 ps
CPU time 11.97 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:09:35 PM PDT 24
Peak memory 240276 kb
Host smart-0489a245-ce3d-4445-965f-76d8716b0273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1937014010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1937014010
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2423325814
Short name T817
Test name
Test status
Simulation time 74532321109 ps
CPU time 442.26 seconds
Started Mar 24 01:09:18 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 267704 kb
Host smart-5ab3807d-a666-4340-b2cf-c2efeca01448
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423325814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2423325814
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1609570029
Short name T711
Test name
Test status
Simulation time 43607149 ps
CPU time 5.85 seconds
Started Mar 24 01:09:21 PM PDT 24
Finished Mar 24 01:09:27 PM PDT 24
Peak memory 248584 kb
Host smart-4b79c8cf-5b93-42ff-aa74-9ae7c2145000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609570029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1609570029
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3543253653
Short name T814
Test name
Test status
Simulation time 12885138 ps
CPU time 1.68 seconds
Started Mar 24 01:10:00 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 235756 kb
Host smart-15c474d5-d034-40cb-96be-a34bfb9ea7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3543253653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3543253653
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1975077795
Short name T755
Test name
Test status
Simulation time 6506194 ps
CPU time 1.42 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 235644 kb
Host smart-0009e09f-b855-465f-9aa7-4a6ee3fb73e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1975077795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1975077795
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1572783264
Short name T170
Test name
Test status
Simulation time 11550270 ps
CPU time 1.39 seconds
Started Mar 24 01:09:59 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 236648 kb
Host smart-b2ffb46c-01d6-492d-ac24-7ea8ad12c8d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1572783264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1572783264
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1888483564
Short name T357
Test name
Test status
Simulation time 15207078 ps
CPU time 1.39 seconds
Started Mar 24 01:10:00 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 234952 kb
Host smart-755b0863-b1b6-4720-b92c-2e739e01f02d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1888483564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1888483564
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1343786923
Short name T750
Test name
Test status
Simulation time 16855347 ps
CPU time 1.3 seconds
Started Mar 24 01:09:59 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 236656 kb
Host smart-e0a11aaf-a463-404f-a21b-2d6fe083ed49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1343786923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1343786923
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4263852161
Short name T169
Test name
Test status
Simulation time 38320091 ps
CPU time 1.33 seconds
Started Mar 24 01:09:57 PM PDT 24
Finished Mar 24 01:09:59 PM PDT 24
Peak memory 235800 kb
Host smart-4d36bb9a-01d9-4d8f-9dba-b9ac1271bb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4263852161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4263852161
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1599073505
Short name T171
Test name
Test status
Simulation time 14369290 ps
CPU time 1.41 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 236672 kb
Host smart-8dae3ecc-2af2-41d0-bd81-07257ec8bac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1599073505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1599073505
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2756383899
Short name T790
Test name
Test status
Simulation time 9525974 ps
CPU time 1.22 seconds
Started Mar 24 01:10:00 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 236636 kb
Host smart-a4a6e1e5-5933-48b3-9e40-589634d9682c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2756383899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2756383899
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1727662041
Short name T738
Test name
Test status
Simulation time 8830838 ps
CPU time 1.6 seconds
Started Mar 24 01:10:00 PM PDT 24
Finished Mar 24 01:10:01 PM PDT 24
Peak memory 235688 kb
Host smart-b68e8250-ef7e-455a-8cae-bdee0d24dc6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1727662041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1727662041
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2128000305
Short name T751
Test name
Test status
Simulation time 9224047 ps
CPU time 1.26 seconds
Started Mar 24 01:09:58 PM PDT 24
Finished Mar 24 01:10:00 PM PDT 24
Peak memory 236688 kb
Host smart-9a0e2d12-d210-47fb-ad13-817fea0b0d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2128000305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2128000305
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1584308394
Short name T766
Test name
Test status
Simulation time 147427754 ps
CPU time 6.34 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:35 PM PDT 24
Peak memory 239880 kb
Host smart-06bc3b38-e3ff-44a0-9f2a-b1e53c186675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584308394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1584308394
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3522366416
Short name T765
Test name
Test status
Simulation time 59451011 ps
CPU time 3.36 seconds
Started Mar 24 01:09:25 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 236584 kb
Host smart-e0d15a71-1722-4289-857e-c9c164e8a48a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3522366416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3522366416
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3892329263
Short name T726
Test name
Test status
Simulation time 15460489 ps
CPU time 1.32 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:09:24 PM PDT 24
Peak memory 234828 kb
Host smart-d2a88729-59ed-45d1-b0d5-4571b591c79a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3892329263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3892329263
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.699201833
Short name T719
Test name
Test status
Simulation time 265275470 ps
CPU time 20.2 seconds
Started Mar 24 01:09:25 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 240384 kb
Host smart-3bf3a8cc-469f-4744-a09a-a980c3380090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=699201833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.699201833
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.4170566068
Short name T141
Test name
Test status
Simulation time 12845841106 ps
CPU time 933.4 seconds
Started Mar 24 01:09:26 PM PDT 24
Finished Mar 24 01:25:00 PM PDT 24
Peak memory 270228 kb
Host smart-c26b63db-4fdb-481b-897f-03d932e7a62f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170566068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.4170566068
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.289101101
Short name T723
Test name
Test status
Simulation time 1498277750 ps
CPU time 26.05 seconds
Started Mar 24 01:09:25 PM PDT 24
Finished Mar 24 01:09:51 PM PDT 24
Peak memory 248508 kb
Host smart-0d557715-0713-4cd5-bdc2-91918d2b868e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=289101101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.289101101
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2201365376
Short name T365
Test name
Test status
Simulation time 172440775 ps
CPU time 12.21 seconds
Started Mar 24 01:09:27 PM PDT 24
Finished Mar 24 01:09:40 PM PDT 24
Peak memory 250380 kb
Host smart-7ef1b93e-14a3-4299-a639-fcb76b4c157a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201365376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2201365376
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3941311820
Short name T771
Test name
Test status
Simulation time 247173956 ps
CPU time 5.45 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:29 PM PDT 24
Peak memory 240132 kb
Host smart-e36e3463-98ab-42c7-b14e-65e1b0838b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3941311820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3941311820
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2804886363
Short name T816
Test name
Test status
Simulation time 26589631 ps
CPU time 1.33 seconds
Started Mar 24 01:09:24 PM PDT 24
Finished Mar 24 01:09:25 PM PDT 24
Peak memory 235768 kb
Host smart-5735a141-f849-4434-88b2-70f2602829b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2804886363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2804886363
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2031505278
Short name T795
Test name
Test status
Simulation time 1367810576 ps
CPU time 42.69 seconds
Started Mar 24 01:09:27 PM PDT 24
Finished Mar 24 01:10:10 PM PDT 24
Peak memory 248460 kb
Host smart-ea98a9ac-e5ff-4ef1-9b2f-15e60ee84e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2031505278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2031505278
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2272409989
Short name T781
Test name
Test status
Simulation time 606149270 ps
CPU time 11.01 seconds
Started Mar 24 01:09:25 PM PDT 24
Finished Mar 24 01:09:36 PM PDT 24
Peak memory 247520 kb
Host smart-489b596a-e5ad-497f-8773-7050b8409f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2272409989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2272409989
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.368615218
Short name T772
Test name
Test status
Simulation time 31364975 ps
CPU time 4.91 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 238456 kb
Host smart-7cc07117-99f5-4230-99fd-f134c6bf823d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368615218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.368615218
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1944156866
Short name T783
Test name
Test status
Simulation time 21575395 ps
CPU time 4.27 seconds
Started Mar 24 01:09:26 PM PDT 24
Finished Mar 24 01:09:30 PM PDT 24
Peak memory 236764 kb
Host smart-4ae48e1c-7c49-442c-a6ec-653d823fb6fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1944156866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1944156866
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1323778125
Short name T722
Test name
Test status
Simulation time 15060090 ps
CPU time 1.53 seconds
Started Mar 24 01:09:26 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 235836 kb
Host smart-e7059b39-a5e8-4dfd-88d4-03c8a203ca05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1323778125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1323778125
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4075516909
Short name T737
Test name
Test status
Simulation time 2231639502 ps
CPU time 19.67 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:48 PM PDT 24
Peak memory 243892 kb
Host smart-c13e5e7f-d3ee-477a-bdfd-666f61553a16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4075516909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.4075516909
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.486193450
Short name T158
Test name
Test status
Simulation time 1672234586 ps
CPU time 209.44 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:12:52 PM PDT 24
Peak memory 265040 kb
Host smart-5ea898c7-b0ed-4998-80c5-cbe61f7524e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=486193450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.486193450
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2746458511
Short name T156
Test name
Test status
Simulation time 15699910176 ps
CPU time 538.12 seconds
Started Mar 24 01:09:26 PM PDT 24
Finished Mar 24 01:18:24 PM PDT 24
Peak memory 265204 kb
Host smart-569c294a-93ec-4fc6-8e61-b82dae5b047b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746458511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2746458511
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3419964983
Short name T767
Test name
Test status
Simulation time 477276988 ps
CPU time 8.65 seconds
Started Mar 24 01:09:22 PM PDT 24
Finished Mar 24 01:09:31 PM PDT 24
Peak memory 248572 kb
Host smart-8b5bb4bb-d4e7-42d0-8df6-6f55b3180e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3419964983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3419964983
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2666305525
Short name T728
Test name
Test status
Simulation time 351799806 ps
CPU time 6.88 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:30 PM PDT 24
Peak memory 240408 kb
Host smart-e9cd9b3c-34a2-41ce-a381-24ed86e44dc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666305525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2666305525
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1571025551
Short name T759
Test name
Test status
Simulation time 118354913 ps
CPU time 5.47 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:09:28 PM PDT 24
Peak memory 236492 kb
Host smart-bd23d6b2-1abe-4777-9300-d5570bbc52e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1571025551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1571025551
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1455267600
Short name T813
Test name
Test status
Simulation time 18752429 ps
CPU time 1.37 seconds
Started Mar 24 01:09:24 PM PDT 24
Finished Mar 24 01:09:25 PM PDT 24
Peak memory 236684 kb
Host smart-981f7787-7105-4cfb-89ae-317b939370aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1455267600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1455267600
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2538979998
Short name T207
Test name
Test status
Simulation time 508235748 ps
CPU time 38.47 seconds
Started Mar 24 01:09:23 PM PDT 24
Finished Mar 24 01:10:02 PM PDT 24
Peak memory 244864 kb
Host smart-723c82a3-23b3-4cdb-aa2e-41efb22822ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2538979998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2538979998
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3176455508
Short name T160
Test name
Test status
Simulation time 2897585074 ps
CPU time 90.76 seconds
Started Mar 24 01:09:24 PM PDT 24
Finished Mar 24 01:10:55 PM PDT 24
Peak memory 256956 kb
Host smart-9a1d571f-90b8-4c37-8cc0-038c900b2c2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3176455508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3176455508
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1088801448
Short name T708
Test name
Test status
Simulation time 120450878 ps
CPU time 16.49 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:45 PM PDT 24
Peak memory 248332 kb
Host smart-c880458d-6b67-47a5-8410-0703d46f42bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1088801448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1088801448
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1644895778
Short name T757
Test name
Test status
Simulation time 100313291 ps
CPU time 7.76 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:36 PM PDT 24
Peak memory 238808 kb
Host smart-198dc7c6-d40f-4138-8d12-0a7b7059fbd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644895778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1644895778
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2243500080
Short name T732
Test name
Test status
Simulation time 471969815 ps
CPU time 4.2 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:33 PM PDT 24
Peak memory 235672 kb
Host smart-17ef1ed4-87b5-4cd7-b960-cbaa63d9e2fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2243500080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2243500080
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.768546687
Short name T359
Test name
Test status
Simulation time 15965662 ps
CPU time 1.55 seconds
Started Mar 24 01:09:30 PM PDT 24
Finished Mar 24 01:09:31 PM PDT 24
Peak memory 235720 kb
Host smart-426ef3d3-85e3-4bf6-92e9-1cd8aef2eaa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=768546687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.768546687
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4001534051
Short name T206
Test name
Test status
Simulation time 1022851006 ps
CPU time 20.09 seconds
Started Mar 24 01:09:28 PM PDT 24
Finished Mar 24 01:09:49 PM PDT 24
Peak memory 248532 kb
Host smart-beb20ddf-676f-41e6-a20b-2a0da91e7bb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4001534051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.4001534051
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1297754800
Short name T815
Test name
Test status
Simulation time 7593123497 ps
CPU time 533.79 seconds
Started Mar 24 01:09:29 PM PDT 24
Finished Mar 24 01:18:23 PM PDT 24
Peak memory 265320 kb
Host smart-936d273b-634a-4a3c-8116-07532f479b70
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297754800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1297754800
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.863335254
Short name T266
Test name
Test status
Simulation time 325461666 ps
CPU time 21.48 seconds
Started Mar 24 01:09:29 PM PDT 24
Finished Mar 24 01:09:50 PM PDT 24
Peak memory 251616 kb
Host smart-b4946e3a-9217-4fc4-9c51-06c78c8c133a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=863335254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.863335254
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.571427971
Short name T568
Test name
Test status
Simulation time 44581228924 ps
CPU time 2965.58 seconds
Started Mar 24 02:53:51 PM PDT 24
Finished Mar 24 03:43:18 PM PDT 24
Peak memory 281592 kb
Host smart-1475a382-41fb-4208-ae6e-d7acf34eee35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571427971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.571427971
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.929244236
Short name T640
Test name
Test status
Simulation time 1194498989 ps
CPU time 14.59 seconds
Started Mar 24 02:53:47 PM PDT 24
Finished Mar 24 02:54:02 PM PDT 24
Peak memory 240660 kb
Host smart-9b7e85e3-3fe5-4f20-9b23-1968e86ca91a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=929244236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.929244236
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1684723770
Short name T470
Test name
Test status
Simulation time 229158575 ps
CPU time 23.11 seconds
Started Mar 24 02:53:49 PM PDT 24
Finished Mar 24 02:54:12 PM PDT 24
Peak memory 255992 kb
Host smart-88e36d49-f107-4283-b297-9bcbccd2a28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
23770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1684723770
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1722427634
Short name T273
Test name
Test status
Simulation time 1004272847 ps
CPU time 60.35 seconds
Started Mar 24 02:53:48 PM PDT 24
Finished Mar 24 02:54:49 PM PDT 24
Peak memory 255712 kb
Host smart-73663279-65d9-4fe6-989e-9b625bbbba41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
27634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1722427634
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.863448271
Short name T336
Test name
Test status
Simulation time 138832554492 ps
CPU time 1299.24 seconds
Started Mar 24 02:53:52 PM PDT 24
Finished Mar 24 03:15:33 PM PDT 24
Peak memory 265164 kb
Host smart-a5dcccbc-df62-40c3-9e0a-f6e3457eba0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863448271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.863448271
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2361440938
Short name T545
Test name
Test status
Simulation time 217499699944 ps
CPU time 3367.39 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 03:49:54 PM PDT 24
Peak memory 288776 kb
Host smart-aead9cb6-3dcd-45c9-96b3-4cb708440ad7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361440938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2361440938
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.258262170
Short name T326
Test name
Test status
Simulation time 7880927547 ps
CPU time 165.26 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 02:56:31 PM PDT 24
Peak memory 247860 kb
Host smart-31451e6d-7700-4162-b412-44f664e48651
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258262170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.258262170
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2152155301
Short name T529
Test name
Test status
Simulation time 96142200 ps
CPU time 11.07 seconds
Started Mar 24 02:53:48 PM PDT 24
Finished Mar 24 02:54:00 PM PDT 24
Peak memory 255012 kb
Host smart-9118f3ba-b470-4d53-be28-911d89171fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521
55301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2152155301
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2088246669
Short name T676
Test name
Test status
Simulation time 285985609 ps
CPU time 5.87 seconds
Started Mar 24 02:53:42 PM PDT 24
Finished Mar 24 02:53:48 PM PDT 24
Peak memory 253244 kb
Host smart-6ffa52cb-05d2-4de2-b377-a5983f02888b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
46669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2088246669
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3333541825
Short name T32
Test name
Test status
Simulation time 5319060111 ps
CPU time 207.07 seconds
Started Mar 24 02:53:49 PM PDT 24
Finished Mar 24 02:57:17 PM PDT 24
Peak memory 273716 kb
Host smart-8ac69199-4d3a-454c-a30d-cdfaaa6aeb78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3333541825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3333541825
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1038691907
Short name T35
Test name
Test status
Simulation time 2579377433 ps
CPU time 50.69 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 02:54:37 PM PDT 24
Peak memory 256052 kb
Host smart-7f559ace-114d-4a01-b67d-e2ff703f1af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
91907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1038691907
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3733445351
Short name T686
Test name
Test status
Simulation time 620204659 ps
CPU time 35.73 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:54:19 PM PDT 24
Peak memory 248864 kb
Host smart-04e2821a-c826-444c-a1cb-b76011c89c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
45351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3733445351
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1350708436
Short name T460
Test name
Test status
Simulation time 6067891251 ps
CPU time 369.54 seconds
Started Mar 24 02:53:45 PM PDT 24
Finished Mar 24 02:59:55 PM PDT 24
Peak memory 257128 kb
Host smart-241de13c-952d-4702-bf5c-44a924379fda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350708436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1350708436
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.147141464
Short name T105
Test name
Test status
Simulation time 106265333908 ps
CPU time 3051.62 seconds
Started Mar 24 02:53:45 PM PDT 24
Finished Mar 24 03:44:38 PM PDT 24
Peak memory 306344 kb
Host smart-8a8f5225-255e-4bc4-833f-5bcae7a666e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147141464 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.147141464
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1383778581
Short name T261
Test name
Test status
Simulation time 80447860480 ps
CPU time 2510.57 seconds
Started Mar 24 02:53:45 PM PDT 24
Finished Mar 24 03:35:36 PM PDT 24
Peak memory 281708 kb
Host smart-e9da3cc5-9c11-43ac-84f4-260a35006a63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383778581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1383778581
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1812467696
Short name T650
Test name
Test status
Simulation time 2287682598 ps
CPU time 20.21 seconds
Started Mar 24 02:53:54 PM PDT 24
Finished Mar 24 02:54:15 PM PDT 24
Peak memory 248872 kb
Host smart-234185d9-f899-49c2-832e-890d7d8af905
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1812467696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1812467696
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1059037743
Short name T634
Test name
Test status
Simulation time 2944943083 ps
CPU time 184.02 seconds
Started Mar 24 02:53:44 PM PDT 24
Finished Mar 24 02:56:48 PM PDT 24
Peak memory 256796 kb
Host smart-54d67a98-6094-4171-9745-ca7770c81cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
37743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1059037743
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1855682519
Short name T430
Test name
Test status
Simulation time 1103052114 ps
CPU time 32.75 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 02:54:31 PM PDT 24
Peak memory 255508 kb
Host smart-9c035f0f-0ea0-4c55-aa41-0fec18d25885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18556
82519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1855682519
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2864175775
Short name T624
Test name
Test status
Simulation time 11924973107 ps
CPU time 1097.57 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 03:12:04 PM PDT 24
Peak memory 273324 kb
Host smart-6a8782e2-b641-4459-bd67-288ec44b24a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864175775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2864175775
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.4284757005
Short name T424
Test name
Test status
Simulation time 37207753579 ps
CPU time 2269.38 seconds
Started Mar 24 02:53:55 PM PDT 24
Finished Mar 24 03:31:45 PM PDT 24
Peak memory 272908 kb
Host smart-9b1f489b-2c2c-48b6-af2d-3fe70d7619d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284757005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.4284757005
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3222042824
Short name T667
Test name
Test status
Simulation time 20262146438 ps
CPU time 215.44 seconds
Started Mar 24 02:53:47 PM PDT 24
Finished Mar 24 02:57:23 PM PDT 24
Peak memory 248120 kb
Host smart-97350407-b585-4830-a05e-6b4a1a244756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222042824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3222042824
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1039859900
Short name T195
Test name
Test status
Simulation time 1732451515 ps
CPU time 32.68 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 02:54:19 PM PDT 24
Peak memory 248828 kb
Host smart-79e10eec-92be-4934-976a-9a2bf5809cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
59900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1039859900
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3797851872
Short name T411
Test name
Test status
Simulation time 3524565036 ps
CPU time 49.16 seconds
Started Mar 24 02:53:46 PM PDT 24
Finished Mar 24 02:54:35 PM PDT 24
Peak memory 247704 kb
Host smart-b95ad044-e95a-42ab-a659-fea8165cdcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37978
51872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3797851872
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.416444260
Short name T33
Test name
Test status
Simulation time 181738014 ps
CPU time 10.9 seconds
Started Mar 24 02:53:52 PM PDT 24
Finished Mar 24 02:54:03 PM PDT 24
Peak memory 268584 kb
Host smart-f8e6a7ea-f365-4998-9701-c2117e45a4d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=416444260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.416444260
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4140835462
Short name T599
Test name
Test status
Simulation time 731849099 ps
CPU time 9.38 seconds
Started Mar 24 02:53:53 PM PDT 24
Finished Mar 24 02:54:03 PM PDT 24
Peak memory 252612 kb
Host smart-706b053f-9d2c-4763-bab0-e6cd4683fe1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41408
35462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4140835462
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3587713039
Short name T703
Test name
Test status
Simulation time 3807173901 ps
CPU time 39.48 seconds
Started Mar 24 02:53:49 PM PDT 24
Finished Mar 24 02:54:29 PM PDT 24
Peak memory 248956 kb
Host smart-6e96a2bf-7714-48b3-a6c4-6720946f9521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35877
13039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3587713039
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.691947306
Short name T570
Test name
Test status
Simulation time 1509513447 ps
CPU time 93.94 seconds
Started Mar 24 02:53:54 PM PDT 24
Finished Mar 24 02:55:28 PM PDT 24
Peak memory 256248 kb
Host smart-acde3fba-93b4-4e41-8228-0470f5bc25b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691947306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.691947306
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4181948719
Short name T34
Test name
Test status
Simulation time 280029261033 ps
CPU time 6721.94 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 04:46:02 PM PDT 24
Peak memory 394080 kb
Host smart-08ae7782-8875-41c6-9400-cf7443f8b011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181948719 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4181948719
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3582085425
Short name T219
Test name
Test status
Simulation time 47940668 ps
CPU time 4 seconds
Started Mar 24 02:54:20 PM PDT 24
Finished Mar 24 02:54:24 PM PDT 24
Peak memory 249100 kb
Host smart-ed66d2fd-c395-44a9-8db7-c3fbc97fea98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3582085425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3582085425
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.779552467
Short name T493
Test name
Test status
Simulation time 309173223 ps
CPU time 7.4 seconds
Started Mar 24 02:54:17 PM PDT 24
Finished Mar 24 02:54:25 PM PDT 24
Peak memory 240632 kb
Host smart-e61fe865-a408-4418-9088-e808915cd90c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=779552467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.779552467
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3583763279
Short name T669
Test name
Test status
Simulation time 13319173981 ps
CPU time 216.9 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 02:57:55 PM PDT 24
Peak memory 257100 kb
Host smart-8ea82125-e1e2-4a46-b36d-e0d2d424e8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35837
63279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3583763279
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3148645883
Short name T433
Test name
Test status
Simulation time 612925631 ps
CPU time 20.12 seconds
Started Mar 24 02:54:17 PM PDT 24
Finished Mar 24 02:54:37 PM PDT 24
Peak memory 255048 kb
Host smart-c479cb80-7438-45f0-81a1-f5bdb89aab2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
45883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3148645883
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.951271795
Short name T198
Test name
Test status
Simulation time 39680356830 ps
CPU time 1525.34 seconds
Started Mar 24 02:54:16 PM PDT 24
Finished Mar 24 03:19:42 PM PDT 24
Peak memory 289356 kb
Host smart-6f470924-692b-48b8-b0fb-53051c95d09c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951271795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.951271795
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2127848759
Short name T454
Test name
Test status
Simulation time 122051435687 ps
CPU time 2119.76 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 03:29:38 PM PDT 24
Peak memory 273452 kb
Host smart-7745d61e-4c7b-4eaf-92cc-1a6e24dbe79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127848759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2127848759
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.896467961
Short name T451
Test name
Test status
Simulation time 9983927777 ps
CPU time 104.72 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 02:56:03 PM PDT 24
Peak memory 248060 kb
Host smart-cab7480f-e366-42f1-a3c5-272e5c9777fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896467961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.896467961
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1355974370
Short name T46
Test name
Test status
Simulation time 1805097739 ps
CPU time 61.87 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 02:55:20 PM PDT 24
Peak memory 249112 kb
Host smart-c10154a3-7525-407e-818e-a756f7b98d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13559
74370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1355974370
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2776221271
Short name T660
Test name
Test status
Simulation time 350938675 ps
CPU time 20.57 seconds
Started Mar 24 02:54:19 PM PDT 24
Finished Mar 24 02:54:39 PM PDT 24
Peak memory 254980 kb
Host smart-42882ac4-1547-4090-a695-0a70a36b7d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27762
21271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2776221271
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3216940750
Short name T559
Test name
Test status
Simulation time 2915944625 ps
CPU time 54.66 seconds
Started Mar 24 02:54:19 PM PDT 24
Finished Mar 24 02:55:14 PM PDT 24
Peak memory 255948 kb
Host smart-c7bef34e-c1dd-4175-9974-f24a25be9386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32169
40750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3216940750
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2421108546
Short name T590
Test name
Test status
Simulation time 2641683052 ps
CPU time 47.8 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 02:55:08 PM PDT 24
Peak memory 256096 kb
Host smart-fe049f4b-3cdb-43db-b51b-ba011ad4dabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
08546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2421108546
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3096325432
Short name T615
Test name
Test status
Simulation time 827525443 ps
CPU time 49.44 seconds
Started Mar 24 02:54:19 PM PDT 24
Finished Mar 24 02:55:09 PM PDT 24
Peak memory 248824 kb
Host smart-d827a427-d402-4fa0-930a-1a3162619eb6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096325432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3096325432
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2928653354
Short name T216
Test name
Test status
Simulation time 517378509427 ps
CPU time 3490.07 seconds
Started Mar 24 02:54:26 PM PDT 24
Finished Mar 24 03:52:37 PM PDT 24
Peak memory 322300 kb
Host smart-c909d28f-a7f2-44d1-ab02-8517e2e52610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928653354 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2928653354
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2458054985
Short name T233
Test name
Test status
Simulation time 38389579 ps
CPU time 3.47 seconds
Started Mar 24 02:54:24 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 249028 kb
Host smart-e73eb2e8-5041-4f5f-a20a-cd85b7fe603d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2458054985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2458054985
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.595639260
Short name T116
Test name
Test status
Simulation time 791703281598 ps
CPU time 2583.41 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 03:37:26 PM PDT 24
Peak memory 281668 kb
Host smart-b9eb1987-9779-49e9-a878-574e17092502
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595639260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.595639260
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3745702892
Short name T641
Test name
Test status
Simulation time 4835117460 ps
CPU time 53.64 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 02:55:14 PM PDT 24
Peak memory 248888 kb
Host smart-4a54dc36-8224-4171-a6fc-f02657b94d4a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3745702892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3745702892
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.314714906
Short name T212
Test name
Test status
Simulation time 1522702080 ps
CPU time 48.16 seconds
Started Mar 24 02:54:24 PM PDT 24
Finished Mar 24 02:55:12 PM PDT 24
Peak memory 256116 kb
Host smart-eaa85ed4-e90d-4222-bf10-1954723944d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31471
4906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.314714906
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.552303482
Short name T606
Test name
Test status
Simulation time 880015118 ps
CPU time 49.04 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 02:55:10 PM PDT 24
Peak memory 255724 kb
Host smart-feff3064-38bc-4d2d-a885-8113fa204af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55230
3482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.552303482
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3863457274
Short name T413
Test name
Test status
Simulation time 50565261770 ps
CPU time 1612.92 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 03:21:14 PM PDT 24
Peak memory 265272 kb
Host smart-3aa7b4dd-2711-4e98-9342-20ab605cefcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863457274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3863457274
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.540128586
Short name T333
Test name
Test status
Simulation time 8469492523 ps
CPU time 175.36 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 02:57:18 PM PDT 24
Peak memory 247884 kb
Host smart-7f79ddde-1622-4e2f-a3f9-402ded76b4bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540128586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.540128586
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.426832260
Short name T23
Test name
Test status
Simulation time 1436813084 ps
CPU time 43.65 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 02:55:05 PM PDT 24
Peak memory 256024 kb
Host smart-0d190dea-afe7-4eab-86ec-3a0591a8d7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
2260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.426832260
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2219453916
Short name T199
Test name
Test status
Simulation time 1508345572 ps
CPU time 26.12 seconds
Started Mar 24 02:54:26 PM PDT 24
Finished Mar 24 02:54:52 PM PDT 24
Peak memory 254596 kb
Host smart-68cd45d4-b9f6-4456-b075-d05a6b296837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22194
53916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2219453916
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2828425991
Short name T210
Test name
Test status
Simulation time 1396310738 ps
CPU time 36.39 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 02:54:59 PM PDT 24
Peak memory 249160 kb
Host smart-1e10d549-d874-48ed-810c-b321f77b12c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28284
25991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2828425991
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1165045961
Short name T611
Test name
Test status
Simulation time 195375874 ps
CPU time 7.67 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 02:54:29 PM PDT 24
Peak memory 249168 kb
Host smart-3e9f680c-c5b2-4d04-a6a4-e4f6aaa4167a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650
45961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1165045961
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3523535790
Short name T661
Test name
Test status
Simulation time 4108632368 ps
CPU time 236.48 seconds
Started Mar 24 02:54:22 PM PDT 24
Finished Mar 24 02:58:19 PM PDT 24
Peak memory 256560 kb
Host smart-5971689f-ed63-4326-a398-46be1a4561e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523535790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3523535790
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.900152997
Short name T312
Test name
Test status
Simulation time 35970837170 ps
CPU time 954.39 seconds
Started Mar 24 02:54:28 PM PDT 24
Finished Mar 24 03:10:22 PM PDT 24
Peak memory 273472 kb
Host smart-3295d088-1e35-4356-a0eb-9f84f900b1f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900152997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.900152997
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2275077917
Short name T551
Test name
Test status
Simulation time 560163033 ps
CPU time 23.68 seconds
Started Mar 24 02:54:28 PM PDT 24
Finished Mar 24 02:54:52 PM PDT 24
Peak memory 240668 kb
Host smart-a6226029-82a7-4dec-bb9b-a5bacc98b64b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2275077917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2275077917
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3285467640
Short name T4
Test name
Test status
Simulation time 11662551725 ps
CPU time 333.57 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 02:59:54 PM PDT 24
Peak memory 257080 kb
Host smart-511865e6-908b-4647-adcd-575a812148b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32854
67640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3285467640
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.104880236
Short name T80
Test name
Test status
Simulation time 4257073934 ps
CPU time 68.12 seconds
Started Mar 24 02:54:24 PM PDT 24
Finished Mar 24 02:55:32 PM PDT 24
Peak memory 249256 kb
Host smart-3875230e-b658-44a6-a5bd-ca075dd6b434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10488
0236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.104880236
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2661607419
Short name T69
Test name
Test status
Simulation time 14028713630 ps
CPU time 962.63 seconds
Started Mar 24 02:54:28 PM PDT 24
Finished Mar 24 03:10:31 PM PDT 24
Peak memory 269420 kb
Host smart-e047bc30-bc52-4f45-80c0-67c23314befc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661607419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2661607419
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3132824367
Short name T382
Test name
Test status
Simulation time 33075212107 ps
CPU time 2210.23 seconds
Started Mar 24 02:54:28 PM PDT 24
Finished Mar 24 03:31:18 PM PDT 24
Peak memory 269576 kb
Host smart-6a5656af-52e6-46af-911c-64faef061c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132824367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3132824367
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3986153798
Short name T71
Test name
Test status
Simulation time 8926691982 ps
CPU time 342.29 seconds
Started Mar 24 02:54:29 PM PDT 24
Finished Mar 24 03:00:12 PM PDT 24
Peak memory 247944 kb
Host smart-9cfad605-bd0b-468b-9cac-d75bc75fb304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986153798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3986153798
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3728935811
Short name T367
Test name
Test status
Simulation time 919766780 ps
CPU time 27.13 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 02:54:49 PM PDT 24
Peak memory 255888 kb
Host smart-ac5102e2-773c-483f-82c3-fec5fbc47769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
35811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3728935811
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3910202936
Short name T292
Test name
Test status
Simulation time 3178141659 ps
CPU time 53.32 seconds
Started Mar 24 02:54:23 PM PDT 24
Finished Mar 24 02:55:16 PM PDT 24
Peak memory 248732 kb
Host smart-58628cd9-9734-461a-b0b1-c665de178841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39102
02936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3910202936
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1241114774
Short name T237
Test name
Test status
Simulation time 1176338041 ps
CPU time 25.23 seconds
Started Mar 24 02:54:24 PM PDT 24
Finished Mar 24 02:54:49 PM PDT 24
Peak memory 256124 kb
Host smart-1a04df21-21f6-4ed1-ae5b-39d52307c7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12411
14774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1241114774
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3469888659
Short name T388
Test name
Test status
Simulation time 1250258743 ps
CPU time 41.99 seconds
Started Mar 24 02:54:24 PM PDT 24
Finished Mar 24 02:55:06 PM PDT 24
Peak memory 248892 kb
Host smart-cc553cd3-3bed-48b0-95ed-4ecbde5f7a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34698
88659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3469888659
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1754836176
Short name T276
Test name
Test status
Simulation time 48878645076 ps
CPU time 2505.97 seconds
Started Mar 24 02:54:25 PM PDT 24
Finished Mar 24 03:36:12 PM PDT 24
Peak memory 289004 kb
Host smart-991110e7-b7f8-44e4-9487-4d15046ce857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754836176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1754836176
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1283392722
Short name T549
Test name
Test status
Simulation time 220501276754 ps
CPU time 2435.2 seconds
Started Mar 24 02:54:27 PM PDT 24
Finished Mar 24 03:35:03 PM PDT 24
Peak memory 272592 kb
Host smart-f8aab27d-e617-4d77-b883-b249c9645640
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283392722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1283392722
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1616885738
Short name T697
Test name
Test status
Simulation time 1516598877 ps
CPU time 18.39 seconds
Started Mar 24 02:54:34 PM PDT 24
Finished Mar 24 02:54:53 PM PDT 24
Peak memory 240668 kb
Host smart-512a6d1b-d8f5-4c50-9ee3-b7543d00b013
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1616885738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1616885738
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3528486628
Short name T677
Test name
Test status
Simulation time 2399036185 ps
CPU time 162.88 seconds
Started Mar 24 02:54:27 PM PDT 24
Finished Mar 24 02:57:10 PM PDT 24
Peak memory 257088 kb
Host smart-b8aeb0a9-c8f9-4a53-8b75-fde514ae7daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35284
86628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3528486628
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1774842057
Short name T468
Test name
Test status
Simulation time 2272801628 ps
CPU time 38.98 seconds
Started Mar 24 02:54:30 PM PDT 24
Finished Mar 24 02:55:09 PM PDT 24
Peak memory 247436 kb
Host smart-ba0dbefd-ce20-4598-9fd9-9d66f280c328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17748
42057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1774842057
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.533181840
Short name T398
Test name
Test status
Simulation time 26115219841 ps
CPU time 1386.1 seconds
Started Mar 24 02:54:31 PM PDT 24
Finished Mar 24 03:17:37 PM PDT 24
Peak memory 283756 kb
Host smart-2389153e-e537-4eec-8e4c-59759a8e4b20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533181840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.533181840
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4119184155
Short name T662
Test name
Test status
Simulation time 166733647 ps
CPU time 5.92 seconds
Started Mar 24 02:54:27 PM PDT 24
Finished Mar 24 02:54:33 PM PDT 24
Peak memory 251124 kb
Host smart-908a7273-cdaf-4141-9a09-382effaf04bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41191
84155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4119184155
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2365780741
Short name T43
Test name
Test status
Simulation time 104778851 ps
CPU time 12.75 seconds
Started Mar 24 02:54:28 PM PDT 24
Finished Mar 24 02:54:41 PM PDT 24
Peak memory 247480 kb
Host smart-735999c9-026a-4709-a547-d96d2861acf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23657
80741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2365780741
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2637826878
Short name T464
Test name
Test status
Simulation time 82131982 ps
CPU time 3.94 seconds
Started Mar 24 02:54:26 PM PDT 24
Finished Mar 24 02:54:30 PM PDT 24
Peak memory 239184 kb
Host smart-a09b10ad-3d32-4817-acd2-cbf6bf45f4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26378
26878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2637826878
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2907323510
Short name T520
Test name
Test status
Simulation time 579612377 ps
CPU time 27.63 seconds
Started Mar 24 02:54:27 PM PDT 24
Finished Mar 24 02:54:55 PM PDT 24
Peak memory 256000 kb
Host smart-cbc5b2ff-514e-47d8-93e0-3ba6d3e79973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29073
23510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2907323510
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2903405633
Short name T230
Test name
Test status
Simulation time 80103776 ps
CPU time 3.5 seconds
Started Mar 24 02:54:36 PM PDT 24
Finished Mar 24 02:54:40 PM PDT 24
Peak memory 249052 kb
Host smart-e548663e-7faf-4d0f-b74c-66c85fe23f8f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2903405633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2903405633
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2708997982
Short name T689
Test name
Test status
Simulation time 14972548424 ps
CPU time 1535.96 seconds
Started Mar 24 02:54:33 PM PDT 24
Finished Mar 24 03:20:09 PM PDT 24
Peak memory 286904 kb
Host smart-8c83ea00-8c8a-4d9d-b585-5553a6293e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708997982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2708997982
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3317043776
Short name T423
Test name
Test status
Simulation time 5636577700 ps
CPU time 60.06 seconds
Started Mar 24 02:54:37 PM PDT 24
Finished Mar 24 02:55:37 PM PDT 24
Peak memory 248960 kb
Host smart-0193c59a-fe8b-400a-8cf4-294b1f72aa6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3317043776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3317043776
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3961309319
Short name T404
Test name
Test status
Simulation time 1005737954 ps
CPU time 16.71 seconds
Started Mar 24 02:54:31 PM PDT 24
Finished Mar 24 02:54:48 PM PDT 24
Peak memory 256716 kb
Host smart-92d3744a-236d-4fb2-86a3-68cc05a3f135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
09319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3961309319
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2004793936
Short name T123
Test name
Test status
Simulation time 152789459 ps
CPU time 4.3 seconds
Started Mar 24 02:54:34 PM PDT 24
Finished Mar 24 02:54:38 PM PDT 24
Peak memory 257048 kb
Host smart-b5353d4f-8233-4438-80aa-4eedd180e4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20047
93936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2004793936
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.184084547
Short name T245
Test name
Test status
Simulation time 193778498784 ps
CPU time 1686.4 seconds
Started Mar 24 02:54:34 PM PDT 24
Finished Mar 24 03:22:41 PM PDT 24
Peak memory 289488 kb
Host smart-ab6c46e5-553b-4de2-87fc-65834e12cee0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184084547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.184084547
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1036471360
Short name T435
Test name
Test status
Simulation time 140655667808 ps
CPU time 2809.79 seconds
Started Mar 24 02:54:35 PM PDT 24
Finished Mar 24 03:41:26 PM PDT 24
Peak memory 288780 kb
Host smart-1805fdf1-f316-40cc-afdc-8ece2d8c8c7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036471360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1036471360
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3710283734
Short name T318
Test name
Test status
Simulation time 68348755900 ps
CPU time 436.39 seconds
Started Mar 24 02:54:31 PM PDT 24
Finished Mar 24 03:01:47 PM PDT 24
Peak memory 247188 kb
Host smart-1fa3eb38-fced-47da-bb3b-a5a51912df20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710283734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3710283734
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3104207931
Short name T449
Test name
Test status
Simulation time 351790193 ps
CPU time 21.26 seconds
Started Mar 24 02:54:31 PM PDT 24
Finished Mar 24 02:54:53 PM PDT 24
Peak memory 254904 kb
Host smart-833f2c9a-db08-4026-be1c-7eb667e747f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31042
07931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3104207931
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3432240916
Short name T664
Test name
Test status
Simulation time 392711499 ps
CPU time 26.25 seconds
Started Mar 24 02:54:33 PM PDT 24
Finished Mar 24 02:54:59 PM PDT 24
Peak memory 256296 kb
Host smart-5e4296eb-ca48-4125-923c-797d188bdc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34322
40916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3432240916
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3406761943
Short name T693
Test name
Test status
Simulation time 116219674 ps
CPU time 14.97 seconds
Started Mar 24 02:54:33 PM PDT 24
Finished Mar 24 02:54:48 PM PDT 24
Peak memory 254596 kb
Host smart-d8ea7e2d-6132-4f76-87a7-4c5a4734f329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067
61943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3406761943
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4231306989
Short name T526
Test name
Test status
Simulation time 3751150923 ps
CPU time 53.3 seconds
Started Mar 24 02:54:32 PM PDT 24
Finished Mar 24 02:55:26 PM PDT 24
Peak memory 256116 kb
Host smart-16d15c37-3509-4ee7-89ac-4d1b827c29ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42313
06989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4231306989
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3834667207
Short name T231
Test name
Test status
Simulation time 38242574 ps
CPU time 2.95 seconds
Started Mar 24 02:54:41 PM PDT 24
Finished Mar 24 02:54:45 PM PDT 24
Peak memory 249088 kb
Host smart-c8bd159e-b00c-4b55-be3f-3cd50149e83f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3834667207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3834667207
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.24658800
Short name T508
Test name
Test status
Simulation time 84550498277 ps
CPU time 2821.13 seconds
Started Mar 24 02:54:38 PM PDT 24
Finished Mar 24 03:41:40 PM PDT 24
Peak memory 273520 kb
Host smart-14a3a0e7-ff33-4b3a-a784-2db6a4c86ac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24658800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.24658800
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3901374420
Short name T552
Test name
Test status
Simulation time 4711272070 ps
CPU time 49.05 seconds
Started Mar 24 02:54:36 PM PDT 24
Finished Mar 24 02:55:26 PM PDT 24
Peak memory 240680 kb
Host smart-2e24364c-67ab-4460-a4f3-0cf697fc21c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3901374420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3901374420
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4029115039
Short name T657
Test name
Test status
Simulation time 3654600330 ps
CPU time 160.3 seconds
Started Mar 24 02:54:36 PM PDT 24
Finished Mar 24 02:57:17 PM PDT 24
Peak memory 256796 kb
Host smart-1342c662-9234-4656-80da-a6c506d01f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40291
15039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4029115039
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.511844107
Short name T673
Test name
Test status
Simulation time 294047094 ps
CPU time 18.3 seconds
Started Mar 24 02:54:36 PM PDT 24
Finished Mar 24 02:54:55 PM PDT 24
Peak memory 248860 kb
Host smart-ebc4101d-04d1-4a94-8810-7ae66f431dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51184
4107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.511844107
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1376839919
Short name T565
Test name
Test status
Simulation time 61944509267 ps
CPU time 3398 seconds
Started Mar 24 02:54:42 PM PDT 24
Finished Mar 24 03:51:20 PM PDT 24
Peak memory 281672 kb
Host smart-674014e1-b0ec-432f-b356-1dc019705654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376839919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1376839919
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1619019220
Short name T331
Test name
Test status
Simulation time 32866601106 ps
CPU time 206.19 seconds
Started Mar 24 02:54:37 PM PDT 24
Finished Mar 24 02:58:04 PM PDT 24
Peak memory 248340 kb
Host smart-dc350e04-b2a5-467e-9885-9e7c602363ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619019220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1619019220
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2273764470
Short name T694
Test name
Test status
Simulation time 350410107 ps
CPU time 28.19 seconds
Started Mar 24 02:54:41 PM PDT 24
Finished Mar 24 02:55:10 PM PDT 24
Peak memory 256056 kb
Host smart-5b1a9e05-3ce7-4b52-9eff-b46224ebbed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22737
64470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2273764470
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2252852693
Short name T646
Test name
Test status
Simulation time 304730524 ps
CPU time 13.66 seconds
Started Mar 24 02:54:42 PM PDT 24
Finished Mar 24 02:54:55 PM PDT 24
Peak memory 254440 kb
Host smart-80e46f4c-2196-42bf-af83-4876d0196838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22528
52693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2252852693
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2948383504
Short name T436
Test name
Test status
Simulation time 56124286 ps
CPU time 2.93 seconds
Started Mar 24 02:54:37 PM PDT 24
Finished Mar 24 02:54:40 PM PDT 24
Peak memory 239196 kb
Host smart-d6a3f1a9-5378-4a71-a227-8b1329466f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29483
83504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2948383504
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3834063904
Short name T638
Test name
Test status
Simulation time 179792789 ps
CPU time 19.37 seconds
Started Mar 24 02:54:37 PM PDT 24
Finished Mar 24 02:54:57 PM PDT 24
Peak memory 256984 kb
Host smart-53320031-73ec-4ab0-be1a-ca75c9712682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38340
63904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3834063904
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.656003146
Short name T100
Test name
Test status
Simulation time 72360394228 ps
CPU time 1237.61 seconds
Started Mar 24 02:54:39 PM PDT 24
Finished Mar 24 03:15:17 PM PDT 24
Peak memory 281716 kb
Host smart-5bb92245-7b14-478b-aaac-96e2826d636d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656003146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.656003146
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3209257174
Short name T59
Test name
Test status
Simulation time 124171914799 ps
CPU time 4571.11 seconds
Started Mar 24 02:54:35 PM PDT 24
Finished Mar 24 04:10:47 PM PDT 24
Peak memory 306312 kb
Host smart-a4fc2d56-d593-47ed-8145-5ebfb8d55a9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209257174 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3209257174
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1839127946
Short name T232
Test name
Test status
Simulation time 139455335 ps
CPU time 3.39 seconds
Started Mar 24 02:54:52 PM PDT 24
Finished Mar 24 02:54:55 PM PDT 24
Peak memory 249096 kb
Host smart-6409859e-12ef-4f3c-b304-2c1e074c92b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1839127946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1839127946
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1485484488
Short name T621
Test name
Test status
Simulation time 99214882052 ps
CPU time 1310.76 seconds
Started Mar 24 02:54:39 PM PDT 24
Finished Mar 24 03:16:30 PM PDT 24
Peak memory 267348 kb
Host smart-42704125-1806-41f7-bab1-5a54fbcafe6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485484488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1485484488
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3768210235
Short name T566
Test name
Test status
Simulation time 497987272 ps
CPU time 22.91 seconds
Started Mar 24 02:54:44 PM PDT 24
Finished Mar 24 02:55:08 PM PDT 24
Peak memory 240616 kb
Host smart-3cee7ec2-597f-4b66-aa2f-ae212dc139b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3768210235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3768210235
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2985152163
Short name T190
Test name
Test status
Simulation time 3429346684 ps
CPU time 38.4 seconds
Started Mar 24 02:54:43 PM PDT 24
Finished Mar 24 02:55:21 PM PDT 24
Peak memory 256084 kb
Host smart-2e56f77f-8449-45e1-a42f-cdedcc18bb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29851
52163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2985152163
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2072123583
Short name T452
Test name
Test status
Simulation time 4822446315 ps
CPU time 69.72 seconds
Started Mar 24 02:54:45 PM PDT 24
Finished Mar 24 02:55:55 PM PDT 24
Peak memory 249148 kb
Host smart-e148a4a9-aae6-4448-ae94-8b5bdf74ec6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
23583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2072123583
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.284295940
Short name T350
Test name
Test status
Simulation time 96570774470 ps
CPU time 2195.85 seconds
Started Mar 24 02:54:46 PM PDT 24
Finished Mar 24 03:31:22 PM PDT 24
Peak memory 270444 kb
Host smart-66c2df96-8acb-4e20-9750-efac39d2ee5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284295940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.284295940
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2075760012
Short name T445
Test name
Test status
Simulation time 28029039676 ps
CPU time 1212.29 seconds
Started Mar 24 02:54:45 PM PDT 24
Finished Mar 24 03:14:57 PM PDT 24
Peak memory 285652 kb
Host smart-33d70a1f-331a-4231-a40c-b352a6709e16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075760012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2075760012
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1394111641
Short name T486
Test name
Test status
Simulation time 2447917155 ps
CPU time 106.2 seconds
Started Mar 24 02:54:44 PM PDT 24
Finished Mar 24 02:56:31 PM PDT 24
Peak memory 248208 kb
Host smart-fcef1a84-8316-45b9-89bb-70cf49f7c2b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394111641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1394111641
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2710404004
Short name T581
Test name
Test status
Simulation time 234139759 ps
CPU time 9.43 seconds
Started Mar 24 02:54:39 PM PDT 24
Finished Mar 24 02:54:49 PM PDT 24
Peak memory 248848 kb
Host smart-7599b786-5261-4ce8-96f1-4e5d502ae707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104
04004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2710404004
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2157805405
Short name T573
Test name
Test status
Simulation time 51651158 ps
CPU time 5 seconds
Started Mar 24 02:54:40 PM PDT 24
Finished Mar 24 02:54:45 PM PDT 24
Peak memory 240656 kb
Host smart-bf054ba9-ea8a-4a79-b510-ad94e5950d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21578
05405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2157805405
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2301136621
Short name T16
Test name
Test status
Simulation time 1194613071 ps
CPU time 39.34 seconds
Started Mar 24 02:54:42 PM PDT 24
Finished Mar 24 02:55:21 PM PDT 24
Peak memory 249048 kb
Host smart-6674e0a9-a461-451e-804c-e291d0240afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23011
36621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2301136621
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3012981182
Short name T704
Test name
Test status
Simulation time 25595644918 ps
CPU time 495.23 seconds
Started Mar 24 02:54:46 PM PDT 24
Finished Mar 24 03:03:01 PM PDT 24
Peak memory 273488 kb
Host smart-df184925-cf86-4b08-bde1-3cfe9530a953
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012981182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3012981182
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3131640066
Short name T39
Test name
Test status
Simulation time 129408353 ps
CPU time 3.23 seconds
Started Mar 24 02:54:56 PM PDT 24
Finished Mar 24 02:54:59 PM PDT 24
Peak memory 249092 kb
Host smart-e0b430aa-2eba-4698-ad3e-a19a69bbc8ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3131640066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3131640066
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3289331025
Short name T494
Test name
Test status
Simulation time 43536474367 ps
CPU time 2717.32 seconds
Started Mar 24 02:54:51 PM PDT 24
Finished Mar 24 03:40:09 PM PDT 24
Peak memory 289432 kb
Host smart-3ef50324-f1ac-4dcf-9d39-096dcbd8cfe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289331025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3289331025
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.215578983
Short name T64
Test name
Test status
Simulation time 467427918 ps
CPU time 22.77 seconds
Started Mar 24 02:54:49 PM PDT 24
Finished Mar 24 02:55:12 PM PDT 24
Peak memory 240668 kb
Host smart-aa727fe4-5f86-4510-90bb-c8798c10e7a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=215578983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.215578983
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1571806415
Short name T671
Test name
Test status
Simulation time 8111655525 ps
CPU time 121.47 seconds
Started Mar 24 02:54:52 PM PDT 24
Finished Mar 24 02:56:54 PM PDT 24
Peak memory 257068 kb
Host smart-1e48ee98-76bb-4fee-9445-b8eb032d9a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
06415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1571806415
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.120617259
Short name T596
Test name
Test status
Simulation time 1755593590 ps
CPU time 45.73 seconds
Started Mar 24 02:54:49 PM PDT 24
Finished Mar 24 02:55:35 PM PDT 24
Peak memory 254776 kb
Host smart-100f62ed-5469-486b-9699-c46e9fad8853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12061
7259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.120617259
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2165821015
Short name T353
Test name
Test status
Simulation time 6808298779 ps
CPU time 633.73 seconds
Started Mar 24 02:54:49 PM PDT 24
Finished Mar 24 03:05:23 PM PDT 24
Peak memory 265508 kb
Host smart-d06ede7a-2241-408a-a68d-12374b4448b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165821015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2165821015
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3317448903
Short name T668
Test name
Test status
Simulation time 6203920801 ps
CPU time 775.18 seconds
Started Mar 24 02:54:51 PM PDT 24
Finished Mar 24 03:07:46 PM PDT 24
Peak memory 273432 kb
Host smart-3597c373-dbe2-4fa6-a579-dde3098e1a03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317448903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3317448903
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.932294281
Short name T330
Test name
Test status
Simulation time 77958469026 ps
CPU time 640.27 seconds
Started Mar 24 02:54:52 PM PDT 24
Finished Mar 24 03:05:33 PM PDT 24
Peak memory 247828 kb
Host smart-490550f0-fedd-45d3-a0b9-5ac76bfe67e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932294281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.932294281
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3757837003
Short name T688
Test name
Test status
Simulation time 402376884 ps
CPU time 35.89 seconds
Started Mar 24 02:54:50 PM PDT 24
Finished Mar 24 02:55:27 PM PDT 24
Peak memory 248860 kb
Host smart-e7bc8225-422b-4dfb-aff1-0b67ff286a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37578
37003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3757837003
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3814514924
Short name T439
Test name
Test status
Simulation time 63590642 ps
CPU time 4.79 seconds
Started Mar 24 02:54:50 PM PDT 24
Finished Mar 24 02:54:56 PM PDT 24
Peak memory 240588 kb
Host smart-6e563fd6-a62c-442e-a3ae-70dec03f3dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38145
14924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3814514924
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2617660706
Short name T251
Test name
Test status
Simulation time 202973405 ps
CPU time 23.73 seconds
Started Mar 24 02:54:52 PM PDT 24
Finished Mar 24 02:55:16 PM PDT 24
Peak memory 256324 kb
Host smart-c75ccaef-860a-426a-87aa-bae65ed84b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26176
60706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2617660706
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4200577162
Short name T507
Test name
Test status
Simulation time 298096723 ps
CPU time 21.79 seconds
Started Mar 24 02:54:51 PM PDT 24
Finished Mar 24 02:55:13 PM PDT 24
Peak memory 248876 kb
Host smart-2087ef4a-f8dd-44f6-8606-c2e53b724333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42005
77162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4200577162
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3565613599
Short name T539
Test name
Test status
Simulation time 46245245785 ps
CPU time 1438.68 seconds
Started Mar 24 02:54:49 PM PDT 24
Finished Mar 24 03:18:48 PM PDT 24
Peak memory 289488 kb
Host smart-850aa3c9-867d-4933-bf0d-65d23065a75d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565613599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3565613599
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2811168771
Short name T227
Test name
Test status
Simulation time 61967633 ps
CPU time 5.3 seconds
Started Mar 24 02:54:58 PM PDT 24
Finished Mar 24 02:55:04 PM PDT 24
Peak memory 249120 kb
Host smart-f6aee4f0-67e5-497b-8b09-72bde3db710d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2811168771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2811168771
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3857773270
Short name T73
Test name
Test status
Simulation time 23296342065 ps
CPU time 698.56 seconds
Started Mar 24 02:54:54 PM PDT 24
Finished Mar 24 03:06:33 PM PDT 24
Peak memory 273516 kb
Host smart-81d6f866-c050-4b93-a828-dfabdc4cbacd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857773270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3857773270
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1737493621
Short name T211
Test name
Test status
Simulation time 268578764 ps
CPU time 14.31 seconds
Started Mar 24 02:54:57 PM PDT 24
Finished Mar 24 02:55:11 PM PDT 24
Peak memory 248844 kb
Host smart-58638671-3aee-4db9-bc3c-adc8f8ae51d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1737493621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1737493621
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.549120911
Short name T602
Test name
Test status
Simulation time 1869212058 ps
CPU time 72.29 seconds
Started Mar 24 02:54:53 PM PDT 24
Finished Mar 24 02:56:06 PM PDT 24
Peak memory 256804 kb
Host smart-56515f3f-3c3d-459d-99e2-a276c9844e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54912
0911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.549120911
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.631297892
Short name T597
Test name
Test status
Simulation time 3487889809 ps
CPU time 49.85 seconds
Started Mar 24 02:54:53 PM PDT 24
Finished Mar 24 02:55:43 PM PDT 24
Peak memory 248916 kb
Host smart-13c8e851-75f5-4b7d-8a68-5c35224fa982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63129
7892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.631297892
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1025049393
Short name T463
Test name
Test status
Simulation time 40281314600 ps
CPU time 1234.6 seconds
Started Mar 24 02:54:55 PM PDT 24
Finished Mar 24 03:15:29 PM PDT 24
Peak memory 289104 kb
Host smart-57daf7c3-6f68-4d5b-b244-a8d6d7321163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025049393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1025049393
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1117154399
Short name T328
Test name
Test status
Simulation time 14574913481 ps
CPU time 153.75 seconds
Started Mar 24 02:54:55 PM PDT 24
Finished Mar 24 02:57:29 PM PDT 24
Peak memory 247932 kb
Host smart-1ed0c337-f856-4668-99a4-64bbb576d294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117154399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1117154399
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4088840678
Short name T491
Test name
Test status
Simulation time 519438001 ps
CPU time 17.47 seconds
Started Mar 24 02:54:57 PM PDT 24
Finished Mar 24 02:55:15 PM PDT 24
Peak memory 248888 kb
Host smart-d3a8c76f-80ab-4ad6-b462-2f86040739d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
40678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4088840678
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4943098
Short name T120
Test name
Test status
Simulation time 549598367 ps
CPU time 16.83 seconds
Started Mar 24 02:54:54 PM PDT 24
Finished Mar 24 02:55:11 PM PDT 24
Peak memory 247388 kb
Host smart-7038a7e7-5dfe-4f57-bf3d-e5e58871582c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49430
98 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4943098
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.919862274
Short name T548
Test name
Test status
Simulation time 352774760 ps
CPU time 24.05 seconds
Started Mar 24 02:54:55 PM PDT 24
Finished Mar 24 02:55:20 PM PDT 24
Peak memory 255912 kb
Host smart-59137be3-7ca2-4191-ae59-45fa25be5991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91986
2274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.919862274
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3961351855
Short name T457
Test name
Test status
Simulation time 199534320 ps
CPU time 6.52 seconds
Started Mar 24 02:54:54 PM PDT 24
Finished Mar 24 02:55:01 PM PDT 24
Peak memory 240636 kb
Host smart-b75b4e1a-0518-4569-bcaa-2c44472f73a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
51855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3961351855
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3985913035
Short name T234
Test name
Test status
Simulation time 45310178 ps
CPU time 4.12 seconds
Started Mar 24 02:55:00 PM PDT 24
Finished Mar 24 02:55:04 PM PDT 24
Peak memory 249116 kb
Host smart-11405c64-3760-4e50-ba80-b764bc796497
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3985913035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3985913035
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.308689427
Short name T60
Test name
Test status
Simulation time 8475252524 ps
CPU time 915.39 seconds
Started Mar 24 02:54:56 PM PDT 24
Finished Mar 24 03:10:12 PM PDT 24
Peak memory 273516 kb
Host smart-a6b8efbd-1706-47d3-8dd2-b66a1ee624b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308689427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.308689427
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3494146268
Short name T440
Test name
Test status
Simulation time 15130602792 ps
CPU time 51.54 seconds
Started Mar 24 02:54:58 PM PDT 24
Finished Mar 24 02:55:50 PM PDT 24
Peak memory 248944 kb
Host smart-a4ba8dfb-41c7-4538-ac20-73729fdc8210
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3494146268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3494146268
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1142712029
Short name T44
Test name
Test status
Simulation time 3161136128 ps
CPU time 186.08 seconds
Started Mar 24 02:55:00 PM PDT 24
Finished Mar 24 02:58:06 PM PDT 24
Peak memory 257068 kb
Host smart-6fbd6e73-b84a-4d53-a74a-bacc7ae0f8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11427
12029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1142712029
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4036123911
Short name T458
Test name
Test status
Simulation time 304381875 ps
CPU time 10.16 seconds
Started Mar 24 02:55:02 PM PDT 24
Finished Mar 24 02:55:12 PM PDT 24
Peak memory 252832 kb
Host smart-53c2c258-b422-4584-907b-d76a3051b137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361
23911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4036123911
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1301551427
Short name T339
Test name
Test status
Simulation time 53481517951 ps
CPU time 1591.82 seconds
Started Mar 24 02:55:00 PM PDT 24
Finished Mar 24 03:21:33 PM PDT 24
Peak memory 265248 kb
Host smart-82c0d848-9705-4832-a279-1b256ecf89bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301551427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1301551427
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.428718489
Short name T78
Test name
Test status
Simulation time 136635798635 ps
CPU time 2328.13 seconds
Started Mar 24 02:55:00 PM PDT 24
Finished Mar 24 03:33:49 PM PDT 24
Peak memory 289868 kb
Host smart-6f9962b3-92a4-445a-a0e7-7fcad17ad514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428718489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.428718489
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3412210280
Short name T7
Test name
Test status
Simulation time 23118063541 ps
CPU time 249.64 seconds
Started Mar 24 02:54:57 PM PDT 24
Finished Mar 24 02:59:07 PM PDT 24
Peak memory 248124 kb
Host smart-a517793d-ebc6-4fd5-b694-e4a71d5e022c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412210280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3412210280
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3422984487
Short name T258
Test name
Test status
Simulation time 369318467 ps
CPU time 20.37 seconds
Started Mar 24 02:55:00 PM PDT 24
Finished Mar 24 02:55:20 PM PDT 24
Peak memory 255672 kb
Host smart-f0d8f60f-07ba-4f4b-ad49-0ebb6e4b5ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34229
84487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3422984487
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2075880738
Short name T107
Test name
Test status
Simulation time 908882829 ps
CPU time 52.06 seconds
Started Mar 24 02:54:59 PM PDT 24
Finished Mar 24 02:55:51 PM PDT 24
Peak memory 255476 kb
Host smart-fce10015-2d14-4eed-a374-e3e1088a9da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20758
80738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2075880738
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.23628479
Short name T121
Test name
Test status
Simulation time 2170912547 ps
CPU time 9.52 seconds
Started Mar 24 02:54:59 PM PDT 24
Finished Mar 24 02:55:09 PM PDT 24
Peak memory 240728 kb
Host smart-a9daad2c-0815-46e7-a992-7f344314a45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23628
479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.23628479
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.35103715
Short name T550
Test name
Test status
Simulation time 397790827 ps
CPU time 12.4 seconds
Started Mar 24 02:55:05 PM PDT 24
Finished Mar 24 02:55:18 PM PDT 24
Peak memory 248876 kb
Host smart-8cbcbb05-3771-473e-8269-831ba6dcaca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35103
715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.35103715
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1048180110
Short name T631
Test name
Test status
Simulation time 17054655418 ps
CPU time 1446.75 seconds
Started Mar 24 02:55:00 PM PDT 24
Finished Mar 24 03:19:07 PM PDT 24
Peak memory 289732 kb
Host smart-203a81b9-b16b-4cb7-94b3-fb6bbb99eabc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048180110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1048180110
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.4137303392
Short name T223
Test name
Test status
Simulation time 359329237 ps
CPU time 3.61 seconds
Started Mar 24 02:53:52 PM PDT 24
Finished Mar 24 02:53:56 PM PDT 24
Peak memory 249076 kb
Host smart-ba7aab8d-ee6e-4946-99a1-ad9599f96e9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4137303392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4137303392
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3762114059
Short name T29
Test name
Test status
Simulation time 151696494298 ps
CPU time 2561.77 seconds
Started Mar 24 02:53:54 PM PDT 24
Finished Mar 24 03:36:36 PM PDT 24
Peak memory 273504 kb
Host smart-2e5a8683-8432-4d43-9304-04f4b700dbf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762114059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3762114059
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1550995597
Short name T416
Test name
Test status
Simulation time 843346889 ps
CPU time 12.27 seconds
Started Mar 24 02:53:53 PM PDT 24
Finished Mar 24 02:54:05 PM PDT 24
Peak memory 240652 kb
Host smart-1d2a40a9-d2d8-4984-94d5-02d7a80e7d3f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1550995597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1550995597
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1063417275
Short name T425
Test name
Test status
Simulation time 4990300866 ps
CPU time 288.97 seconds
Started Mar 24 02:53:53 PM PDT 24
Finished Mar 24 02:58:43 PM PDT 24
Peak memory 256924 kb
Host smart-c3093450-4e2c-4d87-a83a-a373d9ffc568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10634
17275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1063417275
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1824921001
Short name T546
Test name
Test status
Simulation time 272176783 ps
CPU time 32.29 seconds
Started Mar 24 02:53:54 PM PDT 24
Finished Mar 24 02:54:26 PM PDT 24
Peak memory 248860 kb
Host smart-cc4bfdfa-5a5d-4c75-9c7b-02e673ac3295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249
21001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1824921001
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3979329282
Short name T571
Test name
Test status
Simulation time 19075881057 ps
CPU time 1217.46 seconds
Started Mar 24 02:53:56 PM PDT 24
Finished Mar 24 03:14:14 PM PDT 24
Peak memory 272568 kb
Host smart-62590c53-c683-47a0-8813-fcee018035de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979329282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3979329282
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1663756682
Short name T329
Test name
Test status
Simulation time 77778104691 ps
CPU time 191.81 seconds
Started Mar 24 02:53:52 PM PDT 24
Finished Mar 24 02:57:04 PM PDT 24
Peak memory 247900 kb
Host smart-349a35c1-6995-4c4e-856f-271d7f5802d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663756682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1663756682
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2938197928
Short name T610
Test name
Test status
Simulation time 254336611 ps
CPU time 5.21 seconds
Started Mar 24 02:53:53 PM PDT 24
Finished Mar 24 02:53:58 PM PDT 24
Peak memory 240656 kb
Host smart-459eaba9-5d9a-4971-83d9-ab210c5a1cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
97928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2938197928
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2931026365
Short name T301
Test name
Test status
Simulation time 878553039 ps
CPU time 25.21 seconds
Started Mar 24 02:53:52 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 256340 kb
Host smart-d2f98756-b15e-41aa-b887-0f8443626770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
26365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2931026365
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.790812445
Short name T11
Test name
Test status
Simulation time 3450546775 ps
CPU time 21.75 seconds
Started Mar 24 02:53:52 PM PDT 24
Finished Mar 24 02:54:14 PM PDT 24
Peak memory 273476 kb
Host smart-9b91d723-0f44-41e3-aba5-95ba05010237
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=790812445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.790812445
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2006857859
Short name T68
Test name
Test status
Simulation time 10501350343 ps
CPU time 37.19 seconds
Started Mar 24 02:53:56 PM PDT 24
Finished Mar 24 02:54:33 PM PDT 24
Peak memory 256052 kb
Host smart-144372d3-46af-4cc8-af5f-f1b1cff4b694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20068
57859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2006857859
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3308848947
Short name T67
Test name
Test status
Simulation time 801508947 ps
CPU time 49.49 seconds
Started Mar 24 02:53:51 PM PDT 24
Finished Mar 24 02:54:41 PM PDT 24
Peak memory 256092 kb
Host smart-51d6de1a-d61c-49f7-9f27-72bc3a255ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33088
48947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3308848947
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.265636381
Short name T644
Test name
Test status
Simulation time 61308586984 ps
CPU time 1339.5 seconds
Started Mar 24 02:55:05 PM PDT 24
Finished Mar 24 03:17:25 PM PDT 24
Peak memory 289360 kb
Host smart-914b4c10-ef4b-4b58-b267-cbb79387babf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265636381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.265636381
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.589894721
Short name T579
Test name
Test status
Simulation time 13255015407 ps
CPU time 131.29 seconds
Started Mar 24 02:55:05 PM PDT 24
Finished Mar 24 02:57:16 PM PDT 24
Peak memory 256884 kb
Host smart-ba072159-aab5-4b1a-a51d-7b1ef0eda7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58989
4721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.589894721
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.821949249
Short name T462
Test name
Test status
Simulation time 168365881 ps
CPU time 16.87 seconds
Started Mar 24 02:55:05 PM PDT 24
Finished Mar 24 02:55:22 PM PDT 24
Peak memory 249252 kb
Host smart-1b9fccf1-e3b8-4240-9fc0-ab0563c4e9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82194
9249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.821949249
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3169608130
Short name T618
Test name
Test status
Simulation time 165594458699 ps
CPU time 1788.56 seconds
Started Mar 24 02:55:04 PM PDT 24
Finished Mar 24 03:24:53 PM PDT 24
Peak memory 271776 kb
Host smart-c524f6d5-7918-450a-a16b-dbdf84422b9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169608130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3169608130
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1676914689
Short name T623
Test name
Test status
Simulation time 6332040085 ps
CPU time 82.07 seconds
Started Mar 24 02:55:03 PM PDT 24
Finished Mar 24 02:56:26 PM PDT 24
Peak memory 249060 kb
Host smart-0f550065-0764-40f7-bafe-d4015def0c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
14689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1676914689
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.100986872
Short name T417
Test name
Test status
Simulation time 5110023361 ps
CPU time 67.96 seconds
Started Mar 24 02:55:03 PM PDT 24
Finished Mar 24 02:56:11 PM PDT 24
Peak memory 247956 kb
Host smart-0daef118-7002-48a7-8875-84d0dbca180d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10098
6872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.100986872
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.4263298457
Short name T379
Test name
Test status
Simulation time 562028842 ps
CPU time 17.32 seconds
Started Mar 24 02:55:07 PM PDT 24
Finished Mar 24 02:55:25 PM PDT 24
Peak memory 248980 kb
Host smart-dc4c91d4-8f00-49a1-8526-35f89a2521fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42632
98457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4263298457
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2144769015
Short name T687
Test name
Test status
Simulation time 97806655756 ps
CPU time 1426.82 seconds
Started Mar 24 02:55:04 PM PDT 24
Finished Mar 24 03:18:52 PM PDT 24
Peak memory 272456 kb
Host smart-385abf5c-3899-46d1-95a3-032d6bcbcb4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144769015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2144769015
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1727155546
Short name T519
Test name
Test status
Simulation time 11107497417 ps
CPU time 298.13 seconds
Started Mar 24 02:55:06 PM PDT 24
Finished Mar 24 03:00:05 PM PDT 24
Peak memory 256804 kb
Host smart-c424149b-a90f-4892-b935-1f8d171479c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17271
55546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1727155546
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1014974741
Short name T407
Test name
Test status
Simulation time 3840490224 ps
CPU time 57.33 seconds
Started Mar 24 02:55:04 PM PDT 24
Finished Mar 24 02:56:02 PM PDT 24
Peak memory 255748 kb
Host smart-9017841c-3d18-4f1f-b39f-af283c33674b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10149
74741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1014974741
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1064021156
Short name T523
Test name
Test status
Simulation time 26083402689 ps
CPU time 1241.69 seconds
Started Mar 24 02:55:09 PM PDT 24
Finished Mar 24 03:15:51 PM PDT 24
Peak memory 288972 kb
Host smart-6df7465a-3c5c-467e-9cd7-f4c6462f2c85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064021156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1064021156
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2064490499
Short name T628
Test name
Test status
Simulation time 18109080149 ps
CPU time 1358.49 seconds
Started Mar 24 02:55:08 PM PDT 24
Finished Mar 24 03:17:47 PM PDT 24
Peak memory 289480 kb
Host smart-577086b5-7200-41a8-b06b-652fed97dde2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064490499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2064490499
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3445456867
Short name T509
Test name
Test status
Simulation time 8261434171 ps
CPU time 340.67 seconds
Started Mar 24 02:55:13 PM PDT 24
Finished Mar 24 03:00:54 PM PDT 24
Peak memory 247972 kb
Host smart-0e118917-870a-43cc-8e34-71ffe4d95d27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445456867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3445456867
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.453846824
Short name T384
Test name
Test status
Simulation time 2168223056 ps
CPU time 21.13 seconds
Started Mar 24 02:55:02 PM PDT 24
Finished Mar 24 02:55:24 PM PDT 24
Peak memory 248936 kb
Host smart-d281b325-bffc-4eda-bf9b-b0537ba2db69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45384
6824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.453846824
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.159379489
Short name T31
Test name
Test status
Simulation time 121887108 ps
CPU time 15.35 seconds
Started Mar 24 02:55:06 PM PDT 24
Finished Mar 24 02:55:21 PM PDT 24
Peak memory 255216 kb
Host smart-3a916121-4865-481f-9c52-b2cd23482020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
9489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.159379489
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.4135305318
Short name T62
Test name
Test status
Simulation time 645292683 ps
CPU time 23.92 seconds
Started Mar 24 02:55:03 PM PDT 24
Finished Mar 24 02:55:27 PM PDT 24
Peak memory 249140 kb
Host smart-4498e10f-0164-48ee-b182-07ae920bae6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41353
05318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4135305318
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1434351507
Short name T91
Test name
Test status
Simulation time 39641539685 ps
CPU time 2531.55 seconds
Started Mar 24 02:55:11 PM PDT 24
Finished Mar 24 03:37:23 PM PDT 24
Peak memory 281776 kb
Host smart-b32baecd-e5b7-4f64-b49a-09f0ca83fbd1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434351507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1434351507
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2819908969
Short name T56
Test name
Test status
Simulation time 22830024519 ps
CPU time 1814.74 seconds
Started Mar 24 02:55:10 PM PDT 24
Finished Mar 24 03:25:25 PM PDT 24
Peak memory 286652 kb
Host smart-f7b5a98f-ac50-4b2e-8cf3-1f438fd7484e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819908969 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2819908969
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1968552077
Short name T542
Test name
Test status
Simulation time 114527080493 ps
CPU time 1851.66 seconds
Started Mar 24 02:55:13 PM PDT 24
Finished Mar 24 03:26:05 PM PDT 24
Peak memory 282324 kb
Host smart-72b13799-a0c0-429a-8d97-ccc5e28d6cf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968552077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1968552077
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3991216769
Short name T373
Test name
Test status
Simulation time 31215985349 ps
CPU time 347.33 seconds
Started Mar 24 02:55:09 PM PDT 24
Finished Mar 24 03:00:57 PM PDT 24
Peak memory 256708 kb
Host smart-e99d3c4b-5b0f-479c-a2a1-22c3414dcc20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39912
16769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3991216769
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4092128968
Short name T651
Test name
Test status
Simulation time 744011059 ps
CPU time 20.03 seconds
Started Mar 24 02:55:09 PM PDT 24
Finished Mar 24 02:55:30 PM PDT 24
Peak memory 255624 kb
Host smart-4d199df5-156e-4b90-b9af-a84446744ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40921
28968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4092128968
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.346066313
Short name T114
Test name
Test status
Simulation time 19912576257 ps
CPU time 1285.76 seconds
Started Mar 24 02:55:07 PM PDT 24
Finished Mar 24 03:16:34 PM PDT 24
Peak memory 265316 kb
Host smart-bc80189b-ead0-4f2b-8c39-334b31b30fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346066313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.346066313
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3119105643
Short name T574
Test name
Test status
Simulation time 16740212272 ps
CPU time 500.41 seconds
Started Mar 24 02:55:11 PM PDT 24
Finished Mar 24 03:03:31 PM PDT 24
Peak memory 255960 kb
Host smart-3884d0f2-3639-4201-ae08-6b7760b831c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119105643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3119105643
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.743882312
Short name T385
Test name
Test status
Simulation time 473780443 ps
CPU time 16.98 seconds
Started Mar 24 02:55:08 PM PDT 24
Finished Mar 24 02:55:25 PM PDT 24
Peak memory 248860 kb
Host smart-ef8cf803-89b2-4881-9834-475c33ef8ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74388
2312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.743882312
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1975170283
Short name T57
Test name
Test status
Simulation time 1003960302 ps
CPU time 64.46 seconds
Started Mar 24 02:55:12 PM PDT 24
Finished Mar 24 02:56:17 PM PDT 24
Peak memory 256100 kb
Host smart-e7f32b6a-197a-47ba-8764-d708af761f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
70283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1975170283
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.250008248
Short name T459
Test name
Test status
Simulation time 1230920825 ps
CPU time 21.23 seconds
Started Mar 24 02:55:09 PM PDT 24
Finished Mar 24 02:55:30 PM PDT 24
Peak memory 248884 kb
Host smart-5bcaa2f4-c817-4ddd-9bc8-9f0104daf70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000
8248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.250008248
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2953784764
Short name T442
Test name
Test status
Simulation time 1966258444 ps
CPU time 22.69 seconds
Started Mar 24 02:55:09 PM PDT 24
Finished Mar 24 02:55:32 PM PDT 24
Peak memory 257020 kb
Host smart-34335f90-6e3c-4efc-9a81-3d19f6241d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
84764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2953784764
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3000622087
Short name T294
Test name
Test status
Simulation time 9039901877 ps
CPU time 486.52 seconds
Started Mar 24 02:55:10 PM PDT 24
Finished Mar 24 03:03:17 PM PDT 24
Peak memory 257104 kb
Host smart-765103ca-a23c-4074-8ef1-b4fd1377b7d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000622087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3000622087
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.16854876
Short name T625
Test name
Test status
Simulation time 10931257638 ps
CPU time 1277.6 seconds
Started Mar 24 02:55:12 PM PDT 24
Finished Mar 24 03:16:30 PM PDT 24
Peak memory 281424 kb
Host smart-b8fdd2db-55f7-4961-b02c-0d5e2ac1861f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16854876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.16854876
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3316252012
Short name T19
Test name
Test status
Simulation time 676167421 ps
CPU time 56.35 seconds
Started Mar 24 02:55:13 PM PDT 24
Finished Mar 24 02:56:09 PM PDT 24
Peak memory 248808 kb
Host smart-1ab7ae9c-0945-4b58-982c-2d401a1c7304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33162
52012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3316252012
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1922618993
Short name T369
Test name
Test status
Simulation time 269902687 ps
CPU time 4.68 seconds
Started Mar 24 02:55:15 PM PDT 24
Finished Mar 24 02:55:20 PM PDT 24
Peak memory 239232 kb
Host smart-0f7be961-a0d1-4804-bca5-1ba1e7a11b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19226
18993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1922618993
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.528450717
Short name T354
Test name
Test status
Simulation time 135857500460 ps
CPU time 1943.48 seconds
Started Mar 24 02:55:12 PM PDT 24
Finished Mar 24 03:27:36 PM PDT 24
Peak memory 282740 kb
Host smart-6b5545a9-d0d9-4840-803e-ecd014f85877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528450717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.528450717
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.21146117
Short name T15
Test name
Test status
Simulation time 72556506002 ps
CPU time 3367.97 seconds
Started Mar 24 02:55:14 PM PDT 24
Finished Mar 24 03:51:23 PM PDT 24
Peak memory 289628 kb
Host smart-bdfe88e8-4296-4502-adc1-88bb15675d9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21146117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.21146117
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.620868818
Short name T658
Test name
Test status
Simulation time 664349889 ps
CPU time 38.96 seconds
Started Mar 24 02:55:10 PM PDT 24
Finished Mar 24 02:55:49 PM PDT 24
Peak memory 248844 kb
Host smart-1dfda603-1fd7-4839-a93e-140227164cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62086
8818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.620868818
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3341397416
Short name T366
Test name
Test status
Simulation time 2102647577 ps
CPU time 37.92 seconds
Started Mar 24 02:55:15 PM PDT 24
Finished Mar 24 02:55:53 PM PDT 24
Peak memory 248660 kb
Host smart-cba690eb-d37c-444e-a279-a7a6b91236a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
97416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3341397416
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.734389660
Short name T420
Test name
Test status
Simulation time 231405445 ps
CPU time 14.37 seconds
Started Mar 24 02:55:11 PM PDT 24
Finished Mar 24 02:55:26 PM PDT 24
Peak memory 248864 kb
Host smart-1e5ff152-4c60-4653-8800-d3af75af3e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73438
9660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.734389660
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.813132625
Short name T469
Test name
Test status
Simulation time 17061448 ps
CPU time 3.01 seconds
Started Mar 24 02:55:12 PM PDT 24
Finished Mar 24 02:55:15 PM PDT 24
Peak memory 240624 kb
Host smart-c87f9e1c-ef25-4585-9b62-ff72285ba4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81313
2625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.813132625
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.202819658
Short name T54
Test name
Test status
Simulation time 2898679974 ps
CPU time 242.4 seconds
Started Mar 24 02:55:12 PM PDT 24
Finished Mar 24 02:59:15 PM PDT 24
Peak memory 257116 kb
Host smart-3719ef16-961b-441d-aabc-251dd7b5d970
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202819658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.202819658
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1848928904
Short name T217
Test name
Test status
Simulation time 168763423367 ps
CPU time 9024.33 seconds
Started Mar 24 02:55:17 PM PDT 24
Finished Mar 24 05:25:42 PM PDT 24
Peak memory 394164 kb
Host smart-fee55832-87c8-4cc2-b596-3aa6386f9be4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848928904 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1848928904
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.45240939
Short name T564
Test name
Test status
Simulation time 1080229204 ps
CPU time 21.98 seconds
Started Mar 24 02:55:16 PM PDT 24
Finished Mar 24 02:55:38 PM PDT 24
Peak memory 255996 kb
Host smart-31a6176c-5c8c-40e4-ab03-36329f084098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45240
939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.45240939
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3590691603
Short name T87
Test name
Test status
Simulation time 803042575 ps
CPU time 23.77 seconds
Started Mar 24 02:55:16 PM PDT 24
Finished Mar 24 02:55:40 PM PDT 24
Peak memory 255468 kb
Host smart-9176fc9b-7c28-43f8-b481-8b7047c6ca9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
91603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3590691603
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1819117277
Short name T99
Test name
Test status
Simulation time 40074250610 ps
CPU time 1219.03 seconds
Started Mar 24 02:55:19 PM PDT 24
Finished Mar 24 03:15:39 PM PDT 24
Peak memory 272844 kb
Host smart-a535e19e-2c61-4a6b-9a9a-c6c4af441cac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819117277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1819117277
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.605324481
Short name T209
Test name
Test status
Simulation time 3713122645 ps
CPU time 157.87 seconds
Started Mar 24 02:55:20 PM PDT 24
Finished Mar 24 02:57:59 PM PDT 24
Peak memory 247844 kb
Host smart-e581f749-0293-4473-a894-52910e199344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605324481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.605324481
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.199502362
Short name T65
Test name
Test status
Simulation time 202021360 ps
CPU time 12.36 seconds
Started Mar 24 02:55:24 PM PDT 24
Finished Mar 24 02:55:36 PM PDT 24
Peak memory 254100 kb
Host smart-f6669992-89a6-4ee9-a3a9-e00af6b5d27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19950
2362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.199502362
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3356629058
Short name T429
Test name
Test status
Simulation time 3626739015 ps
CPU time 58.6 seconds
Started Mar 24 02:55:18 PM PDT 24
Finished Mar 24 02:56:17 PM PDT 24
Peak memory 248888 kb
Host smart-67425ca5-09c3-4f42-af95-2e74b01626c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33566
29058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3356629058
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.319704201
Short name T75
Test name
Test status
Simulation time 640008582 ps
CPU time 41.17 seconds
Started Mar 24 02:55:19 PM PDT 24
Finished Mar 24 02:56:01 PM PDT 24
Peak memory 248880 kb
Host smart-9a0567ee-54eb-4f92-8f54-d23453a4fe4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31970
4201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.319704201
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1264087980
Short name T506
Test name
Test status
Simulation time 2409410285 ps
CPU time 76.43 seconds
Started Mar 24 02:55:18 PM PDT 24
Finished Mar 24 02:56:36 PM PDT 24
Peak memory 255988 kb
Host smart-e910d66c-c26d-4db1-9f6d-93217767a1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12640
87980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1264087980
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1314787937
Short name T61
Test name
Test status
Simulation time 165166651166 ps
CPU time 2204.97 seconds
Started Mar 24 02:55:17 PM PDT 24
Finished Mar 24 03:32:03 PM PDT 24
Peak memory 287048 kb
Host smart-4c8b6dff-450a-4258-9fc2-58f1579f4fbc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314787937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1314787937
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3021862238
Short name T405
Test name
Test status
Simulation time 29976955777 ps
CPU time 1360.84 seconds
Started Mar 24 02:55:22 PM PDT 24
Finished Mar 24 03:18:03 PM PDT 24
Peak memory 288288 kb
Host smart-48d4baf8-52f7-4c58-9494-a0b8e067839d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021862238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3021862238
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3707035519
Short name T652
Test name
Test status
Simulation time 3730324841 ps
CPU time 192.95 seconds
Started Mar 24 02:55:22 PM PDT 24
Finished Mar 24 02:58:35 PM PDT 24
Peak memory 256852 kb
Host smart-62754fdb-f357-4915-8265-bcde357dfe18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37070
35519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3707035519
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3285746432
Short name T40
Test name
Test status
Simulation time 181038039 ps
CPU time 13 seconds
Started Mar 24 02:55:24 PM PDT 24
Finished Mar 24 02:55:37 PM PDT 24
Peak memory 252416 kb
Host smart-08272279-b6e7-4728-9967-bce1356af062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32857
46432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3285746432
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1951495944
Short name T341
Test name
Test status
Simulation time 33374234820 ps
CPU time 2474.1 seconds
Started Mar 24 02:55:25 PM PDT 24
Finished Mar 24 03:36:40 PM PDT 24
Peak memory 281688 kb
Host smart-1ef25e51-0eeb-41c2-8575-3ee04976c363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951495944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1951495944
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1108921813
Short name T377
Test name
Test status
Simulation time 429519320076 ps
CPU time 2636.28 seconds
Started Mar 24 02:55:30 PM PDT 24
Finished Mar 24 03:39:27 PM PDT 24
Peak memory 289384 kb
Host smart-8ce685b0-c576-417f-a079-aed203da733a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108921813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1108921813
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3649506281
Short name T334
Test name
Test status
Simulation time 17796130390 ps
CPU time 350.95 seconds
Started Mar 24 02:55:22 PM PDT 24
Finished Mar 24 03:01:13 PM PDT 24
Peak memory 247828 kb
Host smart-935ccb19-9e0a-4d20-98ff-4219791b1c07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649506281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3649506281
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1503641869
Short name T412
Test name
Test status
Simulation time 283895964 ps
CPU time 32.84 seconds
Started Mar 24 02:55:26 PM PDT 24
Finished Mar 24 02:55:59 PM PDT 24
Peak memory 255732 kb
Host smart-4af826c6-e67e-4412-a701-569c870fb570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15036
41869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1503641869
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2228297436
Short name T616
Test name
Test status
Simulation time 3309228936 ps
CPU time 54.97 seconds
Started Mar 24 02:55:22 PM PDT 24
Finished Mar 24 02:56:17 PM PDT 24
Peak memory 254948 kb
Host smart-6c4af693-fb93-494c-95ca-edb1c2e898df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
97436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2228297436
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1287233841
Short name T84
Test name
Test status
Simulation time 3387201813 ps
CPU time 60.21 seconds
Started Mar 24 02:55:23 PM PDT 24
Finished Mar 24 02:56:23 PM PDT 24
Peak memory 257080 kb
Host smart-77d117a5-6e93-4edf-8953-78429310b181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872
33841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1287233841
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2459452984
Short name T483
Test name
Test status
Simulation time 255651449 ps
CPU time 22.19 seconds
Started Mar 24 02:55:21 PM PDT 24
Finished Mar 24 02:55:44 PM PDT 24
Peak memory 248924 kb
Host smart-34c19bd3-589f-4176-9fa3-e1ac90d0bef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24594
52984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2459452984
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.574249071
Short name T26
Test name
Test status
Simulation time 56508667499 ps
CPU time 1648.76 seconds
Started Mar 24 02:55:28 PM PDT 24
Finished Mar 24 03:22:57 PM PDT 24
Peak memory 272672 kb
Host smart-90b94381-eb73-4e7e-9180-0d58839cb12c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574249071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.574249071
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1836139417
Short name T66
Test name
Test status
Simulation time 56801070741 ps
CPU time 1341.41 seconds
Started Mar 24 02:55:25 PM PDT 24
Finished Mar 24 03:17:47 PM PDT 24
Peak memory 289404 kb
Host smart-714b1f05-51c3-43be-8e64-3b989b7f76e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836139417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1836139417
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1590054001
Short name T626
Test name
Test status
Simulation time 5867667906 ps
CPU time 88.76 seconds
Started Mar 24 02:55:27 PM PDT 24
Finished Mar 24 02:56:55 PM PDT 24
Peak memory 249080 kb
Host smart-a4d4ff9d-472e-4790-b100-ae520a06e847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
54001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1590054001
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.636356445
Short name T605
Test name
Test status
Simulation time 3765364934 ps
CPU time 66.12 seconds
Started Mar 24 02:55:29 PM PDT 24
Finished Mar 24 02:56:35 PM PDT 24
Peak memory 256804 kb
Host smart-4eba9da2-3d5e-4fac-be1b-c5608a97f51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63635
6445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.636356445
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1133036478
Short name T338
Test name
Test status
Simulation time 33270843008 ps
CPU time 1820.07 seconds
Started Mar 24 02:55:25 PM PDT 24
Finished Mar 24 03:25:46 PM PDT 24
Peak memory 269624 kb
Host smart-061e23fc-1768-4e31-ad83-bea3cbd61d69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133036478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1133036478
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.208071659
Short name T248
Test name
Test status
Simulation time 14287634925 ps
CPU time 1276.29 seconds
Started Mar 24 02:55:27 PM PDT 24
Finished Mar 24 03:16:44 PM PDT 24
Peak memory 286812 kb
Host smart-f65c1456-2fbe-411c-aa18-15f36d05a500
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208071659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.208071659
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.807302894
Short name T327
Test name
Test status
Simulation time 6832334056 ps
CPU time 266.71 seconds
Started Mar 24 02:55:25 PM PDT 24
Finished Mar 24 02:59:52 PM PDT 24
Peak memory 247824 kb
Host smart-af956b5c-866b-4805-a45c-81b1f342ed12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807302894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.807302894
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4286269125
Short name T246
Test name
Test status
Simulation time 781459635 ps
CPU time 51.8 seconds
Started Mar 24 02:55:29 PM PDT 24
Finished Mar 24 02:56:21 PM PDT 24
Peak memory 248748 kb
Host smart-ae156b7d-5649-45b1-8243-1b93957cd97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42862
69125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4286269125
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.164764511
Short name T556
Test name
Test status
Simulation time 3591234482 ps
CPU time 60.44 seconds
Started Mar 24 02:55:30 PM PDT 24
Finished Mar 24 02:56:31 PM PDT 24
Peak memory 255544 kb
Host smart-2b619ce6-564c-4196-aace-70070a09cc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
4511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.164764511
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.798919818
Short name T448
Test name
Test status
Simulation time 2820328819 ps
CPU time 50.16 seconds
Started Mar 24 02:55:27 PM PDT 24
Finished Mar 24 02:56:17 PM PDT 24
Peak memory 256216 kb
Host smart-3e681a4c-b936-4a1a-8a5d-7cd921e6bcae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79891
9818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.798919818
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.79435929
Short name T253
Test name
Test status
Simulation time 160835684 ps
CPU time 13.18 seconds
Started Mar 24 02:55:30 PM PDT 24
Finished Mar 24 02:55:43 PM PDT 24
Peak memory 248900 kb
Host smart-bf29299c-01af-429b-bbc5-62f38e1c10c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79435
929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.79435929
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3439922091
Short name T269
Test name
Test status
Simulation time 142930028197 ps
CPU time 1215.28 seconds
Started Mar 24 02:55:30 PM PDT 24
Finished Mar 24 03:15:45 PM PDT 24
Peak memory 272092 kb
Host smart-86506814-2660-4776-8273-bd320cdc946c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439922091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3439922091
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1843941692
Short name T93
Test name
Test status
Simulation time 170810983650 ps
CPU time 5875.37 seconds
Started Mar 24 02:55:26 PM PDT 24
Finished Mar 24 04:33:22 PM PDT 24
Peak memory 314508 kb
Host smart-a953c0f9-9f2e-436d-8111-24f56b4a3572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843941692 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1843941692
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3019574294
Short name T291
Test name
Test status
Simulation time 119789119029 ps
CPU time 1854.97 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 03:26:26 PM PDT 24
Peak memory 272844 kb
Host smart-c6b2450d-bdec-4d31-a080-f7701136bdf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019574294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3019574294
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2430088332
Short name T74
Test name
Test status
Simulation time 204235464 ps
CPU time 22.69 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 02:55:54 PM PDT 24
Peak memory 256620 kb
Host smart-6f9ff0c2-427a-4a06-aedf-f026cd4cca48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24300
88332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2430088332
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2558149081
Short name T695
Test name
Test status
Simulation time 3365405402 ps
CPU time 54.5 seconds
Started Mar 24 02:55:32 PM PDT 24
Finished Mar 24 02:56:27 PM PDT 24
Peak memory 249236 kb
Host smart-fe2b6fe7-38e8-45db-86a9-d032bddee44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25581
49081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2558149081
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1481641356
Short name T309
Test name
Test status
Simulation time 226256605651 ps
CPU time 1837.03 seconds
Started Mar 24 02:55:32 PM PDT 24
Finished Mar 24 03:26:09 PM PDT 24
Peak memory 272792 kb
Host smart-a72149f7-b7f7-44da-9256-3ca51821034e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481641356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1481641356
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2352981251
Short name T531
Test name
Test status
Simulation time 42133075612 ps
CPU time 2559.22 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 03:38:11 PM PDT 24
Peak memory 281656 kb
Host smart-04fb8603-cc5a-449e-b6e4-151b5bfbbfd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352981251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2352981251
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.460219236
Short name T321
Test name
Test status
Simulation time 95469800548 ps
CPU time 602.53 seconds
Started Mar 24 02:55:32 PM PDT 24
Finished Mar 24 03:05:35 PM PDT 24
Peak memory 248060 kb
Host smart-47dc7692-8c2e-4e67-815f-5c76ff48a2d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460219236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.460219236
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3703463752
Short name T636
Test name
Test status
Simulation time 633312794 ps
CPU time 34.65 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 02:56:06 PM PDT 24
Peak memory 256080 kb
Host smart-86c4c522-7015-42da-9486-d64ae9dfe1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034
63752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3703463752
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.810297517
Short name T510
Test name
Test status
Simulation time 1920937134 ps
CPU time 32.4 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 02:56:04 PM PDT 24
Peak memory 249196 kb
Host smart-3eff46c3-4d7c-4920-87df-9c416a683fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81029
7517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.810297517
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2063729520
Short name T679
Test name
Test status
Simulation time 787922487 ps
CPU time 21.5 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 02:55:52 PM PDT 24
Peak memory 255720 kb
Host smart-9305241d-647e-4556-a0c1-1c106d81cca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20637
29520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2063729520
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.451112624
Short name T94
Test name
Test status
Simulation time 5036802588 ps
CPU time 77.13 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 02:56:49 PM PDT 24
Peak memory 256232 kb
Host smart-0e90d674-bdb4-4ace-bc55-a6a49cfbcb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45111
2624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.451112624
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3082134686
Short name T274
Test name
Test status
Simulation time 7107776076 ps
CPU time 370.16 seconds
Started Mar 24 02:55:31 PM PDT 24
Finished Mar 24 03:01:41 PM PDT 24
Peak memory 255780 kb
Host smart-3cb07ccf-2545-4d1e-976c-729c07358df4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082134686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3082134686
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.527396950
Short name T654
Test name
Test status
Simulation time 13219234407 ps
CPU time 959.1 seconds
Started Mar 24 02:55:36 PM PDT 24
Finished Mar 24 03:11:35 PM PDT 24
Peak memory 269704 kb
Host smart-56fd4222-9aef-472f-8663-39e7125d68a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527396950 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.527396950
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3417002515
Short name T72
Test name
Test status
Simulation time 70343719100 ps
CPU time 1294.57 seconds
Started Mar 24 02:55:36 PM PDT 24
Finished Mar 24 03:17:11 PM PDT 24
Peak memory 284764 kb
Host smart-451d0c12-7456-48a9-9312-bd77db1b957e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417002515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3417002515
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1349436560
Short name T582
Test name
Test status
Simulation time 7359963639 ps
CPU time 122.31 seconds
Started Mar 24 02:55:35 PM PDT 24
Finished Mar 24 02:57:38 PM PDT 24
Peak memory 256680 kb
Host smart-827e4694-6c44-4445-aff0-f5928d4300d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13494
36560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1349436560
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1555957212
Short name T372
Test name
Test status
Simulation time 44994813 ps
CPU time 4.24 seconds
Started Mar 24 02:55:41 PM PDT 24
Finished Mar 24 02:55:46 PM PDT 24
Peak memory 240672 kb
Host smart-02503ad8-ae66-41e3-9a78-f685c72a817f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15559
57212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1555957212
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2872757695
Short name T544
Test name
Test status
Simulation time 63267354208 ps
CPU time 1928.58 seconds
Started Mar 24 02:55:40 PM PDT 24
Finished Mar 24 03:27:49 PM PDT 24
Peak memory 273388 kb
Host smart-5e74ca22-3808-462b-8613-efe2d802dc54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872757695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2872757695
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3978645604
Short name T702
Test name
Test status
Simulation time 18419301417 ps
CPU time 1585.19 seconds
Started Mar 24 02:55:42 PM PDT 24
Finished Mar 24 03:22:07 PM PDT 24
Peak memory 289412 kb
Host smart-aa394a34-c03a-4654-be31-09cd95ca0a57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978645604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3978645604
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.195802722
Short name T467
Test name
Test status
Simulation time 872449576 ps
CPU time 51.09 seconds
Started Mar 24 02:55:34 PM PDT 24
Finished Mar 24 02:56:25 PM PDT 24
Peak memory 255816 kb
Host smart-1fcda392-2f69-454e-b4e7-6633ce66d121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
2722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.195802722
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.352182279
Short name T18
Test name
Test status
Simulation time 756070967 ps
CPU time 33.76 seconds
Started Mar 24 02:55:38 PM PDT 24
Finished Mar 24 02:56:12 PM PDT 24
Peak memory 248844 kb
Host smart-2db3dcd9-ef2c-4499-bfe5-4ef2a21bb811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35218
2279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.352182279
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3031481986
Short name T191
Test name
Test status
Simulation time 230165257 ps
CPU time 20.63 seconds
Started Mar 24 02:55:35 PM PDT 24
Finished Mar 24 02:55:56 PM PDT 24
Peak memory 254848 kb
Host smart-8a1056f6-7712-4fa6-b8e1-5267d798cd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30314
81986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3031481986
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3399147055
Short name T567
Test name
Test status
Simulation time 95694052503 ps
CPU time 2502.52 seconds
Started Mar 24 02:55:41 PM PDT 24
Finished Mar 24 03:37:24 PM PDT 24
Peak memory 304336 kb
Host smart-6478977a-b00a-470f-8d1f-b623b3c9e860
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399147055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3399147055
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2193198679
Short name T675
Test name
Test status
Simulation time 37051213086 ps
CPU time 2872.08 seconds
Started Mar 24 02:55:39 PM PDT 24
Finished Mar 24 03:43:32 PM PDT 24
Peak memory 289196 kb
Host smart-3461140d-da8b-44fd-a2f9-19cc5ea5a201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193198679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2193198679
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.922428857
Short name T648
Test name
Test status
Simulation time 32716010482 ps
CPU time 268.87 seconds
Started Mar 24 02:55:40 PM PDT 24
Finished Mar 24 03:00:09 PM PDT 24
Peak memory 257116 kb
Host smart-bc3f53ca-f841-4169-b798-0ec798f6a531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92242
8857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.922428857
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.314366273
Short name T303
Test name
Test status
Simulation time 287195604 ps
CPU time 29.65 seconds
Started Mar 24 02:55:39 PM PDT 24
Finished Mar 24 02:56:08 PM PDT 24
Peak memory 254864 kb
Host smart-18eca82e-a74e-49fb-8d2e-bb2891b82ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
6273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.314366273
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3953427555
Short name T682
Test name
Test status
Simulation time 46761600430 ps
CPU time 1122.46 seconds
Started Mar 24 02:55:45 PM PDT 24
Finished Mar 24 03:14:27 PM PDT 24
Peak memory 272516 kb
Host smart-e4d13161-2aae-4bff-80fc-9185589e7206
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953427555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3953427555
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2321183788
Short name T30
Test name
Test status
Simulation time 23025204806 ps
CPU time 1344.85 seconds
Started Mar 24 02:55:46 PM PDT 24
Finished Mar 24 03:18:11 PM PDT 24
Peak memory 265240 kb
Host smart-576acd2c-4dce-4328-bb89-e6ef1555767d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321183788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2321183788
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2012059576
Short name T317
Test name
Test status
Simulation time 96354515934 ps
CPU time 500.77 seconds
Started Mar 24 02:55:41 PM PDT 24
Finished Mar 24 03:04:02 PM PDT 24
Peak memory 247860 kb
Host smart-a3e5dc1b-b4f1-4ebd-bab8-ba2775d68af3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012059576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2012059576
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.701363297
Short name T50
Test name
Test status
Simulation time 184893743 ps
CPU time 7.83 seconds
Started Mar 24 02:55:40 PM PDT 24
Finished Mar 24 02:55:47 PM PDT 24
Peak memory 248864 kb
Host smart-f47b9a45-a6fe-4182-9d7e-163705b2dc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70136
3297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.701363297
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2469557574
Short name T110
Test name
Test status
Simulation time 2423103069 ps
CPU time 39.79 seconds
Started Mar 24 02:55:40 PM PDT 24
Finished Mar 24 02:56:20 PM PDT 24
Peak memory 248952 kb
Host smart-3e768ccf-734a-4279-8f67-6f9808492242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24695
57574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2469557574
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3827447252
Short name T583
Test name
Test status
Simulation time 849671387 ps
CPU time 31.66 seconds
Started Mar 24 02:55:40 PM PDT 24
Finished Mar 24 02:56:12 PM PDT 24
Peak memory 248856 kb
Host smart-059c619b-63bd-4354-876b-3cdc86dcaeb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38274
47252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3827447252
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3293606987
Short name T243
Test name
Test status
Simulation time 2646425040 ps
CPU time 11.31 seconds
Started Mar 24 02:55:41 PM PDT 24
Finished Mar 24 02:55:52 PM PDT 24
Peak memory 252908 kb
Host smart-1a19ae04-50a4-4841-b01b-e293f84c115c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
06987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3293606987
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2097673517
Short name T665
Test name
Test status
Simulation time 39145825851 ps
CPU time 2272.71 seconds
Started Mar 24 02:55:45 PM PDT 24
Finished Mar 24 03:33:38 PM PDT 24
Peak memory 289788 kb
Host smart-3ffd917e-8018-4aac-8f88-795cb3fb3b7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097673517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2097673517
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3890246776
Short name T598
Test name
Test status
Simulation time 20102155492 ps
CPU time 1025 seconds
Started Mar 24 02:55:44 PM PDT 24
Finished Mar 24 03:12:49 PM PDT 24
Peak memory 281740 kb
Host smart-d03015f8-f306-436c-8a0b-6c7ab3f3f68e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890246776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3890246776
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4266561038
Short name T235
Test name
Test status
Simulation time 33483496 ps
CPU time 3.37 seconds
Started Mar 24 02:53:54 PM PDT 24
Finished Mar 24 02:53:58 PM PDT 24
Peak memory 249072 kb
Host smart-cf4adfd8-73e7-4c05-8a5e-42e1b7f2f0c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4266561038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4266561038
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.4212811140
Short name T51
Test name
Test status
Simulation time 110926699030 ps
CPU time 2760.5 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 03:39:59 PM PDT 24
Peak memory 288620 kb
Host smart-59077e7d-8fcc-43b2-bb97-db73cb1ae948
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212811140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.4212811140
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1537955712
Short name T389
Test name
Test status
Simulation time 461765932 ps
CPU time 20.46 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 02:54:19 PM PDT 24
Peak memory 240644 kb
Host smart-7687de00-848d-4d20-ab3f-4ab65c2d1c12
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1537955712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1537955712
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3486830660
Short name T472
Test name
Test status
Simulation time 3458832212 ps
CPU time 236.37 seconds
Started Mar 24 02:54:01 PM PDT 24
Finished Mar 24 02:57:58 PM PDT 24
Peak memory 256528 kb
Host smart-126a0c5a-7df4-4eb5-a6b0-f872c0a36759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34868
30660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3486830660
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.789862038
Short name T630
Test name
Test status
Simulation time 255073167 ps
CPU time 26.2 seconds
Started Mar 24 02:54:01 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 255752 kb
Host smart-d1195dab-79ba-4317-a04b-cb6cf8f24b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78986
2038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.789862038
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3842378228
Short name T322
Test name
Test status
Simulation time 189083308702 ps
CPU time 3437.33 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 03:51:16 PM PDT 24
Peak memory 285728 kb
Host smart-63071f29-89a7-4209-a34f-4aaeccfb9a77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842378228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3842378228
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.243074876
Short name T396
Test name
Test status
Simulation time 53969175944 ps
CPU time 991.11 seconds
Started Mar 24 02:53:55 PM PDT 24
Finished Mar 24 03:10:27 PM PDT 24
Peak memory 273492 kb
Host smart-7e46416a-5263-4aaa-bdce-f76d2cbd6842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243074876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.243074876
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2097721795
Short name T575
Test name
Test status
Simulation time 1691504554 ps
CPU time 73.86 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 02:55:12 PM PDT 24
Peak memory 248120 kb
Host smart-02d2c3c2-f72b-41ea-9165-ef797529e9bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097721795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2097721795
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1478111967
Short name T383
Test name
Test status
Simulation time 1870228608 ps
CPU time 29.38 seconds
Started Mar 24 02:53:58 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 248856 kb
Host smart-fa2750ed-1004-46a7-b94d-8304f28b1bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
11967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1478111967
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1225459338
Short name T240
Test name
Test status
Simulation time 278677663 ps
CPU time 9.35 seconds
Started Mar 24 02:53:55 PM PDT 24
Finished Mar 24 02:54:05 PM PDT 24
Peak memory 250508 kb
Host smart-eb6b9f4d-94f4-433f-8877-1d7f23285108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12254
59338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1225459338
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1523534631
Short name T513
Test name
Test status
Simulation time 1436804827 ps
CPU time 23.94 seconds
Started Mar 24 02:53:57 PM PDT 24
Finished Mar 24 02:54:22 PM PDT 24
Peak memory 255604 kb
Host smart-964e907f-84ff-4a19-96a2-9860ccd83cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15235
34631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1523534631
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3767403451
Short name T576
Test name
Test status
Simulation time 69244307 ps
CPU time 5.1 seconds
Started Mar 24 02:53:55 PM PDT 24
Finished Mar 24 02:54:01 PM PDT 24
Peak memory 252752 kb
Host smart-55733c62-4a01-4fc9-a13b-6174ce064dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674
03451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3767403451
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.531759919
Short name T514
Test name
Test status
Simulation time 115585265122 ps
CPU time 2019.07 seconds
Started Mar 24 02:53:57 PM PDT 24
Finished Mar 24 03:27:36 PM PDT 24
Peak memory 289820 kb
Host smart-e94a3329-9406-4b60-88cc-a29bbacb9845
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531759919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.531759919
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2533536720
Short name T482
Test name
Test status
Simulation time 129807351101 ps
CPU time 1980.11 seconds
Started Mar 24 02:55:45 PM PDT 24
Finished Mar 24 03:28:45 PM PDT 24
Peak memory 288828 kb
Host smart-f0486854-0514-441a-994b-bc6c60b12891
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533536720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2533536720
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.744873155
Short name T196
Test name
Test status
Simulation time 896140844 ps
CPU time 94.78 seconds
Started Mar 24 02:55:45 PM PDT 24
Finished Mar 24 02:57:20 PM PDT 24
Peak memory 256696 kb
Host smart-518fb54c-4e00-4c99-90b2-42593bd45da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74487
3155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.744873155
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1368662089
Short name T563
Test name
Test status
Simulation time 3387802740 ps
CPU time 57.67 seconds
Started Mar 24 02:55:43 PM PDT 24
Finished Mar 24 02:56:41 PM PDT 24
Peak memory 255392 kb
Host smart-c607da8e-95a5-4bae-9e64-8aa438b3d47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13686
62089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1368662089
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2357885166
Short name T256
Test name
Test status
Simulation time 31733847408 ps
CPU time 972.27 seconds
Started Mar 24 02:55:50 PM PDT 24
Finished Mar 24 03:12:02 PM PDT 24
Peak memory 269412 kb
Host smart-7dbeee70-23c7-4f2e-89cd-a8e2688cf77c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357885166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2357885166
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3171893474
Short name T536
Test name
Test status
Simulation time 51017109361 ps
CPU time 3011.99 seconds
Started Mar 24 02:55:49 PM PDT 24
Finished Mar 24 03:46:01 PM PDT 24
Peak memory 289068 kb
Host smart-d045d43c-c1ec-4383-aa71-71993f04fb32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171893474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3171893474
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.863578933
Short name T323
Test name
Test status
Simulation time 8680105112 ps
CPU time 332.2 seconds
Started Mar 24 02:55:50 PM PDT 24
Finished Mar 24 03:01:22 PM PDT 24
Peak memory 247824 kb
Host smart-407ea534-5071-492d-abce-1816fc4d7ae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863578933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.863578933
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3625895708
Short name T492
Test name
Test status
Simulation time 874879070 ps
CPU time 17.78 seconds
Started Mar 24 02:55:46 PM PDT 24
Finished Mar 24 02:56:03 PM PDT 24
Peak memory 255224 kb
Host smart-2de1f46c-5cca-433a-be14-d8b5b9bcdd39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36258
95708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3625895708
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2582938398
Short name T698
Test name
Test status
Simulation time 65231423 ps
CPU time 3.51 seconds
Started Mar 24 02:55:44 PM PDT 24
Finished Mar 24 02:55:47 PM PDT 24
Peak memory 239036 kb
Host smart-c6554c38-bb4b-4798-997f-64dadde79c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25829
38398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2582938398
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1058323272
Short name T277
Test name
Test status
Simulation time 686348647 ps
CPU time 38.24 seconds
Started Mar 24 02:55:44 PM PDT 24
Finished Mar 24 02:56:23 PM PDT 24
Peak memory 249136 kb
Host smart-ec532590-405b-4f7b-9f0a-0f319323b7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10583
23272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1058323272
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.336168824
Short name T437
Test name
Test status
Simulation time 317104993 ps
CPU time 37.47 seconds
Started Mar 24 02:55:44 PM PDT 24
Finished Mar 24 02:56:22 PM PDT 24
Peak memory 249036 kb
Host smart-c984d5e8-b373-4cdb-9987-3cfa83a68562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33616
8824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.336168824
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2502503209
Short name T399
Test name
Test status
Simulation time 5675951733 ps
CPU time 319.96 seconds
Started Mar 24 02:55:50 PM PDT 24
Finished Mar 24 03:01:10 PM PDT 24
Peak memory 257080 kb
Host smart-5c7e0e46-fb36-49c9-a852-a44c0c523a50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502503209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2502503209
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3575433460
Short name T543
Test name
Test status
Simulation time 138200414321 ps
CPU time 2752.72 seconds
Started Mar 24 02:55:51 PM PDT 24
Finished Mar 24 03:41:44 PM PDT 24
Peak memory 305816 kb
Host smart-1190fbb9-dbc9-4df2-af6d-ada4b83dc771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575433460 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3575433460
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1558048874
Short name T632
Test name
Test status
Simulation time 273098241184 ps
CPU time 1546.75 seconds
Started Mar 24 02:55:51 PM PDT 24
Finished Mar 24 03:21:38 PM PDT 24
Peak memory 272816 kb
Host smart-d88de024-33ea-4628-8c2f-60ecc0762a0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558048874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1558048874
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4122096181
Short name T670
Test name
Test status
Simulation time 5662077649 ps
CPU time 167.55 seconds
Started Mar 24 02:55:50 PM PDT 24
Finished Mar 24 02:58:38 PM PDT 24
Peak memory 249944 kb
Host smart-81fc12c7-dd2b-4db9-8ea2-76b075f1d776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41220
96181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4122096181
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4077058162
Short name T502
Test name
Test status
Simulation time 888405319 ps
CPU time 60.28 seconds
Started Mar 24 02:55:53 PM PDT 24
Finished Mar 24 02:56:53 PM PDT 24
Peak memory 255600 kb
Host smart-bba8bcac-0738-49d4-a96b-e737c5bc07aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
58162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4077058162
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1651974321
Short name T587
Test name
Test status
Simulation time 144460448784 ps
CPU time 1581.23 seconds
Started Mar 24 02:55:55 PM PDT 24
Finished Mar 24 03:22:17 PM PDT 24
Peak memory 288992 kb
Host smart-6b379a74-8a62-463b-a811-75c2999ab960
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651974321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1651974321
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.322023764
Short name T108
Test name
Test status
Simulation time 84510371260 ps
CPU time 2641.81 seconds
Started Mar 24 02:55:56 PM PDT 24
Finished Mar 24 03:39:58 PM PDT 24
Peak memory 285600 kb
Host smart-1e78821a-8837-4651-83fc-25ac303b8c6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322023764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.322023764
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.621013586
Short name T101
Test name
Test status
Simulation time 58417974719 ps
CPU time 575.22 seconds
Started Mar 24 02:55:59 PM PDT 24
Finished Mar 24 03:05:35 PM PDT 24
Peak memory 248072 kb
Host smart-6cfbc342-2015-41b5-b1b1-00d06d881800
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621013586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.621013586
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1153288446
Short name T678
Test name
Test status
Simulation time 1916097904 ps
CPU time 44.82 seconds
Started Mar 24 02:55:50 PM PDT 24
Finished Mar 24 02:56:35 PM PDT 24
Peak memory 256080 kb
Host smart-b324d1d9-3974-46c5-aa98-102bb72e0e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532
88446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1153288446
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.624114789
Short name T252
Test name
Test status
Simulation time 434412637 ps
CPU time 14.6 seconds
Started Mar 24 02:55:49 PM PDT 24
Finished Mar 24 02:56:04 PM PDT 24
Peak memory 254688 kb
Host smart-ddc9bd42-5093-45bf-8234-7cda9b6d35be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62411
4789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.624114789
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.265905545
Short name T282
Test name
Test status
Simulation time 2624619586 ps
CPU time 43.15 seconds
Started Mar 24 02:55:48 PM PDT 24
Finished Mar 24 02:56:31 PM PDT 24
Peak memory 255996 kb
Host smart-87786920-6a98-41fa-9bb3-85d1a22b7fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26590
5545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.265905545
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2139300790
Short name T392
Test name
Test status
Simulation time 363103867 ps
CPU time 42.76 seconds
Started Mar 24 02:55:52 PM PDT 24
Finished Mar 24 02:56:35 PM PDT 24
Peak memory 255928 kb
Host smart-816836a6-e7c1-4c0c-aefe-4064952bca1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393
00790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2139300790
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.108402505
Short name T535
Test name
Test status
Simulation time 37688933735 ps
CPU time 301.27 seconds
Started Mar 24 02:55:53 PM PDT 24
Finished Mar 24 03:00:54 PM PDT 24
Peak memory 257060 kb
Host smart-dbf6a6b5-3976-4fa5-9ec9-cf3f5e69b6b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108402505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.108402505
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1820209489
Short name T530
Test name
Test status
Simulation time 64326337337 ps
CPU time 2333.42 seconds
Started Mar 24 02:55:58 PM PDT 24
Finished Mar 24 03:34:52 PM PDT 24
Peak memory 289388 kb
Host smart-c747c7d5-bda3-4f36-b82e-8e290e714235
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820209489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1820209489
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.137753628
Short name T503
Test name
Test status
Simulation time 4276670143 ps
CPU time 229.82 seconds
Started Mar 24 02:55:55 PM PDT 24
Finished Mar 24 02:59:45 PM PDT 24
Peak memory 249932 kb
Host smart-ba20523f-69ef-4f25-a03d-eeac25323d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13775
3628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.137753628
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2067352695
Short name T691
Test name
Test status
Simulation time 4639627569 ps
CPU time 67.03 seconds
Started Mar 24 02:55:54 PM PDT 24
Finished Mar 24 02:57:01 PM PDT 24
Peak memory 256808 kb
Host smart-8fa91df6-f3e9-4cc9-ae73-e75d62a15a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20673
52695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2067352695
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3279247601
Short name T337
Test name
Test status
Simulation time 104383608336 ps
CPU time 690.24 seconds
Started Mar 24 02:55:58 PM PDT 24
Finished Mar 24 03:07:28 PM PDT 24
Peak memory 266340 kb
Host smart-b0b460fc-2b79-49f1-a3d7-ba007655d94c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279247601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3279247601
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2894848434
Short name T588
Test name
Test status
Simulation time 40964453230 ps
CPU time 2433.91 seconds
Started Mar 24 02:55:58 PM PDT 24
Finished Mar 24 03:36:32 PM PDT 24
Peak memory 273476 kb
Host smart-2eb6c18e-bad1-479b-a3da-a8542b0de392
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894848434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2894848434
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3623405382
Short name T533
Test name
Test status
Simulation time 35879643834 ps
CPU time 436.2 seconds
Started Mar 24 02:55:57 PM PDT 24
Finished Mar 24 03:03:13 PM PDT 24
Peak memory 255992 kb
Host smart-e263ed3d-9046-436b-a498-7fbe4c438740
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623405382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3623405382
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3747596921
Short name T395
Test name
Test status
Simulation time 5177680178 ps
CPU time 36.09 seconds
Started Mar 24 02:55:55 PM PDT 24
Finished Mar 24 02:56:32 PM PDT 24
Peak memory 248960 kb
Host smart-6fa76de0-f9da-4144-8809-769f33ab1c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37475
96921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3747596921
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2891237377
Short name T22
Test name
Test status
Simulation time 10694512457 ps
CPU time 62.43 seconds
Started Mar 24 02:55:52 PM PDT 24
Finished Mar 24 02:56:55 PM PDT 24
Peak memory 247948 kb
Host smart-46d80666-989d-4417-a1f0-a248787090ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28912
37377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2891237377
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1457837738
Short name T534
Test name
Test status
Simulation time 162509537 ps
CPU time 21.27 seconds
Started Mar 24 02:55:52 PM PDT 24
Finished Mar 24 02:56:14 PM PDT 24
Peak memory 247864 kb
Host smart-6fb47d6e-575a-4dc6-bd03-56cdb7f00e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
37738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1457837738
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3984088822
Short name T400
Test name
Test status
Simulation time 240114904 ps
CPU time 16.46 seconds
Started Mar 24 02:55:56 PM PDT 24
Finished Mar 24 02:56:13 PM PDT 24
Peak memory 254148 kb
Host smart-ead400c1-1be0-4ee8-a963-3d013ee2ad67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39840
88822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3984088822
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3172908035
Short name T76
Test name
Test status
Simulation time 99683895781 ps
CPU time 3286.78 seconds
Started Mar 24 02:55:59 PM PDT 24
Finished Mar 24 03:50:47 PM PDT 24
Peak memory 290128 kb
Host smart-4a87aff4-63d3-4693-9696-9ec688340d33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172908035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3172908035
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3518169011
Short name T391
Test name
Test status
Simulation time 64009131971 ps
CPU time 2161.9 seconds
Started Mar 24 02:55:59 PM PDT 24
Finished Mar 24 03:32:01 PM PDT 24
Peak memory 273456 kb
Host smart-ea5603b9-ea18-453f-8fb2-965eba52a50a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518169011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3518169011
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3519932950
Short name T268
Test name
Test status
Simulation time 1679975699 ps
CPU time 163.8 seconds
Started Mar 24 02:56:00 PM PDT 24
Finished Mar 24 02:58:44 PM PDT 24
Peak memory 256388 kb
Host smart-c8f0b5ea-16aa-4e97-a136-ba5a15c2f5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35199
32950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3519932950
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.984110545
Short name T600
Test name
Test status
Simulation time 292535022 ps
CPU time 13.9 seconds
Started Mar 24 02:55:59 PM PDT 24
Finished Mar 24 02:56:13 PM PDT 24
Peak memory 256064 kb
Host smart-658c021c-8bb8-4e42-bd7b-89466c048431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98411
0545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.984110545
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3121345469
Short name T310
Test name
Test status
Simulation time 322106018799 ps
CPU time 1962.32 seconds
Started Mar 24 02:56:04 PM PDT 24
Finished Mar 24 03:28:48 PM PDT 24
Peak memory 272852 kb
Host smart-a308d03a-13d5-4ac1-802d-e05993d75217
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121345469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3121345469
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2939371433
Short name T637
Test name
Test status
Simulation time 36787528480 ps
CPU time 2730.55 seconds
Started Mar 24 02:56:03 PM PDT 24
Finished Mar 24 03:41:34 PM PDT 24
Peak memory 287220 kb
Host smart-24dcacef-25a4-4446-af31-342d39460e75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939371433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2939371433
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2022874317
Short name T537
Test name
Test status
Simulation time 26322163044 ps
CPU time 321.6 seconds
Started Mar 24 02:56:02 PM PDT 24
Finished Mar 24 03:01:24 PM PDT 24
Peak memory 248156 kb
Host smart-f611412c-9a82-4e5b-bd86-85ef3612023a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022874317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2022874317
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.265059100
Short name T17
Test name
Test status
Simulation time 2068503093 ps
CPU time 63.54 seconds
Started Mar 24 02:55:58 PM PDT 24
Finished Mar 24 02:57:01 PM PDT 24
Peak memory 248856 kb
Host smart-13e072ea-b801-4b56-bed5-6d8226f43dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
9100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.265059100
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1819277216
Short name T397
Test name
Test status
Simulation time 7133191215 ps
CPU time 66.09 seconds
Started Mar 24 02:55:58 PM PDT 24
Finished Mar 24 02:57:04 PM PDT 24
Peak memory 248804 kb
Host smart-ed6b7efd-dfa6-4299-b04c-adee99878d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18192
77216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1819277216
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3282029091
Short name T414
Test name
Test status
Simulation time 160879449 ps
CPU time 8.03 seconds
Started Mar 24 02:55:56 PM PDT 24
Finished Mar 24 02:56:05 PM PDT 24
Peak memory 250968 kb
Host smart-10799206-ab4c-4bd7-9ece-f2472cf838e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
29091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3282029091
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.706203217
Short name T629
Test name
Test status
Simulation time 5457373381 ps
CPU time 38.4 seconds
Started Mar 24 02:55:57 PM PDT 24
Finished Mar 24 02:56:36 PM PDT 24
Peak memory 256164 kb
Host smart-36467ac8-3e4f-4b68-880b-4d71cfeccd9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70620
3217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.706203217
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3044947295
Short name T613
Test name
Test status
Simulation time 208049895650 ps
CPU time 2521.03 seconds
Started Mar 24 02:56:06 PM PDT 24
Finished Mar 24 03:38:07 PM PDT 24
Peak memory 288996 kb
Host smart-d9037648-49e8-42e9-bde3-cede8c43aed1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044947295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3044947295
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2939768925
Short name T92
Test name
Test status
Simulation time 39321787898 ps
CPU time 2703.72 seconds
Started Mar 24 02:56:02 PM PDT 24
Finished Mar 24 03:41:06 PM PDT 24
Peak memory 289912 kb
Host smart-5ef8ffd2-751a-460d-87b1-8bf05121a4cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939768925 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2939768925
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.665873664
Short name T119
Test name
Test status
Simulation time 19544169098 ps
CPU time 1295.41 seconds
Started Mar 24 02:56:08 PM PDT 24
Finished Mar 24 03:17:43 PM PDT 24
Peak memory 267316 kb
Host smart-cb58f3c6-9e16-4596-b44d-076d0584cb70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665873664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.665873664
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3100961019
Short name T125
Test name
Test status
Simulation time 13160009773 ps
CPU time 179.34 seconds
Started Mar 24 02:56:03 PM PDT 24
Finished Mar 24 02:59:03 PM PDT 24
Peak memory 257012 kb
Host smart-fa7eab76-d23c-42e4-8714-352d3c10a017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31009
61019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3100961019
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2865268994
Short name T561
Test name
Test status
Simulation time 164373433 ps
CPU time 5.61 seconds
Started Mar 24 02:56:04 PM PDT 24
Finished Mar 24 02:56:10 PM PDT 24
Peak memory 253368 kb
Host smart-39141364-5cf0-4afa-9553-76abda8e4898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28652
68994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2865268994
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3158020972
Short name T696
Test name
Test status
Simulation time 178044918931 ps
CPU time 2736.81 seconds
Started Mar 24 02:56:08 PM PDT 24
Finished Mar 24 03:41:45 PM PDT 24
Peak memory 289432 kb
Host smart-251754f3-15e9-4637-8910-da75a46d2e8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158020972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3158020972
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1609242014
Short name T298
Test name
Test status
Simulation time 63488993953 ps
CPU time 1665.13 seconds
Started Mar 24 02:56:09 PM PDT 24
Finished Mar 24 03:23:56 PM PDT 24
Peak memory 288336 kb
Host smart-3c41c8c0-2ec1-48c6-961b-8b0cb8cfc100
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609242014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1609242014
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1066490771
Short name T89
Test name
Test status
Simulation time 862558476 ps
CPU time 52.34 seconds
Started Mar 24 02:56:03 PM PDT 24
Finished Mar 24 02:56:55 PM PDT 24
Peak memory 249012 kb
Host smart-14746342-2552-4b92-b3e5-12e566ee7ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10664
90771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1066490771
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1852053882
Short name T422
Test name
Test status
Simulation time 899500911 ps
CPU time 14.67 seconds
Started Mar 24 02:56:02 PM PDT 24
Finished Mar 24 02:56:17 PM PDT 24
Peak memory 248744 kb
Host smart-c577d766-3680-43a9-bb44-5c87c823265f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18520
53882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1852053882
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3609609562
Short name T456
Test name
Test status
Simulation time 220911891 ps
CPU time 13.15 seconds
Started Mar 24 02:56:03 PM PDT 24
Finished Mar 24 02:56:16 PM PDT 24
Peak memory 255544 kb
Host smart-a870f19c-3aa9-4baf-907f-66c1bed9765e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
09562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3609609562
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4267246117
Short name T257
Test name
Test status
Simulation time 514817506 ps
CPU time 32.09 seconds
Started Mar 24 02:56:02 PM PDT 24
Finished Mar 24 02:56:34 PM PDT 24
Peak memory 248868 kb
Host smart-fe90de23-4c7c-44fb-a6d2-ed422072b715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
46117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4267246117
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1501310347
Short name T267
Test name
Test status
Simulation time 16936165731 ps
CPU time 164.42 seconds
Started Mar 24 02:56:07 PM PDT 24
Finished Mar 24 02:58:52 PM PDT 24
Peak memory 257084 kb
Host smart-39d07093-5f03-489a-9878-51fd63e8377a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501310347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1501310347
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.533809768
Short name T264
Test name
Test status
Simulation time 20739771709 ps
CPU time 1465.99 seconds
Started Mar 24 02:56:08 PM PDT 24
Finished Mar 24 03:20:34 PM PDT 24
Peak memory 282292 kb
Host smart-756bb274-ae2b-454b-83cb-2cffd238830c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533809768 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.533809768
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.375672262
Short name T2
Test name
Test status
Simulation time 42677043799 ps
CPU time 2631.1 seconds
Started Mar 24 02:56:16 PM PDT 24
Finished Mar 24 03:40:07 PM PDT 24
Peak memory 285064 kb
Host smart-f784b62c-8fe2-496c-ba23-1a849bda865c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375672262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.375672262
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2736610706
Short name T681
Test name
Test status
Simulation time 2600146798 ps
CPU time 144.62 seconds
Started Mar 24 02:56:13 PM PDT 24
Finished Mar 24 02:58:38 PM PDT 24
Peak memory 248572 kb
Host smart-df9f5c3f-9917-499a-b70a-fde6916e1098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
10706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2736610706
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.395828969
Short name T37
Test name
Test status
Simulation time 571239328 ps
CPU time 37.51 seconds
Started Mar 24 02:56:14 PM PDT 24
Finished Mar 24 02:56:51 PM PDT 24
Peak memory 254824 kb
Host smart-32269c85-c206-4590-80f5-865e2467e9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
8969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.395828969
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4265990576
Short name T690
Test name
Test status
Simulation time 109581769278 ps
CPU time 1665.26 seconds
Started Mar 24 02:56:18 PM PDT 24
Finished Mar 24 03:24:04 PM PDT 24
Peak memory 271588 kb
Host smart-a5aff1a8-1153-4a8f-9a13-4f46a9017791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265990576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4265990576
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1923442096
Short name T528
Test name
Test status
Simulation time 55587474747 ps
CPU time 709.16 seconds
Started Mar 24 02:56:20 PM PDT 24
Finished Mar 24 03:08:10 PM PDT 24
Peak memory 272236 kb
Host smart-f3fdbccd-74d3-4e6f-95ab-d82d74818150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923442096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1923442096
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3759159441
Short name T585
Test name
Test status
Simulation time 8185200900 ps
CPU time 272.98 seconds
Started Mar 24 02:56:17 PM PDT 24
Finished Mar 24 03:00:51 PM PDT 24
Peak memory 252976 kb
Host smart-cf86bae9-6e8e-4b94-adbb-18e8eacb2d1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759159441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3759159441
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3330793132
Short name T378
Test name
Test status
Simulation time 2157892907 ps
CPU time 25.02 seconds
Started Mar 24 02:56:11 PM PDT 24
Finished Mar 24 02:56:37 PM PDT 24
Peak memory 255672 kb
Host smart-e5b1bb30-baf9-4dfa-9ad8-6b302c3b800b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
93132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3330793132
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.673192647
Short name T499
Test name
Test status
Simulation time 737624503 ps
CPU time 15.98 seconds
Started Mar 24 02:56:10 PM PDT 24
Finished Mar 24 02:56:27 PM PDT 24
Peak memory 251952 kb
Host smart-2e524c9e-e425-4ea2-885b-df3e3a8b7c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67319
2647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.673192647
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1891754693
Short name T85
Test name
Test status
Simulation time 910859993 ps
CPU time 32.87 seconds
Started Mar 24 02:56:18 PM PDT 24
Finished Mar 24 02:56:51 PM PDT 24
Peak memory 248820 kb
Host smart-0790d243-f837-414d-bf94-b0872cd7d6c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
54693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1891754693
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.777427776
Short name T569
Test name
Test status
Simulation time 71516664 ps
CPU time 6.43 seconds
Started Mar 24 02:56:10 PM PDT 24
Finished Mar 24 02:56:17 PM PDT 24
Peak memory 248860 kb
Host smart-4c5cdbb4-f3f5-436a-b65f-445bf3c1ddd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77742
7776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.777427776
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2913630656
Short name T275
Test name
Test status
Simulation time 97934920771 ps
CPU time 2568.54 seconds
Started Mar 24 02:56:23 PM PDT 24
Finished Mar 24 03:39:12 PM PDT 24
Peak memory 289924 kb
Host smart-a809dbb6-00a9-44fd-9a76-6b17056f9d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913630656 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2913630656
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.834233910
Short name T655
Test name
Test status
Simulation time 12947481219 ps
CPU time 585.23 seconds
Started Mar 24 02:56:27 PM PDT 24
Finished Mar 24 03:06:13 PM PDT 24
Peak memory 273488 kb
Host smart-7cd79865-6045-4fc4-bddd-d5aa5229921c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834233910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.834233910
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2228170498
Short name T699
Test name
Test status
Simulation time 22359129008 ps
CPU time 124.55 seconds
Started Mar 24 02:56:27 PM PDT 24
Finished Mar 24 02:58:32 PM PDT 24
Peak memory 256700 kb
Host smart-6a8d1e3b-b32c-4f9b-945b-312214d64891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22281
70498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2228170498
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3962714041
Short name T480
Test name
Test status
Simulation time 234732342 ps
CPU time 5.28 seconds
Started Mar 24 02:56:21 PM PDT 24
Finished Mar 24 02:56:26 PM PDT 24
Peak memory 240728 kb
Host smart-4145bafe-8181-46f5-95d6-ee9355859e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
14041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3962714041
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1013008279
Short name T446
Test name
Test status
Simulation time 53418102915 ps
CPU time 1687.99 seconds
Started Mar 24 02:56:26 PM PDT 24
Finished Mar 24 03:24:34 PM PDT 24
Peak memory 284328 kb
Host smart-0f3b4b7f-28c7-430a-8421-b981d3c763bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013008279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1013008279
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2850321914
Short name T489
Test name
Test status
Simulation time 1130017806 ps
CPU time 20.45 seconds
Started Mar 24 02:56:23 PM PDT 24
Finished Mar 24 02:56:44 PM PDT 24
Peak memory 248856 kb
Host smart-2e461d2d-3870-4bd4-a77d-13aebd9d0ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
21914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2850321914
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1818230616
Short name T481
Test name
Test status
Simulation time 688790910 ps
CPU time 23.27 seconds
Started Mar 24 02:56:21 PM PDT 24
Finished Mar 24 02:56:44 PM PDT 24
Peak memory 248612 kb
Host smart-92096c32-4150-48cd-9def-4fac788002b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18182
30616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1818230616
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2929693228
Short name T465
Test name
Test status
Simulation time 752476602 ps
CPU time 11.8 seconds
Started Mar 24 02:56:24 PM PDT 24
Finished Mar 24 02:56:36 PM PDT 24
Peak memory 254012 kb
Host smart-731ec83a-7896-42bd-8aae-c81ca0bc8518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29296
93228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2929693228
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2602572085
Short name T419
Test name
Test status
Simulation time 105239639 ps
CPU time 3.19 seconds
Started Mar 24 02:56:22 PM PDT 24
Finished Mar 24 02:56:25 PM PDT 24
Peak memory 240660 kb
Host smart-8837af17-2f14-4003-b21c-9cc23f7e7ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26025
72085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2602572085
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3949542056
Short name T645
Test name
Test status
Simulation time 39179758498 ps
CPU time 1039.64 seconds
Started Mar 24 02:56:27 PM PDT 24
Finished Mar 24 03:13:47 PM PDT 24
Peak memory 283748 kb
Host smart-b56fccca-74a6-4420-8666-da4cc8626929
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949542056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3949542056
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3703203019
Short name T255
Test name
Test status
Simulation time 8153091627 ps
CPU time 44.51 seconds
Started Mar 24 02:56:31 PM PDT 24
Finished Mar 24 02:57:16 PM PDT 24
Peak memory 257032 kb
Host smart-26d424ac-0d05-48bd-a28b-93e386429175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
03019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3703203019
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2254445813
Short name T63
Test name
Test status
Simulation time 255651951 ps
CPU time 13.07 seconds
Started Mar 24 02:56:32 PM PDT 24
Finished Mar 24 02:56:46 PM PDT 24
Peak memory 254620 kb
Host smart-280c48a9-b00f-4e17-96de-e35b86800410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22544
45813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2254445813
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2732746835
Short name T349
Test name
Test status
Simulation time 175865540531 ps
CPU time 2837.62 seconds
Started Mar 24 02:56:30 PM PDT 24
Finished Mar 24 03:43:48 PM PDT 24
Peak memory 285340 kb
Host smart-d9b3751a-079b-4f52-bcab-337e34e3f409
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732746835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2732746835
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.491314022
Short name T516
Test name
Test status
Simulation time 28314337786 ps
CPU time 311.34 seconds
Started Mar 24 02:56:36 PM PDT 24
Finished Mar 24 03:01:47 PM PDT 24
Peak memory 247916 kb
Host smart-6836cbd5-813f-4614-a6ab-5787481a3d72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491314022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.491314022
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2625587139
Short name T572
Test name
Test status
Simulation time 309989208 ps
CPU time 19.2 seconds
Started Mar 24 02:56:26 PM PDT 24
Finished Mar 24 02:56:46 PM PDT 24
Peak memory 248888 kb
Host smart-ba0eaefc-325e-439e-93d6-1653f4e73f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
87139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2625587139
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.844490336
Short name T96
Test name
Test status
Simulation time 4869355349 ps
CPU time 53.23 seconds
Started Mar 24 02:56:32 PM PDT 24
Finished Mar 24 02:57:26 PM PDT 24
Peak memory 255524 kb
Host smart-15c2690c-54f6-4143-ac06-1ba89f3aecd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84449
0336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.844490336
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1192742329
Short name T418
Test name
Test status
Simulation time 40508243 ps
CPU time 5.04 seconds
Started Mar 24 02:56:35 PM PDT 24
Finished Mar 24 02:56:41 PM PDT 24
Peak memory 239072 kb
Host smart-1bc4a5b4-82e5-4cea-80b1-a0746cf7508d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11927
42329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1192742329
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2196807621
Short name T594
Test name
Test status
Simulation time 71152076 ps
CPU time 5.64 seconds
Started Mar 24 02:56:27 PM PDT 24
Finished Mar 24 02:56:33 PM PDT 24
Peak memory 240692 kb
Host smart-e7aeb55c-bd59-4ed2-9a52-fb52ff49246b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21968
07621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2196807621
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3050570905
Short name T55
Test name
Test status
Simulation time 60495024887 ps
CPU time 1409.7 seconds
Started Mar 24 02:56:41 PM PDT 24
Finished Mar 24 03:20:11 PM PDT 24
Peak memory 289392 kb
Host smart-227529c4-666b-4d15-86c0-a4a79e7913fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050570905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3050570905
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.491916658
Short name T189
Test name
Test status
Simulation time 68510094472 ps
CPU time 2037.25 seconds
Started Mar 24 02:56:35 PM PDT 24
Finished Mar 24 03:30:33 PM PDT 24
Peak memory 305780 kb
Host smart-615cd624-497b-4a27-b179-72a29c39aa8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491916658 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.491916658
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3865920318
Short name T247
Test name
Test status
Simulation time 132519536765 ps
CPU time 2344.21 seconds
Started Mar 24 02:56:38 PM PDT 24
Finished Mar 24 03:35:43 PM PDT 24
Peak memory 289168 kb
Host smart-d8e90d66-a7cc-414e-8d40-cd88a036febe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865920318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3865920318
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3874951255
Short name T500
Test name
Test status
Simulation time 11809995360 ps
CPU time 159.69 seconds
Started Mar 24 02:56:35 PM PDT 24
Finished Mar 24 02:59:14 PM PDT 24
Peak memory 249952 kb
Host smart-9e4c361f-f3ff-4891-996a-6af15af2a6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
51255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3874951255
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3333593099
Short name T593
Test name
Test status
Simulation time 12082410740 ps
CPU time 38.14 seconds
Started Mar 24 02:56:39 PM PDT 24
Finished Mar 24 02:57:18 PM PDT 24
Peak memory 249304 kb
Host smart-8d67e4be-7df2-4231-805a-c7c22895307d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33335
93099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3333593099
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3549365677
Short name T346
Test name
Test status
Simulation time 25022600412 ps
CPU time 1507.45 seconds
Started Mar 24 02:56:39 PM PDT 24
Finished Mar 24 03:21:46 PM PDT 24
Peak memory 270404 kb
Host smart-c80c4087-5e7c-4d0e-a8e9-d2aaebdf59d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549365677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3549365677
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2269846755
Short name T124
Test name
Test status
Simulation time 140017104784 ps
CPU time 2286.54 seconds
Started Mar 24 02:56:40 PM PDT 24
Finished Mar 24 03:34:47 PM PDT 24
Peak memory 273500 kb
Host smart-a3e06f59-e416-47d6-a9cb-6a41acdbc5c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269846755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2269846755
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2101070072
Short name T612
Test name
Test status
Simulation time 5183303721 ps
CPU time 223.12 seconds
Started Mar 24 02:56:40 PM PDT 24
Finished Mar 24 03:00:23 PM PDT 24
Peak memory 247056 kb
Host smart-b42e30a1-8cef-4d3b-91d2-0e092d3066b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101070072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2101070072
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1979892978
Short name T522
Test name
Test status
Simulation time 184526582 ps
CPU time 14.52 seconds
Started Mar 24 02:56:38 PM PDT 24
Finished Mar 24 02:56:53 PM PDT 24
Peak memory 248888 kb
Host smart-81f127b7-5e0e-4c8a-8f3b-cf4d1b410161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19798
92978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1979892978
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.153226962
Short name T614
Test name
Test status
Simulation time 3540302723 ps
CPU time 61.77 seconds
Started Mar 24 02:56:38 PM PDT 24
Finished Mar 24 02:57:40 PM PDT 24
Peak memory 255424 kb
Host smart-d074de3e-1213-4cb8-91a7-09dbcf3b505f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322
6962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.153226962
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1225565553
Short name T410
Test name
Test status
Simulation time 372950552 ps
CPU time 31.48 seconds
Started Mar 24 02:56:34 PM PDT 24
Finished Mar 24 02:57:06 PM PDT 24
Peak memory 256488 kb
Host smart-e0ef3dc4-107a-4be1-8ec0-780a236cc365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12255
65553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1225565553
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2676833234
Short name T578
Test name
Test status
Simulation time 364253664 ps
CPU time 35.5 seconds
Started Mar 24 02:56:39 PM PDT 24
Finished Mar 24 02:57:14 PM PDT 24
Peak memory 249232 kb
Host smart-2a49ca47-d7b2-48a8-a5d0-3c54cbb492b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26768
33234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2676833234
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4240028742
Short name T299
Test name
Test status
Simulation time 61017330979 ps
CPU time 3975.16 seconds
Started Mar 24 02:56:39 PM PDT 24
Finished Mar 24 04:02:55 PM PDT 24
Peak memory 289644 kb
Host smart-f1dad189-ba56-4720-a507-2a9eec306390
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240028742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4240028742
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.573765327
Short name T471
Test name
Test status
Simulation time 15871642101 ps
CPU time 897.79 seconds
Started Mar 24 02:56:48 PM PDT 24
Finished Mar 24 03:11:46 PM PDT 24
Peak memory 273504 kb
Host smart-445d7d60-54bb-4a87-93eb-5d0f03317e6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573765327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.573765327
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.30574437
Short name T250
Test name
Test status
Simulation time 2569131689 ps
CPU time 155.02 seconds
Started Mar 24 02:56:47 PM PDT 24
Finished Mar 24 02:59:22 PM PDT 24
Peak memory 250976 kb
Host smart-dea8b33d-8183-4ffb-8998-f044f554a08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574
437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.30574437
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3400078558
Short name T90
Test name
Test status
Simulation time 3465331362 ps
CPU time 60.66 seconds
Started Mar 24 02:56:42 PM PDT 24
Finished Mar 24 02:57:43 PM PDT 24
Peak memory 255988 kb
Host smart-6afaf1f2-1816-42ce-b502-79107fa42270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34000
78558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3400078558
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2398096532
Short name T484
Test name
Test status
Simulation time 17114676405 ps
CPU time 885.48 seconds
Started Mar 24 02:56:48 PM PDT 24
Finished Mar 24 03:11:34 PM PDT 24
Peak memory 269444 kb
Host smart-6440182e-3677-45b7-99f4-a6b7cd32243b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398096532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2398096532
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2549504863
Short name T374
Test name
Test status
Simulation time 330602198050 ps
CPU time 2005.33 seconds
Started Mar 24 02:56:48 PM PDT 24
Finished Mar 24 03:30:14 PM PDT 24
Peak memory 273524 kb
Host smart-ea5eee89-b04f-4f1f-9e0d-32e37d90f933
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549504863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2549504863
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1926058641
Short name T319
Test name
Test status
Simulation time 9723874423 ps
CPU time 419.42 seconds
Started Mar 24 02:56:49 PM PDT 24
Finished Mar 24 03:03:49 PM PDT 24
Peak memory 248088 kb
Host smart-8ade4139-6c8c-4e85-8169-ad435a744e31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926058641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1926058641
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2608443079
Short name T370
Test name
Test status
Simulation time 924968285 ps
CPU time 26.02 seconds
Started Mar 24 02:56:48 PM PDT 24
Finished Mar 24 02:57:14 PM PDT 24
Peak memory 257060 kb
Host smart-60ff9bb3-5465-4778-8aee-f2110d794bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
43079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2608443079
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2822323694
Short name T601
Test name
Test status
Simulation time 185658169 ps
CPU time 3.99 seconds
Started Mar 24 02:56:43 PM PDT 24
Finished Mar 24 02:56:47 PM PDT 24
Peak memory 239184 kb
Host smart-09d8eae7-5bfb-4595-9347-2af15f05bf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
23694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2822323694
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1893973646
Short name T271
Test name
Test status
Simulation time 2172302796 ps
CPU time 47.4 seconds
Started Mar 24 02:56:48 PM PDT 24
Finished Mar 24 02:57:36 PM PDT 24
Peak memory 248920 kb
Host smart-7662540a-11cb-4f9e-a4b3-200172698967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
73646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1893973646
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2412916075
Short name T473
Test name
Test status
Simulation time 116642206 ps
CPU time 12.61 seconds
Started Mar 24 02:56:46 PM PDT 24
Finished Mar 24 02:56:59 PM PDT 24
Peak memory 249184 kb
Host smart-6ac53b76-dcc5-4ef0-bdb9-bb4e3718f3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
16075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2412916075
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.748306993
Short name T192
Test name
Test status
Simulation time 14355802 ps
CPU time 2.47 seconds
Started Mar 24 02:54:01 PM PDT 24
Finished Mar 24 02:54:04 PM PDT 24
Peak memory 249040 kb
Host smart-8abfd192-e808-472f-b143-833c7a3e2804
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=748306993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.748306993
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1239084124
Short name T104
Test name
Test status
Simulation time 41915943977 ps
CPU time 851.74 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 03:08:12 PM PDT 24
Peak memory 267356 kb
Host smart-dab9bdbf-fc69-4a96-9e60-c8cf83a7ab16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239084124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1239084124
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.409913238
Short name T505
Test name
Test status
Simulation time 2936084238 ps
CPU time 29.93 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 02:54:30 PM PDT 24
Peak memory 240720 kb
Host smart-e9093aee-2529-47b3-a18f-59ce775dc2ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=409913238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.409913238
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3029063126
Short name T242
Test name
Test status
Simulation time 383507606 ps
CPU time 37.32 seconds
Started Mar 24 02:53:59 PM PDT 24
Finished Mar 24 02:54:36 PM PDT 24
Peak memory 255976 kb
Host smart-84cf597e-59ab-4b80-a403-92204a196038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
63126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3029063126
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2606829327
Short name T381
Test name
Test status
Simulation time 597950266 ps
CPU time 28.57 seconds
Started Mar 24 02:53:59 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 249192 kb
Host smart-b3b9b77d-399e-472e-be4d-409c3036c174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
29327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2606829327
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.976381614
Short name T308
Test name
Test status
Simulation time 21591434558 ps
CPU time 1582.54 seconds
Started Mar 24 02:53:59 PM PDT 24
Finished Mar 24 03:20:22 PM PDT 24
Peak memory 267300 kb
Host smart-7e049197-c9d2-4e5b-b973-4ed7dcbb18c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976381614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.976381614
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1711148995
Short name T415
Test name
Test status
Simulation time 25499516697 ps
CPU time 882.8 seconds
Started Mar 24 02:54:01 PM PDT 24
Finished Mar 24 03:08:44 PM PDT 24
Peak memory 268392 kb
Host smart-91aba3f9-ad7e-4684-9e1e-e5489f6f4a13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711148995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1711148995
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2130908307
Short name T320
Test name
Test status
Simulation time 9681861933 ps
CPU time 347.82 seconds
Started Mar 24 02:53:55 PM PDT 24
Finished Mar 24 02:59:43 PM PDT 24
Peak memory 248008 kb
Host smart-7b1f1920-ecd8-4b86-9d0e-8107dd2d934c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130908307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2130908307
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1823855349
Short name T518
Test name
Test status
Simulation time 134749666 ps
CPU time 17.86 seconds
Started Mar 24 02:54:01 PM PDT 24
Finished Mar 24 02:54:20 PM PDT 24
Peak memory 249072 kb
Host smart-1fd03804-df07-4de4-9c2d-ef7709c29961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18238
55349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1823855349
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2653023340
Short name T604
Test name
Test status
Simulation time 116293127 ps
CPU time 10.52 seconds
Started Mar 24 02:53:57 PM PDT 24
Finished Mar 24 02:54:08 PM PDT 24
Peak memory 248876 kb
Host smart-815b5e91-a813-4b67-b242-efeadd9bfece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
23340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2653023340
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3186942675
Short name T10
Test name
Test status
Simulation time 498565951 ps
CPU time 24.41 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 02:54:24 PM PDT 24
Peak memory 273348 kb
Host smart-db48330e-bda5-4344-8993-4f65db128860
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3186942675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3186942675
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2057278254
Short name T287
Test name
Test status
Simulation time 276958943 ps
CPU time 21.25 seconds
Started Mar 24 02:53:56 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 255096 kb
Host smart-ceb21c73-d5a3-4c9a-92d3-4d31fb497228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20572
78254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2057278254
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.417482123
Short name T426
Test name
Test status
Simulation time 51619796 ps
CPU time 7.25 seconds
Started Mar 24 02:53:56 PM PDT 24
Finished Mar 24 02:54:03 PM PDT 24
Peak memory 248832 kb
Host smart-af1bd0f3-6720-4690-b0b1-035456df5274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
2123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.417482123
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1062408365
Short name T113
Test name
Test status
Simulation time 4424594979 ps
CPU time 82.05 seconds
Started Mar 24 02:54:04 PM PDT 24
Finished Mar 24 02:55:26 PM PDT 24
Peak memory 257332 kb
Host smart-98d3c6d0-516c-4575-b9f2-2ef19e207edd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062408365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1062408365
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1397704151
Short name T441
Test name
Test status
Simulation time 38755124367 ps
CPU time 1051.24 seconds
Started Mar 24 02:56:53 PM PDT 24
Finished Mar 24 03:14:25 PM PDT 24
Peak memory 271764 kb
Host smart-e2c1847c-c82f-441f-baff-4391fd15e27a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397704151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1397704151
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3204756587
Short name T666
Test name
Test status
Simulation time 2152249144 ps
CPU time 146.96 seconds
Started Mar 24 02:56:52 PM PDT 24
Finished Mar 24 02:59:19 PM PDT 24
Peak memory 250988 kb
Host smart-a412947d-e8a0-4663-9466-49c72d2d1e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
56587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3204756587
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2407166982
Short name T603
Test name
Test status
Simulation time 1101132163 ps
CPU time 18.1 seconds
Started Mar 24 02:56:52 PM PDT 24
Finished Mar 24 02:57:10 PM PDT 24
Peak memory 255468 kb
Host smart-9d1d89d1-e384-4491-bd6d-9de3660133b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
66982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2407166982
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2761791577
Short name T197
Test name
Test status
Simulation time 73255187550 ps
CPU time 1010.14 seconds
Started Mar 24 02:56:54 PM PDT 24
Finished Mar 24 03:13:45 PM PDT 24
Peak memory 272532 kb
Host smart-23e7210b-d159-4793-84f6-a1e841c249b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761791577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2761791577
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2526119158
Short name T431
Test name
Test status
Simulation time 13335575748 ps
CPU time 679.53 seconds
Started Mar 24 02:56:51 PM PDT 24
Finished Mar 24 03:08:11 PM PDT 24
Peak memory 265316 kb
Host smart-6d520bd8-b541-4985-95a0-b3b7cfdb9f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526119158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2526119158
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2221344852
Short name T466
Test name
Test status
Simulation time 4685098013 ps
CPU time 95.32 seconds
Started Mar 24 02:56:54 PM PDT 24
Finished Mar 24 02:58:29 PM PDT 24
Peak memory 248228 kb
Host smart-492c59be-7197-4386-b1bf-f66982d1c310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221344852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2221344852
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.51465202
Short name T577
Test name
Test status
Simulation time 4173489576 ps
CPU time 49.46 seconds
Started Mar 24 02:56:50 PM PDT 24
Finished Mar 24 02:57:40 PM PDT 24
Peak memory 256336 kb
Host smart-0face912-b48e-4522-8299-90342f19563a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51465
202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.51465202
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4237760439
Short name T547
Test name
Test status
Simulation time 797659606 ps
CPU time 48.23 seconds
Started Mar 24 02:56:54 PM PDT 24
Finished Mar 24 02:57:42 PM PDT 24
Peak memory 256016 kb
Host smart-fe6cba2b-ac44-446c-b418-f27a34855206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377
60439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4237760439
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3458237615
Short name T289
Test name
Test status
Simulation time 495733654 ps
CPU time 13.04 seconds
Started Mar 24 02:56:52 PM PDT 24
Finished Mar 24 02:57:06 PM PDT 24
Peak memory 248864 kb
Host smart-fd04b455-62ba-4880-b5f2-d912953bb976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
37615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3458237615
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1895795496
Short name T409
Test name
Test status
Simulation time 426650662 ps
CPU time 7.59 seconds
Started Mar 24 02:56:50 PM PDT 24
Finished Mar 24 02:56:58 PM PDT 24
Peak memory 250864 kb
Host smart-2e66544a-230f-48c8-a20c-30cf92cee52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18957
95496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1895795496
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2979673967
Short name T620
Test name
Test status
Simulation time 361225276432 ps
CPU time 8233.61 seconds
Started Mar 24 02:56:56 PM PDT 24
Finished Mar 24 05:14:11 PM PDT 24
Peak memory 371664 kb
Host smart-9722d48c-55ef-46dc-ae7e-bf7efa8673d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979673967 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2979673967
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3818229701
Short name T692
Test name
Test status
Simulation time 1093201047 ps
CPU time 25 seconds
Started Mar 24 02:56:57 PM PDT 24
Finished Mar 24 02:57:22 PM PDT 24
Peak memory 255944 kb
Host smart-eb705813-31ad-4572-b258-5299cb2661a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
29701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3818229701
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3930890501
Short name T701
Test name
Test status
Simulation time 330297892 ps
CPU time 27.58 seconds
Started Mar 24 02:56:58 PM PDT 24
Finished Mar 24 02:57:26 PM PDT 24
Peak memory 255632 kb
Host smart-56abee01-1b46-42cd-85bc-4e4ae74d7a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39308
90501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3930890501
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1047086410
Short name T340
Test name
Test status
Simulation time 124154243959 ps
CPU time 1366.65 seconds
Started Mar 24 02:57:02 PM PDT 24
Finished Mar 24 03:19:49 PM PDT 24
Peak memory 266300 kb
Host smart-f26df7f0-6a00-462b-94c0-672a043c5370
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047086410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1047086410
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1125350323
Short name T14
Test name
Test status
Simulation time 32831349114 ps
CPU time 2466.94 seconds
Started Mar 24 02:57:03 PM PDT 24
Finished Mar 24 03:38:11 PM PDT 24
Peak memory 281636 kb
Host smart-41edfd53-2ddb-41e9-be78-3361298407c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125350323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1125350323
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.270583382
Short name T521
Test name
Test status
Simulation time 22168431683 ps
CPU time 256.88 seconds
Started Mar 24 02:57:02 PM PDT 24
Finished Mar 24 03:01:19 PM PDT 24
Peak memory 248028 kb
Host smart-70876db6-f04d-4ac0-a78c-15966f4dc7d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270583382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.270583382
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1514914250
Short name T450
Test name
Test status
Simulation time 1423216632 ps
CPU time 25.05 seconds
Started Mar 24 02:56:57 PM PDT 24
Finished Mar 24 02:57:22 PM PDT 24
Peak memory 248856 kb
Host smart-fce04ae5-bfe0-4592-ba4d-71ea9f88a046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15149
14250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1514914250
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3526486035
Short name T488
Test name
Test status
Simulation time 338412897 ps
CPU time 35.21 seconds
Started Mar 24 02:56:57 PM PDT 24
Finished Mar 24 02:57:33 PM PDT 24
Peak memory 248428 kb
Host smart-606797d6-7f7d-48d6-b828-ad00e2d37fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35264
86035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3526486035
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.561970745
Short name T685
Test name
Test status
Simulation time 821307618 ps
CPU time 14.28 seconds
Started Mar 24 02:56:58 PM PDT 24
Finished Mar 24 02:57:13 PM PDT 24
Peak memory 255516 kb
Host smart-1575a076-ef6f-41fe-8d31-d06ffb4a5e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56197
0745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.561970745
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.431371658
Short name T406
Test name
Test status
Simulation time 47818567 ps
CPU time 4.14 seconds
Started Mar 24 02:56:55 PM PDT 24
Finished Mar 24 02:57:00 PM PDT 24
Peak memory 248892 kb
Host smart-cb6f35af-7b68-47a5-b3b8-cd4acba0a468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43137
1658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.431371658
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3141309856
Short name T511
Test name
Test status
Simulation time 12915259505 ps
CPU time 60.2 seconds
Started Mar 24 02:57:01 PM PDT 24
Finished Mar 24 02:58:01 PM PDT 24
Peak memory 257140 kb
Host smart-1881ca62-0304-462f-a493-196d8751ca8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141309856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3141309856
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3304110238
Short name T263
Test name
Test status
Simulation time 76177523380 ps
CPU time 2762.85 seconds
Started Mar 24 02:57:03 PM PDT 24
Finished Mar 24 03:43:06 PM PDT 24
Peak memory 289940 kb
Host smart-14edd42e-61f0-4ebb-9e8e-9fd9ee7d1957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304110238 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3304110238
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1422936764
Short name T302
Test name
Test status
Simulation time 69925947939 ps
CPU time 1181.95 seconds
Started Mar 24 02:57:07 PM PDT 24
Finished Mar 24 03:16:49 PM PDT 24
Peak memory 265568 kb
Host smart-a919c5a8-3139-4d2d-bfad-ce0dfa3ae873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422936764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1422936764
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4108177010
Short name T295
Test name
Test status
Simulation time 9286271192 ps
CPU time 129 seconds
Started Mar 24 02:57:06 PM PDT 24
Finished Mar 24 02:59:15 PM PDT 24
Peak memory 257060 kb
Host smart-c33f5eb2-843b-42c7-868d-d720e67dbe49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41081
77010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4108177010
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1995285820
Short name T447
Test name
Test status
Simulation time 326301747 ps
CPU time 7.1 seconds
Started Mar 24 02:57:08 PM PDT 24
Finished Mar 24 02:57:16 PM PDT 24
Peak memory 240528 kb
Host smart-7f69c1cf-8402-400b-ad67-5bc621476a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19952
85820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1995285820
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2393101757
Short name T41
Test name
Test status
Simulation time 84184221539 ps
CPU time 1672.34 seconds
Started Mar 24 02:57:06 PM PDT 24
Finished Mar 24 03:24:58 PM PDT 24
Peak memory 281808 kb
Host smart-451741ab-c32a-40e2-9684-802031623901
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393101757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2393101757
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1963737140
Short name T498
Test name
Test status
Simulation time 6641657636 ps
CPU time 570.69 seconds
Started Mar 24 02:57:07 PM PDT 24
Finished Mar 24 03:06:38 PM PDT 24
Peak memory 265452 kb
Host smart-a49db448-95a1-4537-8abc-9d68d54b0a7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963737140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1963737140
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2765684138
Short name T213
Test name
Test status
Simulation time 73864263224 ps
CPU time 647.76 seconds
Started Mar 24 02:57:08 PM PDT 24
Finished Mar 24 03:07:56 PM PDT 24
Peak memory 248096 kb
Host smart-f1e362ce-394b-4443-9065-fe8e0dbdf589
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765684138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2765684138
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.472897676
Short name T86
Test name
Test status
Simulation time 1623973695 ps
CPU time 29.3 seconds
Started Mar 24 02:57:07 PM PDT 24
Finished Mar 24 02:57:37 PM PDT 24
Peak memory 255588 kb
Host smart-34045714-d5e6-4a7f-9277-e4d46a383549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47289
7676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.472897676
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2446922185
Short name T639
Test name
Test status
Simulation time 330279224 ps
CPU time 16.82 seconds
Started Mar 24 02:57:06 PM PDT 24
Finished Mar 24 02:57:23 PM PDT 24
Peak memory 255468 kb
Host smart-b131918d-9e6a-48a1-98d5-5372383c25f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24469
22185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2446922185
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1615175778
Short name T286
Test name
Test status
Simulation time 1604835051 ps
CPU time 67.01 seconds
Started Mar 24 02:57:09 PM PDT 24
Finished Mar 24 02:58:16 PM PDT 24
Peak memory 247852 kb
Host smart-310ef724-52a1-45e7-b4ec-a1a3b10f421c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16151
75778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1615175778
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2919304347
Short name T562
Test name
Test status
Simulation time 5496760500 ps
CPU time 41.22 seconds
Started Mar 24 02:57:06 PM PDT 24
Finished Mar 24 02:57:47 PM PDT 24
Peak memory 249132 kb
Host smart-fdc034d6-2a56-4b4b-b19d-ec28fff9f3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29193
04347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2919304347
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.877464147
Short name T118
Test name
Test status
Simulation time 116861787501 ps
CPU time 5843.33 seconds
Started Mar 24 02:57:06 PM PDT 24
Finished Mar 24 04:34:30 PM PDT 24
Peak memory 338508 kb
Host smart-b3db0b5a-8729-4ed3-939c-14d2283fc807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877464147 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.877464147
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2410108891
Short name T380
Test name
Test status
Simulation time 185871008390 ps
CPU time 2939.65 seconds
Started Mar 24 02:57:14 PM PDT 24
Finished Mar 24 03:46:14 PM PDT 24
Peak memory 288524 kb
Host smart-7ee714cc-e8b9-4b13-9094-e772051f59a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410108891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2410108891
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.155751421
Short name T368
Test name
Test status
Simulation time 11106396792 ps
CPU time 335.31 seconds
Started Mar 24 02:57:09 PM PDT 24
Finished Mar 24 03:02:45 PM PDT 24
Peak memory 256792 kb
Host smart-a368aa21-a5c3-469d-8723-648e0b246d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15575
1421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.155751421
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3557938641
Short name T82
Test name
Test status
Simulation time 643935892 ps
CPU time 44.31 seconds
Started Mar 24 02:57:10 PM PDT 24
Finished Mar 24 02:57:54 PM PDT 24
Peak memory 254972 kb
Host smart-d88b3d84-5683-4e3e-93de-987a0c9f4cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35579
38641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3557938641
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1007591350
Short name T633
Test name
Test status
Simulation time 25833063661 ps
CPU time 1349.57 seconds
Started Mar 24 02:57:15 PM PDT 24
Finished Mar 24 03:19:45 PM PDT 24
Peak memory 285064 kb
Host smart-66374fa9-1ff8-485c-9536-232d6bf3bca4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007591350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1007591350
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2341962528
Short name T455
Test name
Test status
Simulation time 40500424967 ps
CPU time 1183.76 seconds
Started Mar 24 02:57:17 PM PDT 24
Finished Mar 24 03:17:01 PM PDT 24
Peak memory 272184 kb
Host smart-81c24aab-2b69-4c16-afde-621abeeeb1bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341962528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2341962528
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3668102260
Short name T476
Test name
Test status
Simulation time 3981377080 ps
CPU time 165.77 seconds
Started Mar 24 02:57:15 PM PDT 24
Finished Mar 24 03:00:01 PM PDT 24
Peak memory 247856 kb
Host smart-7d15d113-22ca-4cd4-b3a5-b1a0000e6d1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668102260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3668102260
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1922681280
Short name T375
Test name
Test status
Simulation time 457043932 ps
CPU time 25.3 seconds
Started Mar 24 02:57:09 PM PDT 24
Finished Mar 24 02:57:35 PM PDT 24
Peak memory 255328 kb
Host smart-e84597ec-4fa9-4dd7-8c8d-2c62607d7cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19226
81280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1922681280
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2660130717
Short name T584
Test name
Test status
Simulation time 3499559700 ps
CPU time 48.16 seconds
Started Mar 24 02:57:13 PM PDT 24
Finished Mar 24 02:58:01 PM PDT 24
Peak memory 255004 kb
Host smart-c633a5ee-42e1-45f6-8f89-51c63a50d071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26601
30717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2660130717
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1872904067
Short name T554
Test name
Test status
Simulation time 2135044959 ps
CPU time 42.8 seconds
Started Mar 24 02:57:14 PM PDT 24
Finished Mar 24 02:57:56 PM PDT 24
Peak memory 247412 kb
Host smart-0650564e-d279-4cf0-a077-bbb995640433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729
04067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1872904067
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.4074690890
Short name T580
Test name
Test status
Simulation time 93736026 ps
CPU time 6.25 seconds
Started Mar 24 02:57:06 PM PDT 24
Finished Mar 24 02:57:12 PM PDT 24
Peak memory 248820 kb
Host smart-2a31486c-8ffe-473f-a6e1-21d5592342f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40746
90890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4074690890
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1699204437
Short name T3
Test name
Test status
Simulation time 36387326871 ps
CPU time 1716.9 seconds
Started Mar 24 02:57:20 PM PDT 24
Finished Mar 24 03:25:57 PM PDT 24
Peak memory 273504 kb
Host smart-cbd44587-dc5a-4100-b4cf-4e49b90f55fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699204437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1699204437
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3504458567
Short name T663
Test name
Test status
Simulation time 27368693838 ps
CPU time 2785.94 seconds
Started Mar 24 02:57:19 PM PDT 24
Finished Mar 24 03:43:46 PM PDT 24
Peak memory 302724 kb
Host smart-9eff63f9-85a0-4eb6-89bd-af0d1d93254b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504458567 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3504458567
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2361389045
Short name T558
Test name
Test status
Simulation time 36793498819 ps
CPU time 2420.4 seconds
Started Mar 24 02:57:27 PM PDT 24
Finished Mar 24 03:37:48 PM PDT 24
Peak memory 289072 kb
Host smart-df29986b-8abc-4b02-9826-04539c41291f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361389045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2361389045
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.938198347
Short name T443
Test name
Test status
Simulation time 766781130 ps
CPU time 74.33 seconds
Started Mar 24 02:57:22 PM PDT 24
Finished Mar 24 02:58:36 PM PDT 24
Peak memory 248816 kb
Host smart-525aef04-ffd7-45d5-b788-b63d89c72d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93819
8347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.938198347
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3577928819
Short name T461
Test name
Test status
Simulation time 135609643 ps
CPU time 10.12 seconds
Started Mar 24 02:57:23 PM PDT 24
Finished Mar 24 02:57:33 PM PDT 24
Peak memory 251888 kb
Host smart-221ac6f1-959b-485b-bacc-cf93155cab89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
28819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3577928819
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1095452529
Short name T540
Test name
Test status
Simulation time 30977680103 ps
CPU time 1943.72 seconds
Started Mar 24 02:57:25 PM PDT 24
Finished Mar 24 03:29:49 PM PDT 24
Peak memory 267348 kb
Host smart-06d12df6-78d0-4290-a0c8-4375f570aa8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095452529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1095452529
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.233886152
Short name T376
Test name
Test status
Simulation time 354671534193 ps
CPU time 2227 seconds
Started Mar 24 02:57:27 PM PDT 24
Finished Mar 24 03:34:34 PM PDT 24
Peak memory 285284 kb
Host smart-0e6d6fde-df71-441a-8eb9-db00271d8d53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233886152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.233886152
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2668551354
Short name T316
Test name
Test status
Simulation time 33367431400 ps
CPU time 341.56 seconds
Started Mar 24 02:57:23 PM PDT 24
Finished Mar 24 03:03:04 PM PDT 24
Peak memory 247052 kb
Host smart-2ce03b89-d1a1-4368-9f42-649852035da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668551354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2668551354
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2350874483
Short name T390
Test name
Test status
Simulation time 1785476533 ps
CPU time 28.51 seconds
Started Mar 24 02:57:19 PM PDT 24
Finished Mar 24 02:57:48 PM PDT 24
Peak memory 256020 kb
Host smart-cf6c64f6-5593-4f71-a5c1-d80fad458e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23508
74483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2350874483
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2219203072
Short name T478
Test name
Test status
Simulation time 3032483568 ps
CPU time 44.03 seconds
Started Mar 24 02:57:21 PM PDT 24
Finished Mar 24 02:58:05 PM PDT 24
Peak memory 248924 kb
Host smart-241d4d62-8039-433a-bc67-1aa17c52d210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
03072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2219203072
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3038092338
Short name T284
Test name
Test status
Simulation time 1054648237 ps
CPU time 19.3 seconds
Started Mar 24 02:57:20 PM PDT 24
Finished Mar 24 02:57:40 PM PDT 24
Peak memory 254920 kb
Host smart-097e5ff6-0936-4486-84d0-e66f60e6ccbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30380
92338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3038092338
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2479397024
Short name T1
Test name
Test status
Simulation time 1080016502 ps
CPU time 17.15 seconds
Started Mar 24 02:57:18 PM PDT 24
Finished Mar 24 02:57:35 PM PDT 24
Peak memory 248856 kb
Host smart-71b9496d-f51a-40e0-bcf1-4b0ec7087c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793
97024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2479397024
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.104564908
Short name T512
Test name
Test status
Simulation time 64228500677 ps
CPU time 3672.03 seconds
Started Mar 24 02:57:23 PM PDT 24
Finished Mar 24 03:58:36 PM PDT 24
Peak memory 314360 kb
Host smart-3bf0f517-c33d-4d6b-8a5a-f5fd4497b505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104564908 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.104564908
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2492381303
Short name T591
Test name
Test status
Simulation time 34885445431 ps
CPU time 2702.88 seconds
Started Mar 24 02:57:33 PM PDT 24
Finished Mar 24 03:42:37 PM PDT 24
Peak memory 281644 kb
Host smart-e8e18293-4697-46d0-9631-94cfe947bc8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492381303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2492381303
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3993113412
Short name T128
Test name
Test status
Simulation time 6837448597 ps
CPU time 108.28 seconds
Started Mar 24 02:57:29 PM PDT 24
Finished Mar 24 02:59:17 PM PDT 24
Peak memory 249912 kb
Host smart-a96ca87d-d349-4c4e-b6f1-eea6924877b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39931
13412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3993113412
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2363680769
Short name T387
Test name
Test status
Simulation time 1121093316 ps
CPU time 27.52 seconds
Started Mar 24 02:57:26 PM PDT 24
Finished Mar 24 02:57:54 PM PDT 24
Peak memory 255340 kb
Host smart-3b721ccc-4ee3-4263-9aca-b9cf0536f325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
80769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2363680769
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.621973656
Short name T497
Test name
Test status
Simulation time 15099138179 ps
CPU time 1156.94 seconds
Started Mar 24 02:57:38 PM PDT 24
Finished Mar 24 03:16:55 PM PDT 24
Peak memory 270404 kb
Host smart-b47fe59b-8f81-46ac-aeec-f7f2e13093d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621973656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.621973656
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1716577107
Short name T28
Test name
Test status
Simulation time 7349106898 ps
CPU time 916.2 seconds
Started Mar 24 02:57:38 PM PDT 24
Finished Mar 24 03:12:54 PM PDT 24
Peak memory 273484 kb
Host smart-d95d4e01-903b-4d4d-bbf6-1665b632713f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716577107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1716577107
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1165680577
Short name T238
Test name
Test status
Simulation time 2358937562 ps
CPU time 53.66 seconds
Started Mar 24 02:57:28 PM PDT 24
Finished Mar 24 02:58:22 PM PDT 24
Peak memory 255612 kb
Host smart-9b355551-e6b6-45fe-b998-2b41204b9bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
80577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1165680577
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4002944247
Short name T525
Test name
Test status
Simulation time 2890136724 ps
CPU time 52.08 seconds
Started Mar 24 02:57:27 PM PDT 24
Finished Mar 24 02:58:19 PM PDT 24
Peak memory 255200 kb
Host smart-6c092f50-a45e-4fc0-8c21-8bcc1a348d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40029
44247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4002944247
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3126666710
Short name T403
Test name
Test status
Simulation time 559448164 ps
CPU time 28.96 seconds
Started Mar 24 02:57:40 PM PDT 24
Finished Mar 24 02:58:10 PM PDT 24
Peak memory 248432 kb
Host smart-f87fa65a-13ca-4298-a532-3b79d8b44e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
66710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3126666710
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1406524483
Short name T538
Test name
Test status
Simulation time 17951497 ps
CPU time 3.11 seconds
Started Mar 24 02:57:28 PM PDT 24
Finished Mar 24 02:57:31 PM PDT 24
Peak memory 240692 kb
Host smart-1e5b3af7-17b9-4967-b487-57fe6b80baa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14065
24483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1406524483
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.878251302
Short name T306
Test name
Test status
Simulation time 51695352393 ps
CPU time 3728.1 seconds
Started Mar 24 02:57:37 PM PDT 24
Finished Mar 24 03:59:46 PM PDT 24
Peak memory 305664 kb
Host smart-78640388-7b4d-426d-9fbc-665f5fda9c20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878251302 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.878251302
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1606829890
Short name T214
Test name
Test status
Simulation time 205788388381 ps
CPU time 3080.1 seconds
Started Mar 24 02:57:42 PM PDT 24
Finished Mar 24 03:49:03 PM PDT 24
Peak memory 289428 kb
Host smart-234874f2-8bf8-4021-9684-7c150070beed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606829890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1606829890
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1908364564
Short name T684
Test name
Test status
Simulation time 7052682398 ps
CPU time 220.73 seconds
Started Mar 24 02:57:42 PM PDT 24
Finished Mar 24 03:01:23 PM PDT 24
Peak memory 256660 kb
Host smart-40af022d-3ce0-4a38-9d7b-8e729f64e2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19083
64564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1908364564
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3681454825
Short name T627
Test name
Test status
Simulation time 236763321 ps
CPU time 5.21 seconds
Started Mar 24 02:57:41 PM PDT 24
Finished Mar 24 02:57:47 PM PDT 24
Peak memory 239244 kb
Host smart-3a592049-bd62-4747-9565-8b39842b11d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36814
54825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3681454825
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1624594245
Short name T254
Test name
Test status
Simulation time 14039385920 ps
CPU time 1323 seconds
Started Mar 24 02:57:42 PM PDT 24
Finished Mar 24 03:19:45 PM PDT 24
Peak memory 286184 kb
Host smart-223453e8-ddb4-4ae2-a87a-72f516a1bceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624594245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1624594245
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.939997522
Short name T122
Test name
Test status
Simulation time 26943923760 ps
CPU time 1336.55 seconds
Started Mar 24 02:57:47 PM PDT 24
Finished Mar 24 03:20:05 PM PDT 24
Peak memory 287792 kb
Host smart-2450bc9e-e86f-45ee-9ed4-a67030eafdc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939997522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.939997522
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1893499667
Short name T332
Test name
Test status
Simulation time 19025843508 ps
CPU time 210.02 seconds
Started Mar 24 02:57:44 PM PDT 24
Finished Mar 24 03:01:14 PM PDT 24
Peak memory 247792 kb
Host smart-af611290-59b8-4849-a2c8-22b741d7b099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893499667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1893499667
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1190575398
Short name T592
Test name
Test status
Simulation time 904032098 ps
CPU time 47.68 seconds
Started Mar 24 02:57:38 PM PDT 24
Finished Mar 24 02:58:26 PM PDT 24
Peak memory 248876 kb
Host smart-b2c2283c-b516-4c73-9504-08cb24506291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11905
75398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1190575398
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3296819505
Short name T553
Test name
Test status
Simulation time 675816155 ps
CPU time 39.94 seconds
Started Mar 24 02:57:39 PM PDT 24
Finished Mar 24 02:58:20 PM PDT 24
Peak memory 253984 kb
Host smart-ba9f5729-b699-40da-b7ef-83c00be6ac7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968
19505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3296819505
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4037789700
Short name T304
Test name
Test status
Simulation time 833836256 ps
CPU time 51.81 seconds
Started Mar 24 02:57:38 PM PDT 24
Finished Mar 24 02:58:30 PM PDT 24
Peak memory 248860 kb
Host smart-14889465-1d0b-443c-9d9a-fb5749c1984b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
89700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4037789700
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4105653622
Short name T42
Test name
Test status
Simulation time 2973700896 ps
CPU time 259.28 seconds
Started Mar 24 02:57:46 PM PDT 24
Finished Mar 24 03:02:06 PM PDT 24
Peak memory 256432 kb
Host smart-7500a130-aeb1-4482-9915-26bd14a840cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105653622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4105653622
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.901388250
Short name T394
Test name
Test status
Simulation time 121227807333 ps
CPU time 2214.31 seconds
Started Mar 24 02:57:54 PM PDT 24
Finished Mar 24 03:34:48 PM PDT 24
Peak memory 281944 kb
Host smart-590e2d7c-4de5-4831-9844-f99761d9ecca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901388250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.901388250
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.221233012
Short name T444
Test name
Test status
Simulation time 1810919057 ps
CPU time 23.73 seconds
Started Mar 24 02:57:47 PM PDT 24
Finished Mar 24 02:58:12 PM PDT 24
Peak memory 256756 kb
Host smart-77b62ef7-17ac-4c03-8f17-7673885a2d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22123
3012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.221233012
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4250858
Short name T475
Test name
Test status
Simulation time 566063222 ps
CPU time 12.03 seconds
Started Mar 24 02:57:48 PM PDT 24
Finished Mar 24 02:58:01 PM PDT 24
Peak memory 253012 kb
Host smart-989343b9-fada-4dab-ad5e-e24d6071664a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42508
58 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4250858
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.546595696
Short name T343
Test name
Test status
Simulation time 58121114718 ps
CPU time 1386.78 seconds
Started Mar 24 02:57:52 PM PDT 24
Finished Mar 24 03:21:00 PM PDT 24
Peak memory 289252 kb
Host smart-f7d94b05-445a-4597-8c63-11086ccdf820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546595696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.546595696
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2370724961
Short name T608
Test name
Test status
Simulation time 191350064070 ps
CPU time 1973.67 seconds
Started Mar 24 02:57:52 PM PDT 24
Finished Mar 24 03:30:46 PM PDT 24
Peak memory 283688 kb
Host smart-7c4a2108-a955-4a18-a6b3-7d7c235ab97b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370724961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2370724961
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2162341414
Short name T617
Test name
Test status
Simulation time 4400788447 ps
CPU time 189.79 seconds
Started Mar 24 02:57:54 PM PDT 24
Finished Mar 24 03:01:03 PM PDT 24
Peak memory 247840 kb
Host smart-731f71c2-7d2c-4add-bc6d-e76ffca1e641
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162341414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2162341414
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1708639266
Short name T293
Test name
Test status
Simulation time 2224506723 ps
CPU time 37.34 seconds
Started Mar 24 02:57:50 PM PDT 24
Finished Mar 24 02:58:27 PM PDT 24
Peak memory 255584 kb
Host smart-67ca48f2-49f2-4c24-b707-6f8239e9b22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
39266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1708639266
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.305528826
Short name T53
Test name
Test status
Simulation time 344879344 ps
CPU time 18.62 seconds
Started Mar 24 02:57:49 PM PDT 24
Finished Mar 24 02:58:08 PM PDT 24
Peak memory 248884 kb
Host smart-4df4bdb7-1d40-465a-a9ec-2c604ef18b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30552
8826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.305528826
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3915744947
Short name T485
Test name
Test status
Simulation time 70353693 ps
CPU time 5.06 seconds
Started Mar 24 02:57:51 PM PDT 24
Finished Mar 24 02:57:57 PM PDT 24
Peak memory 240696 kb
Host smart-50caacf2-0fe7-4bcc-a6db-cbbb22871781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39157
44947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3915744947
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3819363634
Short name T81
Test name
Test status
Simulation time 4330436770 ps
CPU time 53.31 seconds
Started Mar 24 02:57:47 PM PDT 24
Finished Mar 24 02:58:40 PM PDT 24
Peak memory 256080 kb
Host smart-7566e586-cd6d-44ae-aa43-be4d68d1bcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
63634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3819363634
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3357131205
Short name T560
Test name
Test status
Simulation time 43746617949 ps
CPU time 2804.53 seconds
Started Mar 24 02:58:01 PM PDT 24
Finished Mar 24 03:44:46 PM PDT 24
Peak memory 289300 kb
Host smart-7a5b746a-9f49-488e-9c16-a40e50d6582e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357131205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3357131205
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3130335245
Short name T501
Test name
Test status
Simulation time 5589789451 ps
CPU time 153.46 seconds
Started Mar 24 02:57:55 PM PDT 24
Finished Mar 24 03:00:28 PM PDT 24
Peak memory 256952 kb
Host smart-6a14d239-2c73-4c5d-a9d6-7624c3b85767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31303
35245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3130335245
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2224188878
Short name T527
Test name
Test status
Simulation time 1414157297 ps
CPU time 45.16 seconds
Started Mar 24 02:57:56 PM PDT 24
Finished Mar 24 02:58:41 PM PDT 24
Peak memory 254856 kb
Host smart-34550b31-b003-4bde-b091-df30a72afcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22241
88878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2224188878
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1972786017
Short name T490
Test name
Test status
Simulation time 38926723823 ps
CPU time 943.14 seconds
Started Mar 24 02:58:00 PM PDT 24
Finished Mar 24 03:13:44 PM PDT 24
Peak memory 267356 kb
Host smart-ad7bd609-0e93-42ce-a8be-bbc1ab4f5b3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972786017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1972786017
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.391136435
Short name T647
Test name
Test status
Simulation time 47544922247 ps
CPU time 3061.01 seconds
Started Mar 24 02:58:01 PM PDT 24
Finished Mar 24 03:49:03 PM PDT 24
Peak memory 281716 kb
Host smart-68304a93-2ae9-41e0-a124-c1261f5fa92f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391136435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.391136435
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1738420779
Short name T705
Test name
Test status
Simulation time 163029741 ps
CPU time 8.51 seconds
Started Mar 24 02:57:54 PM PDT 24
Finished Mar 24 02:58:03 PM PDT 24
Peak memory 252332 kb
Host smart-f43699bd-9ad9-4f47-bd1f-e346feb775b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17384
20779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1738420779
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.353889903
Short name T402
Test name
Test status
Simulation time 56025654 ps
CPU time 5.7 seconds
Started Mar 24 02:57:57 PM PDT 24
Finished Mar 24 02:58:03 PM PDT 24
Peak memory 251012 kb
Host smart-acbe833e-1237-4ce2-ba27-b87a8863ae8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
9903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.353889903
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3478084735
Short name T532
Test name
Test status
Simulation time 762948736 ps
CPU time 47.46 seconds
Started Mar 24 02:57:55 PM PDT 24
Finished Mar 24 02:58:43 PM PDT 24
Peak memory 255400 kb
Host smart-4709c891-b471-47d8-8da2-bf91dff7925f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
84735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3478084735
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1984597740
Short name T622
Test name
Test status
Simulation time 352597133 ps
CPU time 30.19 seconds
Started Mar 24 02:57:55 PM PDT 24
Finished Mar 24 02:58:25 PM PDT 24
Peak memory 249240 kb
Host smart-1d6f324d-cebc-44e4-b127-ea7e8887c4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
97740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1984597740
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.836647176
Short name T674
Test name
Test status
Simulation time 55707530114 ps
CPU time 3344.09 seconds
Started Mar 24 02:58:06 PM PDT 24
Finished Mar 24 03:53:51 PM PDT 24
Peak memory 289148 kb
Host smart-430e5206-9ca5-44d6-ace0-6458c0d46fe2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836647176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.836647176
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1323624587
Short name T487
Test name
Test status
Simulation time 98435212128 ps
CPU time 4348.68 seconds
Started Mar 24 02:58:07 PM PDT 24
Finished Mar 24 04:10:36 PM PDT 24
Peak memory 288928 kb
Host smart-4686c9ca-c8be-4171-8db1-2d702040ee70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323624587 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1323624587
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3538258881
Short name T557
Test name
Test status
Simulation time 13981955747 ps
CPU time 1331.25 seconds
Started Mar 24 02:58:10 PM PDT 24
Finished Mar 24 03:20:21 PM PDT 24
Peak memory 289176 kb
Host smart-9c5bcb47-4015-4409-9e66-fe0a354421db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538258881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3538258881
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3628455340
Short name T103
Test name
Test status
Simulation time 4242598683 ps
CPU time 63.82 seconds
Started Mar 24 02:58:10 PM PDT 24
Finished Mar 24 02:59:14 PM PDT 24
Peak memory 256816 kb
Host smart-7e622c51-c4ce-4641-9ad5-8dd9e78408b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36284
55340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3628455340
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1831457498
Short name T586
Test name
Test status
Simulation time 161234810 ps
CPU time 6.34 seconds
Started Mar 24 02:58:10 PM PDT 24
Finished Mar 24 02:58:17 PM PDT 24
Peak memory 251872 kb
Host smart-fb0e51e3-db6e-43a6-b8a9-384af6afebec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18314
57498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1831457498
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3539994538
Short name T348
Test name
Test status
Simulation time 143324535413 ps
CPU time 1485.06 seconds
Started Mar 24 02:58:09 PM PDT 24
Finished Mar 24 03:22:55 PM PDT 24
Peak memory 288888 kb
Host smart-e0ed9a37-8ef0-400d-b4d1-43071098af0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539994538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3539994538
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3803553335
Short name T95
Test name
Test status
Simulation time 23072593825 ps
CPU time 1090.43 seconds
Started Mar 24 02:58:09 PM PDT 24
Finished Mar 24 03:16:20 PM PDT 24
Peak memory 289380 kb
Host smart-5857075a-fd35-47f1-934e-dfdb54d205fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803553335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3803553335
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3992392404
Short name T314
Test name
Test status
Simulation time 42389232510 ps
CPU time 200.22 seconds
Started Mar 24 02:58:09 PM PDT 24
Finished Mar 24 03:01:29 PM PDT 24
Peak memory 248092 kb
Host smart-0dc2a54a-1a82-447f-8137-f67353171e69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992392404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3992392404
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3829410551
Short name T401
Test name
Test status
Simulation time 557074649 ps
CPU time 38.24 seconds
Started Mar 24 02:58:06 PM PDT 24
Finished Mar 24 02:58:44 PM PDT 24
Peak memory 249100 kb
Host smart-4aac124f-644b-485b-8505-575db25ec028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38294
10551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3829410551
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3463607478
Short name T619
Test name
Test status
Simulation time 390783563 ps
CPU time 33.5 seconds
Started Mar 24 02:58:06 PM PDT 24
Finished Mar 24 02:58:40 PM PDT 24
Peak memory 256096 kb
Host smart-b242772b-b3ac-4c8a-a5c2-04a347783c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34636
07478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3463607478
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1653663762
Short name T280
Test name
Test status
Simulation time 264442936 ps
CPU time 17.47 seconds
Started Mar 24 02:58:10 PM PDT 24
Finished Mar 24 02:58:28 PM PDT 24
Peak memory 247412 kb
Host smart-d317dc76-f5c6-4f80-ab2b-db2d3639cfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536
63762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1653663762
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1192889156
Short name T680
Test name
Test status
Simulation time 722129141 ps
CPU time 41.03 seconds
Started Mar 24 02:58:06 PM PDT 24
Finished Mar 24 02:58:47 PM PDT 24
Peak memory 248916 kb
Host smart-fa4c21be-8a58-4dae-a7da-02edc774b477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
89156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1192889156
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3420926043
Short name T279
Test name
Test status
Simulation time 78156565730 ps
CPU time 2912.17 seconds
Started Mar 24 02:58:17 PM PDT 24
Finished Mar 24 03:46:49 PM PDT 24
Peak memory 289796 kb
Host smart-5bff7d07-e4db-4310-a60c-898bd7aeeb42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420926043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3420926043
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.274135729
Short name T200
Test name
Test status
Simulation time 167423383562 ps
CPU time 3946.1 seconds
Started Mar 24 02:58:14 PM PDT 24
Finished Mar 24 04:04:02 PM PDT 24
Peak memory 333532 kb
Host smart-8a93eedd-235f-4c78-9ce6-64b12d0265bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274135729 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.274135729
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.268026974
Short name T221
Test name
Test status
Simulation time 116477953 ps
CPU time 3.35 seconds
Started Mar 24 02:54:06 PM PDT 24
Finished Mar 24 02:54:09 PM PDT 24
Peak memory 249076 kb
Host smart-c9ed3f80-b223-4652-9cda-69a5ee4253a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=268026974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.268026974
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1313553877
Short name T479
Test name
Test status
Simulation time 21049287514 ps
CPU time 1499.25 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 03:19:00 PM PDT 24
Peak memory 272440 kb
Host smart-98670736-6388-45c7-9a58-fdd630e47247
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313553877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1313553877
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2767132433
Short name T427
Test name
Test status
Simulation time 486551655 ps
CPU time 21.08 seconds
Started Mar 24 02:54:02 PM PDT 24
Finished Mar 24 02:54:23 PM PDT 24
Peak memory 248952 kb
Host smart-c4f6a55e-49a0-4e60-a50c-622948221fc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2767132433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2767132433
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.118619943
Short name T393
Test name
Test status
Simulation time 1259869148 ps
CPU time 83.12 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 02:55:24 PM PDT 24
Peak memory 256796 kb
Host smart-dcdc1b1c-1767-42ea-b19e-b93bb403e9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11861
9943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.118619943
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.157185422
Short name T496
Test name
Test status
Simulation time 241892344 ps
CPU time 29.18 seconds
Started Mar 24 02:54:03 PM PDT 24
Finished Mar 24 02:54:32 PM PDT 24
Peak memory 254912 kb
Host smart-c39db6bb-f26d-424e-a2bb-da1f56cb3dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15718
5422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.157185422
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.645057446
Short name T290
Test name
Test status
Simulation time 15654118442 ps
CPU time 1337.95 seconds
Started Mar 24 02:54:03 PM PDT 24
Finished Mar 24 03:16:21 PM PDT 24
Peak memory 289220 kb
Host smart-155529d2-db17-4392-b858-1ce898df63db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645057446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.645057446
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3226546517
Short name T589
Test name
Test status
Simulation time 96938540057 ps
CPU time 319.22 seconds
Started Mar 24 02:54:01 PM PDT 24
Finished Mar 24 02:59:20 PM PDT 24
Peak memory 247832 kb
Host smart-a3d2cb1e-a982-4461-8bcb-3356b6dbd45e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226546517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3226546517
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1653422162
Short name T541
Test name
Test status
Simulation time 1052867120 ps
CPU time 17.6 seconds
Started Mar 24 02:54:02 PM PDT 24
Finished Mar 24 02:54:20 PM PDT 24
Peak memory 248856 kb
Host smart-da640426-b6d2-40dd-8bff-dd3296c2fdd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16534
22162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1653422162
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3462625633
Short name T428
Test name
Test status
Simulation time 1823426497 ps
CPU time 57.67 seconds
Started Mar 24 02:54:02 PM PDT 24
Finished Mar 24 02:55:00 PM PDT 24
Peak memory 247564 kb
Host smart-2458192e-c759-4c8e-acbc-63adeccd1b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
25633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3462625633
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.96800498
Short name T249
Test name
Test status
Simulation time 485061766 ps
CPU time 19.05 seconds
Started Mar 24 02:54:04 PM PDT 24
Finished Mar 24 02:54:23 PM PDT 24
Peak memory 248872 kb
Host smart-87f99321-65ca-4cd5-b9a9-15c7db135e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96800
498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.96800498
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1361512870
Short name T515
Test name
Test status
Simulation time 265775407 ps
CPU time 27.16 seconds
Started Mar 24 02:54:00 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 248956 kb
Host smart-7d483d7c-5cd3-4165-9656-a3564209c320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13615
12870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1361512870
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4239164745
Short name T296
Test name
Test status
Simulation time 23715623367 ps
CPU time 1230.56 seconds
Started Mar 24 02:54:09 PM PDT 24
Finished Mar 24 03:14:40 PM PDT 24
Peak memory 273472 kb
Host smart-860a7c72-9739-4ae3-8b0d-4e2fa83a2320
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239164745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4239164745
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1732191864
Short name T229
Test name
Test status
Simulation time 68774706 ps
CPU time 3.06 seconds
Started Mar 24 02:54:09 PM PDT 24
Finished Mar 24 02:54:12 PM PDT 24
Peak memory 249072 kb
Host smart-af4e9ec6-656d-4c3d-9abc-9e4404854be8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1732191864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1732191864
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3180880836
Short name T12
Test name
Test status
Simulation time 28603592381 ps
CPU time 1805.64 seconds
Started Mar 24 02:54:07 PM PDT 24
Finished Mar 24 03:24:13 PM PDT 24
Peak memory 267336 kb
Host smart-fc778882-fa0a-4355-8d81-2f5c81763747
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180880836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3180880836
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1128004268
Short name T262
Test name
Test status
Simulation time 326039846 ps
CPU time 9.55 seconds
Started Mar 24 02:54:06 PM PDT 24
Finished Mar 24 02:54:16 PM PDT 24
Peak memory 240660 kb
Host smart-1bc603cf-523c-445c-abad-27f9ba0a7c5a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1128004268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1128004268
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.335845904
Short name T408
Test name
Test status
Simulation time 15211285060 ps
CPU time 157.36 seconds
Started Mar 24 02:54:10 PM PDT 24
Finished Mar 24 02:56:47 PM PDT 24
Peak memory 248920 kb
Host smart-08d697c8-6f30-4863-b57a-e5da6c615286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584
5904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.335845904
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1963858265
Short name T239
Test name
Test status
Simulation time 623415819 ps
CPU time 38.88 seconds
Started Mar 24 02:54:09 PM PDT 24
Finished Mar 24 02:54:48 PM PDT 24
Peak memory 255552 kb
Host smart-b22092d3-ce28-4235-aebc-bee1898cf2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19638
58265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1963858265
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.4156547344
Short name T351
Test name
Test status
Simulation time 30192222081 ps
CPU time 1494.23 seconds
Started Mar 24 02:54:08 PM PDT 24
Finished Mar 24 03:19:02 PM PDT 24
Peak memory 289136 kb
Host smart-1e90bee9-5f1a-4db7-995f-901c7b4aca02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156547344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4156547344
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1879692755
Short name T432
Test name
Test status
Simulation time 564164446 ps
CPU time 36.13 seconds
Started Mar 24 02:54:09 PM PDT 24
Finished Mar 24 02:54:45 PM PDT 24
Peak memory 248860 kb
Host smart-19e20099-32b8-4926-8130-fb03593b1deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
92755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1879692755
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2333163979
Short name T371
Test name
Test status
Simulation time 1077613351 ps
CPU time 58.01 seconds
Started Mar 24 02:54:06 PM PDT 24
Finished Mar 24 02:55:05 PM PDT 24
Peak memory 255392 kb
Host smart-1687d0c3-8f62-446f-85fb-093a0c1c9ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23331
63979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2333163979
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.946656534
Short name T88
Test name
Test status
Simulation time 4430071240 ps
CPU time 65.74 seconds
Started Mar 24 02:54:08 PM PDT 24
Finished Mar 24 02:55:14 PM PDT 24
Peak memory 255644 kb
Host smart-af74ee35-cdf5-49ac-8eb1-7910e3e4315b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94665
6534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.946656534
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1312640560
Short name T434
Test name
Test status
Simulation time 589981402 ps
CPU time 11.38 seconds
Started Mar 24 02:54:07 PM PDT 24
Finished Mar 24 02:54:19 PM PDT 24
Peak memory 248796 kb
Host smart-d2eb7660-4314-413b-954b-1ab50993b4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13126
40560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1312640560
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3825960052
Short name T220
Test name
Test status
Simulation time 33397113 ps
CPU time 2.77 seconds
Started Mar 24 02:54:15 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 257228 kb
Host smart-5213af31-a944-4123-9f44-d5d350c3d063
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3825960052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3825960052
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3789190650
Short name T524
Test name
Test status
Simulation time 107442615790 ps
CPU time 1730.99 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 03:23:03 PM PDT 24
Peak memory 267368 kb
Host smart-9f2b7d3f-b70a-49f7-acc2-3e07eb0363a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789190650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3789190650
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3240651065
Short name T683
Test name
Test status
Simulation time 1023046271 ps
CPU time 44.76 seconds
Started Mar 24 02:54:15 PM PDT 24
Finished Mar 24 02:55:00 PM PDT 24
Peak memory 248816 kb
Host smart-69735b76-fcdd-47b6-bdee-515eb00b90ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3240651065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3240651065
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.704597229
Short name T672
Test name
Test status
Simulation time 4137384514 ps
CPU time 224.62 seconds
Started Mar 24 02:54:15 PM PDT 24
Finished Mar 24 02:58:00 PM PDT 24
Peak memory 256708 kb
Host smart-6c5764c2-a043-402d-a121-64c28101553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70459
7229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.704597229
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.470139542
Short name T126
Test name
Test status
Simulation time 223000443 ps
CPU time 20.69 seconds
Started Mar 24 02:54:06 PM PDT 24
Finished Mar 24 02:54:27 PM PDT 24
Peak memory 255288 kb
Host smart-981c5a55-ebe6-4bc3-9879-97527897a2a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47013
9542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.470139542
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1261745588
Short name T288
Test name
Test status
Simulation time 203524190680 ps
CPU time 955.74 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 03:10:08 PM PDT 24
Peak memory 273504 kb
Host smart-f8c59fc1-c932-4001-8903-e57cd0e0a6c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261745588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1261745588
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1037329038
Short name T8
Test name
Test status
Simulation time 52670504935 ps
CPU time 516.52 seconds
Started Mar 24 02:54:14 PM PDT 24
Finished Mar 24 03:02:50 PM PDT 24
Peak memory 247096 kb
Host smart-32bb5f55-0da0-4177-8e6d-2a67c8f463b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037329038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1037329038
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.903614664
Short name T438
Test name
Test status
Simulation time 414174491 ps
CPU time 24.98 seconds
Started Mar 24 02:54:09 PM PDT 24
Finished Mar 24 02:54:34 PM PDT 24
Peak memory 255296 kb
Host smart-3b353fd7-9024-42a0-a223-154044b12c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90361
4664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.903614664
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.158974626
Short name T474
Test name
Test status
Simulation time 516827871 ps
CPU time 26.69 seconds
Started Mar 24 02:54:09 PM PDT 24
Finished Mar 24 02:54:36 PM PDT 24
Peak memory 249124 kb
Host smart-e84b36b2-9c0d-4d8a-8be0-4a2c821bc448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15897
4626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.158974626
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3787498708
Short name T272
Test name
Test status
Simulation time 446626118 ps
CPU time 26.79 seconds
Started Mar 24 02:54:17 PM PDT 24
Finished Mar 24 02:54:44 PM PDT 24
Peak memory 254968 kb
Host smart-63be25e4-ef28-42ae-8817-345979230900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37874
98708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3787498708
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1209913108
Short name T609
Test name
Test status
Simulation time 824390888 ps
CPU time 22.48 seconds
Started Mar 24 02:54:08 PM PDT 24
Finished Mar 24 02:54:31 PM PDT 24
Peak memory 248888 kb
Host smart-e34d015e-f832-4116-b8a2-7d08a3d7d1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12099
13108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1209913108
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.807364302
Short name T58
Test name
Test status
Simulation time 1645797915 ps
CPU time 146.93 seconds
Started Mar 24 02:54:15 PM PDT 24
Finished Mar 24 02:56:42 PM PDT 24
Peak memory 257032 kb
Host smart-0293b7cb-9ed1-46ec-b124-d4d13367d1c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807364302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.807364302
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1146625052
Short name T112
Test name
Test status
Simulation time 100909969208 ps
CPU time 4371.03 seconds
Started Mar 24 02:54:11 PM PDT 24
Finished Mar 24 04:07:03 PM PDT 24
Peak memory 339040 kb
Host smart-29655a31-6405-470a-9033-382bc8703948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146625052 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1146625052
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3210584005
Short name T225
Test name
Test status
Simulation time 44194439 ps
CPU time 3.65 seconds
Started Mar 24 02:54:14 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 249100 kb
Host smart-8eb67c60-6c77-4dbf-ba3f-74029286eff8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3210584005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3210584005
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.331982631
Short name T260
Test name
Test status
Simulation time 52660388546 ps
CPU time 1455.33 seconds
Started Mar 24 02:54:16 PM PDT 24
Finished Mar 24 03:18:31 PM PDT 24
Peak memory 288604 kb
Host smart-59d042c5-0a2e-4c34-9103-830044a1f8b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331982631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.331982631
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1382675462
Short name T386
Test name
Test status
Simulation time 2329622465 ps
CPU time 50.46 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 02:55:03 PM PDT 24
Peak memory 248880 kb
Host smart-641ff307-9a49-439f-8162-32ed30d9d5ec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1382675462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1382675462
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2105036669
Short name T453
Test name
Test status
Simulation time 2344761735 ps
CPU time 155.25 seconds
Started Mar 24 02:54:13 PM PDT 24
Finished Mar 24 02:56:48 PM PDT 24
Peak memory 256728 kb
Host smart-7f5e8fb3-55f3-4e32-ae22-b7a98f470b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21050
36669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2105036669
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.554377476
Short name T656
Test name
Test status
Simulation time 2383525951 ps
CPU time 44.06 seconds
Started Mar 24 02:54:15 PM PDT 24
Finished Mar 24 02:54:59 PM PDT 24
Peak memory 249060 kb
Host smart-dc060808-af9f-4ab2-ba2c-98ccbd3bfac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55437
7476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.554377476
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.170344901
Short name T325
Test name
Test status
Simulation time 44270672377 ps
CPU time 2386.1 seconds
Started Mar 24 02:54:13 PM PDT 24
Finished Mar 24 03:33:59 PM PDT 24
Peak memory 289128 kb
Host smart-b2569192-110d-4415-ba74-ff7fa977f566
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170344901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.170344901
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3368959649
Short name T25
Test name
Test status
Simulation time 77610440598 ps
CPU time 1396.48 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 03:17:29 PM PDT 24
Peak memory 273532 kb
Host smart-0ecaa8c1-4d67-450b-b0ca-28394e1e766a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368959649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3368959649
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2437709618
Short name T311
Test name
Test status
Simulation time 19932207115 ps
CPU time 374.11 seconds
Started Mar 24 02:54:14 PM PDT 24
Finished Mar 24 03:00:28 PM PDT 24
Peak memory 247072 kb
Host smart-22d5dbb4-950f-4424-aae4-692d19147259
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437709618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2437709618
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1916552005
Short name T49
Test name
Test status
Simulation time 3128171395 ps
CPU time 23.48 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 02:54:35 PM PDT 24
Peak memory 256116 kb
Host smart-2065a6b1-ee49-4f90-a9f0-67f1d82e435d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
52005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1916552005
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1800939995
Short name T607
Test name
Test status
Simulation time 796713725 ps
CPU time 14.62 seconds
Started Mar 24 02:54:12 PM PDT 24
Finished Mar 24 02:54:26 PM PDT 24
Peak memory 254728 kb
Host smart-d00f0b85-8208-4e38-9d59-2644a85b3d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
39995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1800939995
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1423085715
Short name T127
Test name
Test status
Simulation time 522933340 ps
CPU time 33.15 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 02:54:51 PM PDT 24
Peak memory 248516 kb
Host smart-c952dd52-ca30-4598-bd96-873f05dbd5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14230
85715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1423085715
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1219141577
Short name T504
Test name
Test status
Simulation time 634929101 ps
CPU time 16.19 seconds
Started Mar 24 02:54:17 PM PDT 24
Finished Mar 24 02:54:33 PM PDT 24
Peak memory 249176 kb
Host smart-8893fac6-7d48-4401-8279-16917cfd2e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
41577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1219141577
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1254248218
Short name T236
Test name
Test status
Simulation time 39155419 ps
CPU time 3.34 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 02:54:24 PM PDT 24
Peak memory 249328 kb
Host smart-b1f1fa4a-3540-494e-8dc9-aece2225a832
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1254248218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1254248218
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3142843200
Short name T97
Test name
Test status
Simulation time 86342441341 ps
CPU time 1830.77 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 03:24:50 PM PDT 24
Peak memory 273416 kb
Host smart-491798c9-ac21-4f78-a5a2-aa09233a5cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142843200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3142843200
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1586649972
Short name T643
Test name
Test status
Simulation time 6191975878 ps
CPU time 18.93 seconds
Started Mar 24 02:54:16 PM PDT 24
Finished Mar 24 02:54:35 PM PDT 24
Peak memory 248904 kb
Host smart-664d3a88-7df8-4f7d-bf81-7bb7a5b34cdc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1586649972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1586649972
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3895533986
Short name T517
Test name
Test status
Simulation time 637670036 ps
CPU time 18.76 seconds
Started Mar 24 02:54:20 PM PDT 24
Finished Mar 24 02:54:39 PM PDT 24
Peak memory 254696 kb
Host smart-22ff30ca-8675-4600-a4f0-25eef03edb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38955
33986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3895533986
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.998500419
Short name T477
Test name
Test status
Simulation time 642189459 ps
CPU time 38.5 seconds
Started Mar 24 02:54:16 PM PDT 24
Finished Mar 24 02:54:54 PM PDT 24
Peak memory 255940 kb
Host smart-3300bf48-c7d2-45fe-8b8a-02a1e22bdde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99850
0419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.998500419
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2555700158
Short name T345
Test name
Test status
Simulation time 42494286044 ps
CPU time 928.54 seconds
Started Mar 24 02:54:21 PM PDT 24
Finished Mar 24 03:09:49 PM PDT 24
Peak memory 273452 kb
Host smart-a0a60a22-fea1-48b7-aed5-8ea275b61a18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555700158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2555700158
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3800407742
Short name T595
Test name
Test status
Simulation time 64154610534 ps
CPU time 407.52 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 03:01:06 PM PDT 24
Peak memory 247988 kb
Host smart-ac82b5cb-0bc1-4908-b4f1-353bb4775160
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800407742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3800407742
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3028889345
Short name T495
Test name
Test status
Simulation time 1734516958 ps
CPU time 59.55 seconds
Started Mar 24 02:54:15 PM PDT 24
Finished Mar 24 02:55:14 PM PDT 24
Peak memory 257084 kb
Host smart-38927a17-c050-44f6-bf8f-f4591ff2923b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
89345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3028889345
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3369591171
Short name T642
Test name
Test status
Simulation time 597967248 ps
CPU time 20.2 seconds
Started Mar 24 02:54:16 PM PDT 24
Finished Mar 24 02:54:37 PM PDT 24
Peak memory 254860 kb
Host smart-8dc603f2-aef6-4b5d-ada3-4a2e6c4f3f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695
91171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3369591171
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.857399884
Short name T102
Test name
Test status
Simulation time 247201493 ps
CPU time 13.56 seconds
Started Mar 24 02:54:17 PM PDT 24
Finished Mar 24 02:54:31 PM PDT 24
Peak memory 247280 kb
Host smart-d7cd6bae-e3eb-48b1-8756-6db8ea9b5a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85739
9884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.857399884
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.153279818
Short name T421
Test name
Test status
Simulation time 385113995 ps
CPU time 15.78 seconds
Started Mar 24 02:54:16 PM PDT 24
Finished Mar 24 02:54:32 PM PDT 24
Peak memory 248884 kb
Host smart-a4c6d4a2-4069-4e93-b627-2c468c35afb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15327
9818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.153279818
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3911678625
Short name T270
Test name
Test status
Simulation time 104863263493 ps
CPU time 1848.74 seconds
Started Mar 24 02:54:18 PM PDT 24
Finished Mar 24 03:25:07 PM PDT 24
Peak memory 298084 kb
Host smart-0d136682-6822-4ad9-a3f1-b449ff260c2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911678625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3911678625
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1469400094
Short name T659
Test name
Test status
Simulation time 10599729219 ps
CPU time 1214.23 seconds
Started Mar 24 02:54:19 PM PDT 24
Finished Mar 24 03:14:34 PM PDT 24
Peak memory 284832 kb
Host smart-c5f57a96-07e9-49e9-8368-48ff9c1b43ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469400094 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1469400094
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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