Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	120833	1			T2	4055		T4	4026		T18	6
class_i[0x1]	69153	1			T2	2418		T19	13		T24	13
class_i[0x2]	75132	1			T2	6		T4	2		T19	327
class_i[0x3]	32486	1			T4	31		T19	3		T13	2717

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	73258	1			T2	1514		T4	964		T19	20
alert[0x1]	71500	1			T2	2160		T4	972		T18	6
alert[0x2]	74998	1			T2	1438		T4	1089		T19	462
alert[0x3]	77848	1			T2	1367		T4	1034		T19	277

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

297306

1

T2

6479

T4

4059

T18

6

esc_ping_fail

298

1

T6

5

T7

3

T8

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	73174	1			T2	1514		T4	964		T19	20
esc_integrity_fail	alert[0x1]	71417	1			T2	2160		T4	972		T18	6
esc_integrity_fail	alert[0x2]	74928	1			T2	1438		T4	1089		T19	462
esc_integrity_fail	alert[0x3]	77787	1			T2	1367		T4	1034		T19	277
esc_ping_fail	alert[0x0]	84	1			T6	1		T7	1		T8	3
esc_ping_fail	alert[0x1]	83	1			T6	2		T7	1		T8	1
esc_ping_fail	alert[0x2]	70	1			T6	2		T8	2		T224	2
esc_ping_fail	alert[0x3]	61	1			T7	1		T8	3		T225	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	120759	1			T2	4055		T4	4026		T18	6
esc_integrity_fail	class_i[0x1]	69057	1			T2	2418		T19	13		T24	13
esc_integrity_fail	class_i[0x2]	75066	1			T2	6		T4	2		T19	327
esc_integrity_fail	class_i[0x3]	32424	1			T4	31		T19	3		T13	2717
esc_ping_fail	class_i[0x0]	74	1			T6	1		T265	5		T274	4
esc_ping_fail	class_i[0x1]	96	1			T6	1		T224	2		T225	1
esc_ping_fail	class_i[0x2]	66	1			T6	1		T8	9		T224	1
esc_ping_fail	class_i[0x3]	62	1			T6	2		T7	3		T224	1