Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	756152024	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	756152024	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	756152024	755992484	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	756152024	755992484	0	0
tb.dut.EdnKnownO_A	0	0	756152024	755992484	0	0
tb.dut.EscPKnownO_A	0	0	756152024	755992484	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	756152024	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	756152024	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	756152024	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	756152024	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	756152024	70	0	0
tb.dut.IrqAKnownO_A	0	0	756152024	755992484	0	0
tb.dut.IrqBKnownO_A	0	0	756152024	755992484	0	0
tb.dut.IrqCKnownO_A	0	0	756152024	755992484	0	0
tb.dut.IrqDKnownO_A	0	0	756152024	755992484	0	0
tb.dut.TlAReadyKnownO_A	0	0	756152024	755992484	0	0
tb.dut.TlDValidKnownO_A	0	0	756152024	755992484	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	784946862	4404491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	784946862	19449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	784946862	19396	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	784946862	20524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	784946862	18425	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	784946862	18621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	784946862	19341	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	784946862	19607	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	784946862	20648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	784946862	20752	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	784946862	18310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	784946862	18558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	784946862	19524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	784946862	19097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	784946862	19417	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	784946862	19270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	784946862	18028	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	784946862	18525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	784946862	18320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	784946862	19627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	784946862	20667	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	784946862	18266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	784946862	20717	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	784946862	18386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	784946862	19173	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	784946862	20837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	784946862	18470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	784946862	19376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	784946862	19572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	784946862	18116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	784946862	19531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	784946862	19019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	784946862	18171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	784946862	19358	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	784946862	20884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	784946862	19501	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	784946862	18289	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	784946862	20584	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	784946862	19430	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	784946862	19416	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	784946862	18244	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	784946862	18147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	784946862	19181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	784946862	20420	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	784946862	19309	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	784946862	19870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	784946862	19463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	784946862	19590	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	784946862	19345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	784946862	18516	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	784946862	20357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	784946862	20416	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	784946862	18602	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	784946862	19586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	784946862	18026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	784946862	19532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	784946862	18303	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	784946862	19442	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	784946862	19268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	784946862	18055	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	784946862	18235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	784946862	19581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	784946862	18505	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	784946862	19663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	784946862	18995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	784946862	19857	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	784946862	20186	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	784946862	19267	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	784946862	18495	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	784946862	19185	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	784946862	36766	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	784946862	19581	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	784946862	18108	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	784946862	18385	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	784946862	19429	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	784946862	18216	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	784946862	18272	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	784946862	20639	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	784946862	19417	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	756152024	5244	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	756152024	274813	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	756152024	371981522	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	756152024	270	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	756152024	872	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	756152024	42	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	756152024	404	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	755979266	262792351	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	756152024	958	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	756152024	933	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	756152024	912	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	756152024	890	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	756152024	1464	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	756152024	149228	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	756152024	1364	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	756152024	56	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	756152024	1293	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	756152024	1083	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	756152024	755992484	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	756152024	4574	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	756152024	214193	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	756152024	406851599	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	756152024	204	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	756152024	532	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	756152024	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	756152024	241	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	755979266	339124461	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	756152024	621	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	756152024	612	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	756152024	608	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	756152024	599	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	756152024	2379	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	756152024	216239	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	756152024	2280	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	756152024	76	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	756152024	1241	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	756152024	1031	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	756152024	755992484	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	756152024	1741	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	756152024	200777	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	756152024	435598926	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	756152024	247	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	756152024	523	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	756152024	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	756152024	223	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	755979266	322445793	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	756152024	607	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	756152024	601	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	756152024	590	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	756152024	586	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	756152024	1469	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	756152024	151438	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	756152024	1376	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	756152024	71	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	756152024	1276	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	756152024	1066	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	756152024	755992484	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	756152024	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	756152024	3035	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	756152024	195670	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	756152024	456736830	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	756152024	268	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	756152024	561	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	756152024	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	756152024	276	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	755979266	330178370	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	756152024	643	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	756152024	634	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	756152024	621	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	756152024	608	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	756152024	1558	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	756152024	170868	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	756152024	1465	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	756152024	63	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	756152024	1301	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	756152024	1091	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	756152024	755992484	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	784946862	156868037	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	784946862	784288228	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	784946862	784288228	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	784946862	206729165	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	784946862	784288228	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	784946862	784288228	0	0
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