Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	0	44	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	0	44	100.00	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	168	1			T5	1		T19	3		T14	1
index[0x1]	188	1			T2	1		T3	1		T5	2
index[0x2]	177	1			T2	2		T3	1		T19	2
index[0x3]	168	1			T2	1		T4	2		T19	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	242	1			T2	3		T3	1		T5	1
lens_less_than_1000[1]	137	1			T5	2		T19	3		T12	1
lens_less_than_1000[2]	96	1			T2	1		T4	1		T26	1
lens_less_than_1000[3]	59	1			T3	1		T6	1		T28	1
lens_less_than_1000[4]	61	1			T19	2		T58	1		T29	2
lens_less_than_1000[5]	30	1			T26	1		T66	2		T102	1
lens_less_than_1000[6]	32	1			T4	1		T60	3		T207	1
lens_less_than_1000[7]	20	1			T39	1		T65	1		T46	1
lens_less_than_1000[8]	12	1			T79	1		T90	1		T292	1
lens_less_than_1000[9]	5	1			T30	1		T7	1		T293	1
len_2	7	1			T108	1		T242	1		T249	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	0	44	100.00

Automatically Generated Cross Bins for len_per_esc_sig

Bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	53	1			T5	1		T19	1		T17	1
index[0x0]	lens_less_than_1000[1]	23	1			T19	1		T14	1		T89	1
index[0x0]	lens_less_than_1000[2]	26	1			T25	1		T294	1		T295	1
index[0x0]	lens_less_than_1000[3]	12	1			T25	1		T45	1		T89	1
index[0x0]	lens_less_than_1000[4]	28	1			T19	1		T58	1		T102	1
index[0x0]	lens_less_than_1000[5]	9	1			T102	1		T67	2		T90	1
index[0x0]	lens_less_than_1000[6]	9	1			T207	1		T267	1		T296	1
index[0x0]	lens_less_than_1000[7]	4	1			T297	1		T254	1		T239	1
index[0x0]	lens_less_than_1000[8]	2	1			T298	1		T235	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T30	1		-	-		-	-
index[0x0]	len_2	1	1			T108	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	55	1			T2	1		T24	2		T40	1
index[0x1]	lens_less_than_1000[1]	53	1			T5	2		T19	1		T13	5
index[0x1]	lens_less_than_1000[2]	21	1			T26	1		T28	1		T40	2
index[0x1]	lens_less_than_1000[3]	11	1			T3	1		T206	1		T46	1
index[0x1]	lens_less_than_1000[4]	21	1			T29	2		T65	1		T102	1
index[0x1]	lens_less_than_1000[5]	7	1			T77	1		T47	1		T299	1
index[0x1]	lens_less_than_1000[6]	8	1			T60	2		T300	1		T239	2
index[0x1]	lens_less_than_1000[7]	5	1			T65	1		T108	1		T53	1
index[0x1]	lens_less_than_1000[8]	3	1			T49	1		T96	1		T301	1
index[0x1]	lens_less_than_1000[9]	2	1			T7	1		T293	1		-	-
index[0x1]	len_2	2	1			T302	1		T303	1		-	-
index[0x2]	lens_less_than_1000[0]	77	1			T2	2		T3	1		T19	1
index[0x2]	lens_less_than_1000[1]	30	1			T57	1		T89	1		T67	1
index[0x2]	lens_less_than_1000[2]	22	1			T30	1		T56	1		T99	1
index[0x2]	lens_less_than_1000[3]	17	1			T102	1		T79	1		T304	6
index[0x2]	lens_less_than_1000[4]	7	1			T19	1		T71	1		T305	1
index[0x2]	lens_less_than_1000[5]	9	1			T26	1		T66	1		T47	1
index[0x2]	lens_less_than_1000[6]	4	1			T60	1		T68	1		T306	1
index[0x2]	lens_less_than_1000[7]	5	1			T39	1		T70	1		T299	1
index[0x2]	lens_less_than_1000[8]	4	1			T90	1		T292	1		T245	1
index[0x2]	lens_less_than_1000[9]	1	1			T307	1		-	-		-	-
index[0x2]	len_2	1	1			T249	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	57	1			T19	1		T29	1		T25	1
index[0x3]	lens_less_than_1000[1]	31	1			T19	1		T12	1		T45	1
index[0x3]	lens_less_than_1000[2]	27	1			T2	1		T4	1		T28	1
index[0x3]	lens_less_than_1000[3]	19	1			T6	1		T28	1		T37	1
index[0x3]	lens_less_than_1000[4]	5	1			T67	1		T238	1		T308	1
index[0x3]	lens_less_than_1000[5]	5	1			T66	1		T309	1		T239	1
index[0x3]	lens_less_than_1000[6]	11	1			T4	1		T216	1		T79	1
index[0x3]	lens_less_than_1000[7]	6	1			T46	1		T310	1		T311	1
index[0x3]	lens_less_than_1000[8]	3	1			T79	1		T74	1		T55	1
index[0x3]	lens_less_than_1000[9]	1	1			T312	1		-	-		-	-
index[0x3]	len_2	3	1			T242	1		T313	1		T314	1