Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	56	1			T19	1		T28	1		T46	2
class_index[0x1]	76	1			T4	1		T18	1		T19	1
class_index[0x2]	71	1			T19	3		T44	2		T59	1
class_index[0x3]	63	1			T4	1		T19	7		T24	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	113	1			T19	1		T26	1		T28	1
intr_timeout_cnt[1]	56	1			T18	1		T19	7		T13	1
intr_timeout_cnt[2]	22	1			T44	2		T111	1		T237	1
intr_timeout_cnt[3]	13	1			T109	1		T46	1		T71	1
intr_timeout_cnt[4]	9	1			T19	1		T25	1		T65	1
intr_timeout_cnt[5]	20	1			T4	1		T19	1		T66	1
intr_timeout_cnt[6]	9	1			T4	1		T238	1		T47	2
intr_timeout_cnt[7]	4	1			T67	1		T69	1		T53	1
intr_timeout_cnt[8]	12	1			T19	2		T90	1		T81	1
intr_timeout_cnt[9]	8	1			T49	1		T239	2		T240	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T28	1		T46	2		T72	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T19	1		T241	1		T81	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T73	1		T74	1		T85	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T71	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T47	1		T242	1		T236	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T69	1		T70	1		T243	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T244	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T53	1		T245	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T81	1		T246	3		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T239	1		T247	2		-	-
class_index[0x1]	intr_timeout_cnt[0]	38	1			T26	1		T29	1		T68	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T18	1		T13	1		T26	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T79	1		T248	1		T54	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T249	1		T244	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	2	1			T19	1		T47	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	12	1			T4	1		T66	1		T45	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T245	1		T96	1		T250	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T67	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T251	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	3	1			T239	1		T240	1		T252	1
class_index[0x2]	intr_timeout_cnt[0]	32	1			T59	1		T89	1		T46	2
class_index[0x2]	intr_timeout_cnt[1]	14	1			T19	1		T25	1		T79	3
class_index[0x2]	intr_timeout_cnt[2]	7	1			T44	2		T83	1		T253	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T46	1		T254	1		T249	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T65	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T19	1		T74	1		T83	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T238	1		T47	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	4	1			T19	1		T90	1		T255	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T49	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	21	1			T19	1		T61	1		T110	1
class_index[0x3]	intr_timeout_cnt[1]	21	1			T19	5		T24	1		T59	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T111	1		T237	1		T245	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T109	1		T243	1		T244	1
class_index[0x3]	intr_timeout_cnt[4]	3	1			T25	1		T239	1		T236	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T255	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T4	1		T47	1		T256	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T69	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T19	1		T83	1		T240	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T257	1		-	-		-	-