Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	387794	1			T1	29		T2	2933		T3	873
all_values[1]	387794	1			T1	29		T2	2933		T3	873
all_values[2]	387794	1			T1	29		T2	2933		T3	873
all_values[3]	387794	1			T1	29		T2	2933		T3	873

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

771646

1

T1

63

T2

5975

T3

1811

auto[1]

779530

1

T1

53

T2

5757

T3

1681

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

909404

1

T1

102

T2

6410

T3

2742

auto[1]

641772

1

T1

14

T2

5322

T3

750

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	108325	1			T1	9		T2	775		T3	453
all_values[0]	auto[0]	auto[1]	84912	1			T1	9		T2	712		T3	1
all_values[0]	auto[1]	auto[0]	109642	1			T1	6		T2	754		T3	418
all_values[0]	auto[1]	auto[1]	84915	1			T1	5		T2	692		T3	1
all_values[1]	auto[0]	auto[0]	114670	1			T1	14		T2	847		T3	354
all_values[1]	auto[0]	auto[1]	78269	1			T2	692		T3	106		T4	211
all_values[1]	auto[1]	auto[0]	116536	1			T1	15		T2	758		T3	315
all_values[1]	auto[1]	auto[1]	78319	1			T2	636		T3	98		T4	221
all_values[2]	auto[0]	auto[0]	113702	1			T1	15		T2	805		T3	292
all_values[2]	auto[0]	auto[1]	78598	1			T2	642		T3	165		T4	301
all_values[2]	auto[1]	auto[0]	115951	1			T1	14		T2	801		T3	260
all_values[2]	auto[1]	auto[1]	79543	1			T2	685		T3	156		T4	277
all_values[3]	auto[0]	auto[0]	114803	1			T1	16		T2	863		T3	321
all_values[3]	auto[0]	auto[1]	78367	1			T2	639		T3	119		T4	311
all_values[3]	auto[1]	auto[0]	115775	1			T1	13		T2	807		T3	329
all_values[3]	auto[1]	auto[1]	78849	1			T2	624		T3	104		T4	280