Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	387794	1			T1	29		T2	2933		T3	873
all_pins[1]	387794	1			T1	29		T2	2933		T3	873
all_pins[2]	387794	1			T1	29		T2	2933		T3	873
all_pins[3]	387794	1			T1	29		T2	2933		T3	873

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1229550	1			T1	111		T2	9095		T3	3133
values[0x1]	321626	1			T1	5		T2	2637		T3	359
transitions[0x0=>0x1]	213514	1			T1	4		T2	1698		T3	296
transitions[0x1=>0x0]	213771	1			T1	5		T2	1699		T3	296

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	302879	1			T1	24		T2	2241		T3	872
all_pins[0]	values[0x1]	84915	1			T1	5		T2	692		T3	1
all_pins[0]	transitions[0x0=>0x1]	84133	1			T1	4		T2	680		T3	1
all_pins[0]	transitions[0x1=>0x0]	78324	1			T2	613		T3	104		T4	274
all_pins[1]	values[0x0]	309475	1			T1	29		T2	2297		T3	775
all_pins[1]	values[0x1]	78319	1			T2	636		T3	98		T4	221
all_pins[1]	transitions[0x0=>0x1]	42047	1			T2	342		T3	98		T4	112
all_pins[1]	transitions[0x1=>0x0]	48643	1			T1	5		T2	398		T3	1
all_pins[2]	values[0x0]	308251	1			T1	29		T2	2248		T3	717
all_pins[2]	values[0x1]	79543	1			T2	685		T3	156		T4	277
all_pins[2]	transitions[0x0=>0x1]	44202	1			T2	369		T3	121		T4	201
all_pins[2]	transitions[0x1=>0x0]	42978	1			T2	320		T3	63		T4	145
all_pins[3]	values[0x0]	308945	1			T1	29		T2	2309		T3	769
all_pins[3]	values[0x1]	78849	1			T2	624		T3	104		T4	280
all_pins[3]	transitions[0x0=>0x1]	43132	1			T2	307		T3	76		T4	193
all_pins[3]	transitions[0x1=>0x0]	43826	1			T2	368		T3	128		T4	190