Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	98244	1			T2	520		T4	191		T12	1128
accum_cnt_1000	255337	1			T2	3092		T3	843		T4	214
accum_cnt_100	30111	1			T1	7		T2	265		T3	227
accum_cnt_50	81256	1			T1	13		T2	316		T3	174
accum_cnt_10	203949	1			T1	1		T2	2494		T3	63
accum_cnt_0	422702	1			T1	63		T2	1564		T3	1337

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	287091	1			T1	21		T2	2121		T3	661
class_index[0x1]	287091	1			T1	21		T2	2121		T3	661
class_index[0x2]	287091	1			T1	21		T2	2121		T3	661
class_index[0x3]	287091	1			T1	21		T2	2121		T3	661

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	30603	1			T4	191		T12	642		T17	110
class_index[0x0]	accum_cnt_1000	68049	1			T2	7		T4	174		T12	663
class_index[0x0]	accum_cnt_100	7616	1			T1	7		T2	61		T4	11
class_index[0x0]	accum_cnt_50	18969	1			T1	13		T2	129		T4	18
class_index[0x0]	accum_cnt_10	52877	1			T1	1		T2	1225		T4	126
class_index[0x0]	accum_cnt_0	88423	1			T2	699		T3	661		T4	200
class_index[0x1]	accum_cnt_2000	22901	1			T2	219		T12	486		T13	179
class_index[0x1]	accum_cnt_1000	64829	1			T2	205		T3	355		T4	1
class_index[0x1]	accum_cnt_100	7135	1			T2	28		T3	150		T4	29
class_index[0x1]	accum_cnt_50	19545	1			T2	22		T3	111		T4	28
class_index[0x1]	accum_cnt_10	44902	1			T2	1040		T3	36		T4	22
class_index[0x1]	accum_cnt_0	114648	1			T1	21		T2	374		T3	9
class_index[0x2]	accum_cnt_2000	23396	1			T2	293		T13	270		T14	547
class_index[0x2]	accum_cnt_1000	64523	1			T2	1386		T3	488		T4	30
class_index[0x2]	accum_cnt_100	9473	1			T2	80		T3	77		T4	53
class_index[0x2]	accum_cnt_50	18952	1			T2	87		T3	63		T4	55
class_index[0x2]	accum_cnt_10	53478	1			T2	31		T3	27		T4	75
class_index[0x2]	accum_cnt_0	104308	1			T1	21		T2	244		T3	6
class_index[0x3]	accum_cnt_2000	21344	1			T2	8		T14	567		T44	104
class_index[0x3]	accum_cnt_1000	57936	1			T2	1494		T4	9		T5	767
class_index[0x3]	accum_cnt_100	5887	1			T2	96		T4	60		T5	78
class_index[0x3]	accum_cnt_50	23790	1			T2	78		T4	63		T5	63
class_index[0x3]	accum_cnt_10	52692	1			T2	198		T4	143		T18	15
class_index[0x3]	accum_cnt_0	115323	1			T1	21		T2	247		T3	661