Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9532	1			T2	112		T26	75		T28	191
alert[0x1]	6155	1			T4	8		T66	1		T78	3
alert[0x2]	5495	1			T24	13		T78	2		T224	1
alert[0x3]	10224	1			T2	1		T4	48		T40	6
alert[0x4]	6727	1			T19	4		T26	67		T44	214
alert[0x5]	13915	1			T13	77		T44	3937		T28	122
alert[0x6]	8720	1			T18	4		T24	3		T6	1
alert[0x7]	4625	1			T13	31		T44	14		T25	9
alert[0x8]	7393	1			T26	270		T44	166		T28	70
alert[0x9]	12486	1			T26	13		T44	118		T99	49
alert[0xa]	2039	1			T4	29		T13	112		T26	12
alert[0xb]	9394	1			T2	14		T4	1		T13	24
alert[0xc]	6429	1			T19	1		T13	77		T26	30
alert[0xd]	1573	1			T4	4		T24	6		T26	4
alert[0xe]	4535	1			T13	38		T26	4		T44	20
alert[0xf]	9122	1			T13	58		T44	125		T28	198
alert[0x10]	11492	1			T4	34		T13	18		T44	89
alert[0x11]	5780	1			T26	58		T66	1		T225	1
alert[0x12]	8105	1			T6	3		T26	6		T28	82
alert[0x13]	6111	1			T2	10		T4	535		T19	1
alert[0x14]	9341	1			T26	1200		T44	320		T40	50
alert[0x15]	5616	1			T26	36		T44	432		T25	19
alert[0x16]	14377	1			T5	1		T19	1		T13	198
alert[0x17]	6987	1			T18	9		T13	16		T75	76
alert[0x18]	7361	1			T2	12		T4	1		T13	1374
alert[0x19]	9020	1			T26	5		T44	289		T28	267
alert[0x1a]	5949	1			T2	35		T13	84		T26	55
alert[0x1b]	11808	1			T2	570		T4	18		T13	2
alert[0x1c]	6221	1			T13	6		T28	27		T99	47
alert[0x1d]	8586	1			T4	43		T24	18		T66	2
alert[0x1e]	14949	1			T2	49		T24	5		T26	25
alert[0x1f]	5772	1			T4	7		T24	1		T26	65
alert[0x20]	9245	1			T13	105		T26	10		T28	10
alert[0x21]	5765	1			T2	1		T18	28		T13	15
alert[0x22]	8990	1			T3	1		T13	5		T24	10
alert[0x23]	4135	1			T18	1		T13	28		T26	6
alert[0x24]	7359	1			T2	5		T4	7		T26	319
alert[0x25]	6752	1			T4	8		T13	86		T24	2
alert[0x26]	7327	1			T44	39		T28	20		T224	1
alert[0x27]	3407	1			T19	12		T13	311		T25	105
alert[0x28]	13087	1			T2	17		T4	88		T13	18
alert[0x29]	6249	1			T26	25		T28	39		T25	19
alert[0x2a]	4490	1			T2	114		T13	80		T24	2
alert[0x2b]	5256	1			T13	18		T6	2		T44	320
alert[0x2c]	15597	1			T13	105		T26	5		T44	14
alert[0x2d]	5964	1			T44	63		T28	17		T37	2
alert[0x2e]	6030	1			T6	1		T26	936		T8	1
alert[0x2f]	6111	1			T18	4		T5	2		T19	3
alert[0x30]	2739	1			T19	3		T13	40		T26	345
alert[0x31]	13757	1			T4	77		T44	31		T78	1
alert[0x32]	13679	1			T26	2		T44	48		T28	166
alert[0x33]	6401	1			T2	29		T13	35		T26	72
alert[0x34]	3897	1			T13	17		T44	17		T28	28
alert[0x35]	6498	1			T2	434		T24	1		T6	1
alert[0x36]	8192	1			T18	4		T13	1276		T26	37
alert[0x37]	12823	1			T2	10		T4	17		T24	1
alert[0x38]	5714	1			T4	56		T13	20		T26	7
alert[0x39]	7294	1			T2	1		T40	60		T110	4
alert[0x3a]	4412	1			T2	2		T26	110		T44	281
alert[0x3b]	7754	1			T18	1		T28	39		T78	99
alert[0x3c]	3021	1			T2	26		T6	2		T44	66
alert[0x3d]	5779	1			T2	583		T13	6		T28	256
alert[0x3e]	4445	1			T13	7		T44	27		T25	581
alert[0x3f]	7336	1			T2	20		T19	6		T6	1
alert[0x40]	11333	1			T24	35		T26	1		T44	194

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	135751	1			T2	2019		T4	981		T19	29
class_i[0x1]	146315	1			T2	13		T5	3		T19	2
class_i[0x2]	113283	1			T2	13		T3	1		T18	51
class_i[0x3]	101328	1			T6	2		T44	7947		T28	7

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

495966

1

T2

2045

T4

981

T18

51

alert_ping_fail

711

1

T3

1

T5

3

T6

14

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9528	1			T2	112		T26	75		T28	191
alert_integrity_fail	alert[0x1]	6148	1			T4	8		T66	1		T78	3
alert_integrity_fail	alert[0x2]	5477	1			T24	13		T78	2		T262	211
alert_integrity_fail	alert[0x3]	10217	1			T2	1		T4	48		T40	6
alert_integrity_fail	alert[0x4]	6711	1			T19	4		T26	67		T44	214
alert_integrity_fail	alert[0x5]	13896	1			T13	77		T44	3937		T28	122
alert_integrity_fail	alert[0x6]	8705	1			T18	4		T24	3		T26	2
alert_integrity_fail	alert[0x7]	4616	1			T13	31		T44	14		T25	9
alert_integrity_fail	alert[0x8]	7380	1			T26	270		T44	166		T28	70
alert_integrity_fail	alert[0x9]	12474	1			T26	13		T44	118		T99	49
alert_integrity_fail	alert[0xa]	2028	1			T4	29		T13	112		T26	12
alert_integrity_fail	alert[0xb]	9388	1			T2	14		T4	1		T13	24
alert_integrity_fail	alert[0xc]	6419	1			T19	1		T13	77		T26	30
alert_integrity_fail	alert[0xd]	1562	1			T4	4		T24	6		T26	4
alert_integrity_fail	alert[0xe]	4525	1			T13	38		T26	4		T44	20
alert_integrity_fail	alert[0xf]	9112	1			T13	58		T44	125		T28	198
alert_integrity_fail	alert[0x10]	11479	1			T4	34		T13	18		T44	89
alert_integrity_fail	alert[0x11]	5769	1			T26	58		T66	1		T77	115
alert_integrity_fail	alert[0x12]	8093	1			T26	6		T28	82		T57	1
alert_integrity_fail	alert[0x13]	6099	1			T2	10		T4	535		T19	1
alert_integrity_fail	alert[0x14]	9323	1			T26	1200		T44	320		T40	50
alert_integrity_fail	alert[0x15]	5604	1			T26	36		T44	432		T25	19
alert_integrity_fail	alert[0x16]	14358	1			T19	1		T13	198		T28	38
alert_integrity_fail	alert[0x17]	6976	1			T18	9		T13	16		T75	76
alert_integrity_fail	alert[0x18]	7348	1			T2	12		T4	1		T13	1374
alert_integrity_fail	alert[0x19]	9013	1			T26	5		T44	289		T28	267
alert_integrity_fail	alert[0x1a]	5938	1			T2	35		T13	84		T26	55
alert_integrity_fail	alert[0x1b]	11795	1			T2	570		T4	18		T13	2
alert_integrity_fail	alert[0x1c]	6210	1			T13	6		T28	27		T99	47
alert_integrity_fail	alert[0x1d]	8573	1			T4	43		T24	18		T66	2
alert_integrity_fail	alert[0x1e]	14934	1			T2	49		T24	5		T26	25
alert_integrity_fail	alert[0x1f]	5767	1			T4	7		T24	1		T26	65
alert_integrity_fail	alert[0x20]	9235	1			T13	105		T26	10		T28	10
alert_integrity_fail	alert[0x21]	5754	1			T2	1		T18	28		T13	15
alert_integrity_fail	alert[0x22]	8974	1			T13	5		T24	10		T26	30
alert_integrity_fail	alert[0x23]	4126	1			T18	1		T13	28		T26	6
alert_integrity_fail	alert[0x24]	7349	1			T2	5		T4	7		T26	319
alert_integrity_fail	alert[0x25]	6737	1			T4	8		T13	86		T24	2
alert_integrity_fail	alert[0x26]	7320	1			T44	39		T28	20		T99	111
alert_integrity_fail	alert[0x27]	3397	1			T19	12		T13	311		T25	105
alert_integrity_fail	alert[0x28]	13070	1			T2	17		T4	88		T13	18
alert_integrity_fail	alert[0x29]	6233	1			T26	25		T28	39		T25	19
alert_integrity_fail	alert[0x2a]	4474	1			T2	114		T13	80		T24	2
alert_integrity_fail	alert[0x2b]	5245	1			T13	18		T44	320		T28	273
alert_integrity_fail	alert[0x2c]	15586	1			T13	105		T26	5		T44	14
alert_integrity_fail	alert[0x2d]	5952	1			T44	63		T28	17		T40	22
alert_integrity_fail	alert[0x2e]	6019	1			T26	936		T89	182		T69	133
alert_integrity_fail	alert[0x2f]	6103	1			T18	4		T19	3		T13	248
alert_integrity_fail	alert[0x30]	2730	1			T19	3		T13	40		T26	345
alert_integrity_fail	alert[0x31]	13743	1			T4	77		T44	31		T78	1
alert_integrity_fail	alert[0x32]	13669	1			T26	2		T44	48		T28	166
alert_integrity_fail	alert[0x33]	6390	1			T2	29		T13	35		T26	72
alert_integrity_fail	alert[0x34]	3893	1			T13	17		T44	17		T28	28
alert_integrity_fail	alert[0x35]	6486	1			T2	434		T24	1		T44	60
alert_integrity_fail	alert[0x36]	8184	1			T18	4		T13	1276		T26	37
alert_integrity_fail	alert[0x37]	12809	1			T2	10		T4	17		T24	1
alert_integrity_fail	alert[0x38]	5705	1			T4	56		T13	20		T26	7
alert_integrity_fail	alert[0x39]	7288	1			T2	1		T40	60		T110	4
alert_integrity_fail	alert[0x3a]	4403	1			T2	2		T26	110		T44	281
alert_integrity_fail	alert[0x3b]	7749	1			T18	1		T28	39		T78	99
alert_integrity_fail	alert[0x3c]	3007	1			T2	26		T44	66		T28	33
alert_integrity_fail	alert[0x3d]	5770	1			T2	583		T13	6		T28	256
alert_integrity_fail	alert[0x3e]	4441	1			T13	7		T44	27		T25	581
alert_integrity_fail	alert[0x3f]	7330	1			T2	20		T19	6		T26	108
alert_integrity_fail	alert[0x40]	11330	1			T24	35		T26	1		T44	194
alert_ping_fail	alert[0x0]	4	1			T100	1		T263	2		T264	1
alert_ping_fail	alert[0x1]	7	1			T226	1		T265	1		T266	1
alert_ping_fail	alert[0x2]	18	1			T224	1		T267	1		T268	1
alert_ping_fail	alert[0x3]	7	1			T263	1		T269	2		T270	1
alert_ping_fail	alert[0x4]	16	1			T7	1		T265	1		T271	1
alert_ping_fail	alert[0x5]	19	1			T7	1		T225	1		T271	1
alert_ping_fail	alert[0x6]	15	1			T6	1		T8	1		T226	1
alert_ping_fail	alert[0x7]	9	1			T37	1		T258	2		T272	1
alert_ping_fail	alert[0x8]	13	1			T265	1		T215	2		T273	2
alert_ping_fail	alert[0x9]	12	1			T274	1		T215	1		T275	1
alert_ping_fail	alert[0xa]	11	1			T225	1		T265	1		T214	1
alert_ping_fail	alert[0xb]	6	1			T6	1		T263	1		T276	1
alert_ping_fail	alert[0xc]	10	1			T224	1		T274	1		T267	1
alert_ping_fail	alert[0xd]	11	1			T215	1		T277	1		T263	1
alert_ping_fail	alert[0xe]	10	1			T226	1		T278	1		T273	1
alert_ping_fail	alert[0xf]	10	1			T7	1		T225	1		T226	1
alert_ping_fail	alert[0x10]	13	1			T226	1		T268	2		T279	1
alert_ping_fail	alert[0x11]	11	1			T225	1		T277	1		T280	2
alert_ping_fail	alert[0x12]	12	1			T6	3		T8	1		T265	1
alert_ping_fail	alert[0x13]	12	1			T225	1		T265	1		T281	1
alert_ping_fail	alert[0x14]	18	1			T8	1		T260	1		T265	1
alert_ping_fail	alert[0x15]	12	1			T274	1		T215	1		T271	1
alert_ping_fail	alert[0x16]	19	1			T5	1		T8	2		T261	1
alert_ping_fail	alert[0x17]	11	1			T215	1		T267	1		T268	2
alert_ping_fail	alert[0x18]	13	1			T7	1		T274	1		T215	2
alert_ping_fail	alert[0x19]	7	1			T281	1		T278	1		T263	1
alert_ping_fail	alert[0x1a]	11	1			T224	1		T268	1		T282	1
alert_ping_fail	alert[0x1b]	13	1			T6	1		T281	1		T278	3
alert_ping_fail	alert[0x1c]	11	1			T278	1		T283	2		T280	2
alert_ping_fail	alert[0x1d]	13	1			T37	2		T8	3		T225	1
alert_ping_fail	alert[0x1e]	15	1			T8	4		T215	1		T277	2
alert_ping_fail	alert[0x1f]	5	1			T37	1		T8	1		T268	1
alert_ping_fail	alert[0x20]	10	1			T226	1		T265	1		T215	1
alert_ping_fail	alert[0x21]	11	1			T7	1		T275	1		T276	1
alert_ping_fail	alert[0x22]	16	1			T3	1		T259	1		T215	1
alert_ping_fail	alert[0x23]	9	1			T224	1		T267	1		T279	2
alert_ping_fail	alert[0x24]	10	1			T225	1		T226	2		T215	1
alert_ping_fail	alert[0x25]	15	1			T278	1		T267	1		T279	2
alert_ping_fail	alert[0x26]	7	1			T224	1		T225	1		T281	2
alert_ping_fail	alert[0x27]	10	1			T267	1		T279	1		T275	1
alert_ping_fail	alert[0x28]	17	1			T225	1		T226	1		T274	1
alert_ping_fail	alert[0x29]	16	1			T7	2		T225	1		T271	1
alert_ping_fail	alert[0x2a]	16	1			T224	1		T215	1		T267	2
alert_ping_fail	alert[0x2b]	11	1			T6	2		T274	1		T280	1
alert_ping_fail	alert[0x2c]	11	1			T265	1		T268	1		T284	2
alert_ping_fail	alert[0x2d]	12	1			T37	2		T258	1		T285	1
alert_ping_fail	alert[0x2e]	11	1			T6	1		T8	1		T225	1
alert_ping_fail	alert[0x2f]	8	1			T5	2		T6	1		T225	1
alert_ping_fail	alert[0x30]	9	1			T226	1		T274	1		T273	1
alert_ping_fail	alert[0x31]	14	1			T8	1		T225	2		T271	1
alert_ping_fail	alert[0x32]	10	1			T224	1		T225	1		T215	1
alert_ping_fail	alert[0x33]	11	1			T278	1		T268	1		T283	1
alert_ping_fail	alert[0x34]	4	1			T8	1		T286	1		T287	1
alert_ping_fail	alert[0x35]	12	1			T6	1		T226	1		T279	1
alert_ping_fail	alert[0x36]	8	1			T225	1		T226	1		T274	1
alert_ping_fail	alert[0x37]	14	1			T225	1		T226	2		T274	1
alert_ping_fail	alert[0x38]	9	1			T279	1		T283	1		T276	2
alert_ping_fail	alert[0x39]	6	1			T265	1		T281	1		T288	1
alert_ping_fail	alert[0x3a]	9	1			T225	1		T265	1		T274	1
alert_ping_fail	alert[0x3b]	5	1			T226	2		T275	1		T269	1
alert_ping_fail	alert[0x3c]	14	1			T6	2		T8	1		T226	1
alert_ping_fail	alert[0x3d]	9	1			T8	1		T274	1		T215	1
alert_ping_fail	alert[0x3e]	4	1			T277	1		T100	1		T289	1
alert_ping_fail	alert[0x3f]	6	1			T6	1		T225	1		T226	1
alert_ping_fail	alert[0x40]	3	1			T279	1		T290	1		T291	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	135569	1			T2	2019		T4	981		T19	29
alert_integrity_fail	class_i[0x1]	146140	1			T2	13		T19	2		T13	4551
alert_integrity_fail	class_i[0x2]	113107	1			T2	13		T18	51		T24	5
alert_integrity_fail	class_i[0x3]	101150	1			T44	7947		T28	7		T25	4232
alert_ping_fail	class_i[0x0]	182	1			T6	9		T7	1		T8	16
alert_ping_fail	class_i[0x1]	175	1			T5	3		T6	2		T8	1
alert_ping_fail	class_i[0x2]	176	1			T3	1		T6	1		T7	5
alert_ping_fail	class_i[0x3]	178	1			T6	2		T7	1		T224	1