Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.65 100.00 100.00 100.00 99.38 99.76


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2824402506 Mar 26 12:55:59 PM PDT 24 Mar 26 12:56:07 PM PDT 24 82312854 ps
T772 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2918012364 Mar 26 12:57:49 PM PDT 24 Mar 26 12:57:54 PM PDT 24 51239247 ps
T773 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.329134544 Mar 26 12:57:09 PM PDT 24 Mar 26 12:57:11 PM PDT 24 8734330 ps
T145 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1916182213 Mar 26 12:57:37 PM PDT 24 Mar 26 01:00:49 PM PDT 24 1974836635 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1301129947 Mar 26 12:56:10 PM PDT 24 Mar 26 12:56:25 PM PDT 24 91249955 ps
T775 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2993884014 Mar 26 12:58:00 PM PDT 24 Mar 26 12:58:02 PM PDT 24 8108824 ps
T776 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1305984531 Mar 26 12:57:07 PM PDT 24 Mar 26 12:57:12 PM PDT 24 65279043 ps
T167 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3189995974 Mar 26 12:55:57 PM PDT 24 Mar 26 12:55:59 PM PDT 24 412729746 ps
T163 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.202297874 Mar 26 12:57:37 PM PDT 24 Mar 26 12:57:42 PM PDT 24 56255518 ps
T162 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1379526085 Mar 26 12:57:42 PM PDT 24 Mar 26 12:58:29 PM PDT 24 1928491321 ps
T777 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2793678271 Mar 26 12:55:48 PM PDT 24 Mar 26 12:55:50 PM PDT 24 12428458 ps
T121 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3733186478 Mar 26 12:57:49 PM PDT 24 Mar 26 01:15:57 PM PDT 24 68683415098 ps
T147 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3145709443 Mar 26 12:57:38 PM PDT 24 Mar 26 01:15:30 PM PDT 24 151291353037 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.529290421 Mar 26 12:55:49 PM PDT 24 Mar 26 12:56:13 PM PDT 24 314868813 ps
T779 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.192087380 Mar 26 12:56:47 PM PDT 24 Mar 26 12:57:36 PM PDT 24 999014650 ps
T780 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2803551956 Mar 26 12:57:48 PM PDT 24 Mar 26 12:58:12 PM PDT 24 350068200 ps
T781 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3288998398 Mar 26 12:56:12 PM PDT 24 Mar 26 12:56:18 PM PDT 24 34821570 ps
T782 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.198709466 Mar 26 12:58:01 PM PDT 24 Mar 26 12:58:02 PM PDT 24 16035536 ps
T127 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3729933197 Mar 26 12:57:37 PM PDT 24 Mar 26 01:12:36 PM PDT 24 12867603802 ps
T783 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3385821542 Mar 26 12:55:47 PM PDT 24 Mar 26 12:56:01 PM PDT 24 459946530 ps
T784 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.201010379 Mar 26 12:56:57 PM PDT 24 Mar 26 12:57:10 PM PDT 24 353738682 ps
T157 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2378320970 Mar 26 12:56:37 PM PDT 24 Mar 26 12:56:42 PM PDT 24 269214617 ps
T166 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2204396559 Mar 26 12:56:47 PM PDT 24 Mar 26 12:57:10 PM PDT 24 239519496 ps
T785 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1274313483 Mar 26 12:58:12 PM PDT 24 Mar 26 12:58:14 PM PDT 24 8124849 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4190694371 Mar 26 12:55:50 PM PDT 24 Mar 26 12:55:59 PM PDT 24 37243695 ps
T164 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2062704746 Mar 26 12:57:10 PM PDT 24 Mar 26 12:57:13 PM PDT 24 179269730 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.998636145 Mar 26 12:55:59 PM PDT 24 Mar 26 12:56:05 PM PDT 24 742445368 ps
T788 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1862371763 Mar 26 12:56:01 PM PDT 24 Mar 26 12:56:03 PM PDT 24 6124552 ps
T789 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1687879901 Mar 26 12:57:49 PM PDT 24 Mar 26 12:57:57 PM PDT 24 233093380 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1248050114 Mar 26 12:57:33 PM PDT 24 Mar 26 12:57:41 PM PDT 24 92728392 ps
T146 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1928030469 Mar 26 12:56:46 PM PDT 24 Mar 26 12:59:03 PM PDT 24 1816124930 ps
T791 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2116842265 Mar 26 12:57:49 PM PDT 24 Mar 26 12:58:01 PM PDT 24 517775849 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1828756927 Mar 26 12:56:38 PM PDT 24 Mar 26 12:59:49 PM PDT 24 5835525095 ps
T148 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1102209431 Mar 26 12:55:50 PM PDT 24 Mar 26 01:14:10 PM PDT 24 34873192079 ps
T793 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1960294125 Mar 26 12:57:17 PM PDT 24 Mar 26 12:57:39 PM PDT 24 165849063 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1014077857 Mar 26 12:57:49 PM PDT 24 Mar 26 12:58:22 PM PDT 24 503603090 ps
T795 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4291774342 Mar 26 12:56:57 PM PDT 24 Mar 26 12:56:58 PM PDT 24 12411599 ps
T131 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1414897734 Mar 26 12:57:41 PM PDT 24 Mar 26 01:00:06 PM PDT 24 19829232186 ps
T796 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.148671691 Mar 26 12:57:37 PM PDT 24 Mar 26 12:57:44 PM PDT 24 46819169 ps
T797 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2282540028 Mar 26 12:57:29 PM PDT 24 Mar 26 12:57:44 PM PDT 24 98355961 ps
T798 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2846025228 Mar 26 12:57:42 PM PDT 24 Mar 26 12:57:43 PM PDT 24 19838011 ps
T799 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1066005663 Mar 26 12:56:10 PM PDT 24 Mar 26 12:56:31 PM PDT 24 158308766 ps
T800 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.242125006 Mar 26 12:57:18 PM PDT 24 Mar 26 12:57:20 PM PDT 24 13927123 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.775188246 Mar 26 12:56:47 PM PDT 24 Mar 26 12:56:59 PM PDT 24 580979625 ps
T802 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.69550550 Mar 26 12:56:36 PM PDT 24 Mar 26 12:57:32 PM PDT 24 713019228 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2742874175 Mar 26 12:57:51 PM PDT 24 Mar 26 12:58:34 PM PDT 24 1614270914 ps
T804 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2027610304 Mar 26 12:56:47 PM PDT 24 Mar 26 12:56:56 PM PDT 24 162060947 ps
T805 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.975900967 Mar 26 12:57:52 PM PDT 24 Mar 26 12:58:12 PM PDT 24 962406390 ps
T149 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3157602213 Mar 26 12:57:16 PM PDT 24 Mar 26 01:10:06 PM PDT 24 4449118560 ps
T806 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.497976202 Mar 26 12:56:46 PM PDT 24 Mar 26 12:56:49 PM PDT 24 19365416 ps
T807 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.377418953 Mar 26 12:56:09 PM PDT 24 Mar 26 01:02:22 PM PDT 24 18087622560 ps
T161 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1811400834 Mar 26 12:57:16 PM PDT 24 Mar 26 12:57:21 PM PDT 24 50985842 ps
T808 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.46291030 Mar 26 12:57:59 PM PDT 24 Mar 26 12:58:01 PM PDT 24 19823937 ps
T809 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2413733295 Mar 26 12:56:36 PM PDT 24 Mar 26 12:56:38 PM PDT 24 14338545 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.10135877 Mar 26 12:55:57 PM PDT 24 Mar 26 12:56:30 PM PDT 24 181161536 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3856155120 Mar 26 12:55:51 PM PDT 24 Mar 26 01:01:30 PM PDT 24 6010628530 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1847993308 Mar 26 12:56:48 PM PDT 24 Mar 26 12:57:08 PM PDT 24 541363320 ps
T813 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1247576936 Mar 26 12:56:46 PM PDT 24 Mar 26 12:56:50 PM PDT 24 63480869 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3495293259 Mar 26 12:55:59 PM PDT 24 Mar 26 01:03:14 PM PDT 24 9166851013 ps
T815 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4236863039 Mar 26 12:57:48 PM PDT 24 Mar 26 01:00:47 PM PDT 24 2701590906 ps
T816 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2544443061 Mar 26 12:57:05 PM PDT 24 Mar 26 12:57:23 PM PDT 24 299357382 ps
T817 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2694766109 Mar 26 12:57:16 PM PDT 24 Mar 26 12:57:38 PM PDT 24 1766185844 ps
T818 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3633857525 Mar 26 12:56:50 PM PDT 24 Mar 26 12:56:55 PM PDT 24 97287176 ps
T156 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.972179093 Mar 26 12:57:28 PM PDT 24 Mar 26 12:58:17 PM PDT 24 5642039452 ps
T133 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2622515850 Mar 26 12:57:49 PM PDT 24 Mar 26 01:04:56 PM PDT 24 12870033652 ps
T819 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.330342145 Mar 26 12:57:41 PM PDT 24 Mar 26 12:58:09 PM PDT 24 331515436 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1123322381 Mar 26 12:56:11 PM PDT 24 Mar 26 12:56:18 PM PDT 24 389302809 ps
T821 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2706335503 Mar 26 12:58:03 PM PDT 24 Mar 26 12:58:05 PM PDT 24 23324893 ps
T822 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3533794816 Mar 26 12:57:06 PM PDT 24 Mar 26 12:57:16 PM PDT 24 755233941 ps
T823 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2954287417 Mar 26 12:56:10 PM PDT 24 Mar 26 12:56:16 PM PDT 24 55694792 ps
T140 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.358919487 Mar 26 12:56:27 PM PDT 24 Mar 26 01:16:52 PM PDT 24 19112143114 ps
T824 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1932084526 Mar 26 12:56:36 PM PDT 24 Mar 26 12:59:09 PM PDT 24 8438611807 ps
T825 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.241282091 Mar 26 12:57:49 PM PDT 24 Mar 26 12:58:01 PM PDT 24 3363008998 ps
T826 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1626700760 Mar 26 12:57:59 PM PDT 24 Mar 26 12:58:00 PM PDT 24 12800767 ps
T184 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1174561271 Mar 26 12:57:07 PM PDT 24 Mar 26 01:01:42 PM PDT 24 2199409236 ps
T827 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.680247237 Mar 26 12:57:17 PM PDT 24 Mar 26 12:57:24 PM PDT 24 124987475 ps
T828 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3595265119 Mar 26 12:58:11 PM PDT 24 Mar 26 12:58:13 PM PDT 24 9509222 ps
T829 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2761896238 Mar 26 12:56:47 PM PDT 24 Mar 26 12:57:12 PM PDT 24 188412364 ps
T830 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1363178364 Mar 26 12:57:38 PM PDT 24 Mar 26 12:57:52 PM PDT 24 173384717 ps
T831 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3387038309 Mar 26 12:55:59 PM PDT 24 Mar 26 12:56:05 PM PDT 24 173494155 ps
T159 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2051711305 Mar 26 12:55:47 PM PDT 24 Mar 26 12:56:22 PM PDT 24 464607927 ps

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3644009438
Short name T2
Test name
Test status
Simulation time 31358045614 ps
CPU time 3053.27 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:59:54 PM PDT 24
Peak memory 322064 kb
Host smart-e2714f6f-0d2b-4b5c-afac-9daee33a5c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644009438 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3644009438
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.229099563
Short name T26
Test name
Test status
Simulation time 142441819318 ps
CPU time 2195.72 seconds
Started Mar 26 02:10:40 PM PDT 24
Finished Mar 26 02:47:16 PM PDT 24
Peak memory 290008 kb
Host smart-b353b2f9-1329-464c-a07a-cab7eed24561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229099563 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.229099563
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.660974356
Short name T10
Test name
Test status
Simulation time 819674555 ps
CPU time 13.06 seconds
Started Mar 26 02:06:58 PM PDT 24
Finished Mar 26 02:07:11 PM PDT 24
Peak memory 277780 kb
Host smart-283a55fd-205c-4113-b3a0-7030c4effc0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=660974356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.660974356
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1451049597
Short name T151
Test name
Test status
Simulation time 4266160345 ps
CPU time 69.78 seconds
Started Mar 26 12:56:00 PM PDT 24
Finished Mar 26 12:57:10 PM PDT 24
Peak memory 252328 kb
Host smart-b5ff8102-d070-4917-93f1-7ed4ff216d4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1451049597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1451049597
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1574660009
Short name T28
Test name
Test status
Simulation time 257376502993 ps
CPU time 1942.2 seconds
Started Mar 26 02:09:31 PM PDT 24
Finished Mar 26 02:41:53 PM PDT 24
Peak memory 300900 kb
Host smart-a1da4fc0-3518-4f85-ad11-08676a10de7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574660009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1574660009
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.456129300
Short name T115
Test name
Test status
Simulation time 29538109450 ps
CPU time 372.09 seconds
Started Mar 26 12:57:52 PM PDT 24
Finished Mar 26 01:04:04 PM PDT 24
Peak memory 265016 kb
Host smart-df2c2172-1bbb-48fc-82b0-483f760004ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=456129300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.456129300
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3249286365
Short name T75
Test name
Test status
Simulation time 162906844561 ps
CPU time 3624.1 seconds
Started Mar 26 02:11:20 PM PDT 24
Finished Mar 26 03:11:44 PM PDT 24
Peak memory 298656 kb
Host smart-b2364a50-034e-42e5-9281-d60d365d23b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249286365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3249286365
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4224828635
Short name T33
Test name
Test status
Simulation time 686868697 ps
CPU time 12.1 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:08:15 PM PDT 24
Peak memory 240676 kb
Host smart-7bb8a74a-b709-4910-a96d-341f1829e275
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4224828635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4224828635
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.564185660
Short name T5
Test name
Test status
Simulation time 69824860259 ps
CPU time 2081.96 seconds
Started Mar 26 02:08:23 PM PDT 24
Finished Mar 26 02:43:06 PM PDT 24
Peak memory 270504 kb
Host smart-9dbf6b92-75dc-4f91-878e-c9e1ebc264ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564185660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.564185660
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2505783380
Short name T83
Test name
Test status
Simulation time 49021355916 ps
CPU time 4831.23 seconds
Started Mar 26 02:09:36 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 339156 kb
Host smart-38cd415a-25e8-4281-bd84-5baa6cc1b3f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505783380 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2505783380
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2071868057
Short name T705
Test name
Test status
Simulation time 744739052785 ps
CPU time 2601.43 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:50:03 PM PDT 24
Peak memory 289664 kb
Host smart-8ae14de6-75c4-4864-b03e-daa9c140007b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071868057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2071868057
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3014589556
Short name T128
Test name
Test status
Simulation time 12632529112 ps
CPU time 1022.1 seconds
Started Mar 26 12:56:11 PM PDT 24
Finished Mar 26 01:13:14 PM PDT 24
Peak memory 265332 kb
Host smart-cfaed9eb-173e-4bc1-816d-97ca5fca41c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014589556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3014589556
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.685929275
Short name T19
Test name
Test status
Simulation time 131372270040 ps
CPU time 1785.48 seconds
Started Mar 26 02:08:20 PM PDT 24
Finished Mar 26 02:38:05 PM PDT 24
Peak memory 282132 kb
Host smart-7901afcd-8b12-4909-9fe1-1b9bc20e7695
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685929275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.685929275
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3469586702
Short name T46
Test name
Test status
Simulation time 46834632101 ps
CPU time 2038.29 seconds
Started Mar 26 02:07:49 PM PDT 24
Finished Mar 26 02:41:48 PM PDT 24
Peak memory 302176 kb
Host smart-643a5168-a287-4ae1-81c5-b2db2f596f26
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469586702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3469586702
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3657146445
Short name T114
Test name
Test status
Simulation time 2220856747 ps
CPU time 370.87 seconds
Started Mar 26 12:57:27 PM PDT 24
Finished Mar 26 01:03:38 PM PDT 24
Peak memory 265120 kb
Host smart-70ab70d5-4972-4263-8a6e-734ab2ecffaa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657146445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3657146445
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3060645750
Short name T239
Test name
Test status
Simulation time 47765344264 ps
CPU time 2518.6 seconds
Started Mar 26 02:10:39 PM PDT 24
Finished Mar 26 02:52:38 PM PDT 24
Peak memory 289584 kb
Host smart-998a63db-5c50-40d5-b15a-5d4259bc2220
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060645750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3060645750
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1916182213
Short name T145
Test name
Test status
Simulation time 1974836635 ps
CPU time 191.26 seconds
Started Mar 26 12:57:37 PM PDT 24
Finished Mar 26 01:00:49 PM PDT 24
Peak memory 264976 kb
Host smart-6f188f61-9897-44cd-9ec5-6161c8ffec21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916182213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1916182213
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3733186478
Short name T121
Test name
Test status
Simulation time 68683415098 ps
CPU time 1087.76 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 01:15:57 PM PDT 24
Peak memory 264980 kb
Host smart-b7587f82-0932-4e25-a0f0-5db59dbcec01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733186478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3733186478
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3212071613
Short name T225
Test name
Test status
Simulation time 66426700358 ps
CPU time 557.39 seconds
Started Mar 26 02:08:58 PM PDT 24
Finished Mar 26 02:18:16 PM PDT 24
Peak memory 248180 kb
Host smart-af90ea0c-d1ee-40a4-a16c-8c462c7a67a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212071613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3212071613
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1417587603
Short name T234
Test name
Test status
Simulation time 10651370 ps
CPU time 1.73 seconds
Started Mar 26 12:57:27 PM PDT 24
Finished Mar 26 12:57:30 PM PDT 24
Peak memory 235676 kb
Host smart-af8c9fe1-ad88-4878-841f-42916852cf85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1417587603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1417587603
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2329844530
Short name T175
Test name
Test status
Simulation time 83272707635 ps
CPU time 1233.3 seconds
Started Mar 26 02:07:31 PM PDT 24
Finished Mar 26 02:28:05 PM PDT 24
Peak memory 265368 kb
Host smart-d53ddcf1-1734-442a-a44c-cb252d57b788
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329844530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2329844530
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1849297975
Short name T134
Test name
Test status
Simulation time 24346783130 ps
CPU time 159.68 seconds
Started Mar 26 12:57:30 PM PDT 24
Finished Mar 26 01:00:10 PM PDT 24
Peak memory 265052 kb
Host smart-a8650c15-55b2-4338-9b57-6e6167a17612
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1849297975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1849297975
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2317760731
Short name T282
Test name
Test status
Simulation time 28841046098 ps
CPU time 1769.02 seconds
Started Mar 26 02:06:40 PM PDT 24
Finished Mar 26 02:36:10 PM PDT 24
Peak memory 270380 kb
Host smart-83a27047-32fb-47e0-869d-f86190350286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317760731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2317760731
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2461037253
Short name T290
Test name
Test status
Simulation time 26610208388 ps
CPU time 608.82 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:18:30 PM PDT 24
Peak memory 248128 kb
Host smart-edb80647-7615-4d86-83a4-d864ade399c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461037253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2461037253
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3729933197
Short name T127
Test name
Test status
Simulation time 12867603802 ps
CPU time 898.25 seconds
Started Mar 26 12:57:37 PM PDT 24
Finished Mar 26 01:12:36 PM PDT 24
Peak memory 272400 kb
Host smart-78b47e51-daef-4057-a9ba-1daea27cadb3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729933197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3729933197
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.4141523551
Short name T265
Test name
Test status
Simulation time 9694385163 ps
CPU time 405.34 seconds
Started Mar 26 02:07:36 PM PDT 24
Finished Mar 26 02:14:22 PM PDT 24
Peak memory 248992 kb
Host smart-3767422d-c18f-43bc-a281-82e34bd80e7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141523551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.4141523551
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1384593530
Short name T296
Test name
Test status
Simulation time 33808131582 ps
CPU time 1419.87 seconds
Started Mar 26 02:10:54 PM PDT 24
Finished Mar 26 02:34:34 PM PDT 24
Peak memory 288948 kb
Host smart-a7fa3272-9fe3-4ee6-8ff0-098fad40b9fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384593530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1384593530
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.209043493
Short name T116
Test name
Test status
Simulation time 15512927036 ps
CPU time 333.62 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 01:01:44 PM PDT 24
Peak memory 271896 kb
Host smart-8dd9d766-bec7-4bb5-9b6c-06ea54bb705b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=209043493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.209043493
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1383357769
Short name T37
Test name
Test status
Simulation time 88892077913 ps
CPU time 2379.72 seconds
Started Mar 26 02:12:16 PM PDT 24
Finished Mar 26 02:51:57 PM PDT 24
Peak memory 282372 kb
Host smart-3b7fe34c-08cc-4b03-a1a9-ed8ed16f7e33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383357769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1383357769
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1168032784
Short name T67
Test name
Test status
Simulation time 48643371391 ps
CPU time 3490.82 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 03:05:20 PM PDT 24
Peak memory 305948 kb
Host smart-8e49605e-d453-44d7-a16c-61fba99e9a66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168032784 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1168032784
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2422637564
Short name T270
Test name
Test status
Simulation time 469961544421 ps
CPU time 1984.86 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:42:06 PM PDT 24
Peak memory 273568 kb
Host smart-602cc9a5-4639-444d-96f4-0e3ad3d9b245
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422637564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2422637564
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.210110405
Short name T79
Test name
Test status
Simulation time 565518655341 ps
CPU time 9256.35 seconds
Started Mar 26 02:08:19 PM PDT 24
Finished Mar 26 04:42:37 PM PDT 24
Peak memory 338588 kb
Host smart-38a7f422-9a82-4e0c-9e66-d1d7f2781229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210110405 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.210110405
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1928030469
Short name T146
Test name
Test status
Simulation time 1816124930 ps
CPU time 136.35 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:59:03 PM PDT 24
Peak memory 256896 kb
Host smart-c38a052c-ea9d-457a-81ec-527710c4ca5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1928030469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1928030469
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.237595445
Short name T279
Test name
Test status
Simulation time 13777507911 ps
CPU time 553.91 seconds
Started Mar 26 02:07:35 PM PDT 24
Finished Mar 26 02:16:49 PM PDT 24
Peak memory 248120 kb
Host smart-8c0be47b-faf8-4045-b9fc-d75e12be4d15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237595445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.237595445
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1012689284
Short name T178
Test name
Test status
Simulation time 203052647 ps
CPU time 5.87 seconds
Started Mar 26 12:57:38 PM PDT 24
Finished Mar 26 12:57:44 PM PDT 24
Peak memory 240116 kb
Host smart-cf279e2b-fef5-44aa-a4fe-4d3688fd1b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1012689284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1012689284
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2791333421
Short name T141
Test name
Test status
Simulation time 24546360526 ps
CPU time 1047.45 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 01:14:04 PM PDT 24
Peak memory 271048 kb
Host smart-3184a85c-daca-4be5-b277-7f4733e528e4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791333421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2791333421
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2707861783
Short name T325
Test name
Test status
Simulation time 102655194540 ps
CPU time 1592.39 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:35:24 PM PDT 24
Peak memory 289600 kb
Host smart-3a2b7ade-5d86-46a9-b0f3-a319106a203d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707861783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2707861783
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.226920619
Short name T47
Test name
Test status
Simulation time 187666271191 ps
CPU time 4514.06 seconds
Started Mar 26 02:09:01 PM PDT 24
Finished Mar 26 03:24:16 PM PDT 24
Peak memory 336848 kb
Host smart-40b8b000-2af7-49bd-b068-6c2397519bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226920619 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.226920619
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1450025405
Short name T25
Test name
Test status
Simulation time 185334687909 ps
CPU time 5227.04 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 03:35:21 PM PDT 24
Peak memory 354720 kb
Host smart-8ab8bc89-4080-4c53-9d21-24b83e0a454f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450025405 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1450025405
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3322812489
Short name T220
Test name
Test status
Simulation time 12524523 ps
CPU time 1.51 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:51 PM PDT 24
Peak memory 236668 kb
Host smart-9e3ab4f7-6eda-4dc3-aa8d-d4e064de27f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3322812489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3322812489
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2469301125
Short name T266
Test name
Test status
Simulation time 18788444784 ps
CPU time 362.07 seconds
Started Mar 26 02:07:38 PM PDT 24
Finished Mar 26 02:13:40 PM PDT 24
Peak memory 248016 kb
Host smart-2207926c-f830-4eaf-a4d7-bf2d1956c637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469301125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2469301125
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.914019498
Short name T96
Test name
Test status
Simulation time 296029558673 ps
CPU time 3748 seconds
Started Mar 26 02:12:18 PM PDT 24
Finished Mar 26 03:14:46 PM PDT 24
Peak memory 298132 kb
Host smart-52b74be2-87cd-4f51-9eea-39e073867acb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914019498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.914019498
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1949222622
Short name T117
Test name
Test status
Simulation time 13117817648 ps
CPU time 289.67 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 01:00:50 PM PDT 24
Peak memory 265040 kb
Host smart-cac8b9fe-6a27-4059-a348-04159d2942b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1949222622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1949222622
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3291838312
Short name T688
Test name
Test status
Simulation time 86192419683 ps
CPU time 2421.79 seconds
Started Mar 26 02:07:43 PM PDT 24
Finished Mar 26 02:48:08 PM PDT 24
Peak memory 283492 kb
Host smart-6c7f07ad-1613-4884-8066-a3b83151a5e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291838312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3291838312
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.715713252
Short name T249
Test name
Test status
Simulation time 50490931790 ps
CPU time 2729 seconds
Started Mar 26 02:07:35 PM PDT 24
Finished Mar 26 02:53:05 PM PDT 24
Peak memory 289576 kb
Host smart-2f90ba90-857f-4a54-884c-020b23c87394
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715713252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.715713252
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1395073282
Short name T243
Test name
Test status
Simulation time 112583642984 ps
CPU time 2024.16 seconds
Started Mar 26 02:07:52 PM PDT 24
Finished Mar 26 02:41:37 PM PDT 24
Peak memory 281180 kb
Host smart-1ca10863-6977-4e56-b85b-8c6e11fac741
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395073282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1395073282
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4138515531
Short name T68
Test name
Test status
Simulation time 221116324306 ps
CPU time 2326.33 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:47:27 PM PDT 24
Peak memory 286244 kb
Host smart-9cf88e55-1534-473e-a210-5df54237fd29
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138515531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4138515531
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1619818084
Short name T7
Test name
Test status
Simulation time 7772999952 ps
CPU time 165.38 seconds
Started Mar 26 02:11:13 PM PDT 24
Finished Mar 26 02:13:58 PM PDT 24
Peak memory 247080 kb
Host smart-8f7e8493-4ec7-4049-9032-8341c1a3e269
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619818084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1619818084
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1870660731
Short name T158
Test name
Test status
Simulation time 281949115 ps
CPU time 4.22 seconds
Started Mar 26 12:57:10 PM PDT 24
Finished Mar 26 12:57:15 PM PDT 24
Peak memory 236500 kb
Host smart-cee692dd-df01-43b4-8022-66ab925956e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1870660731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1870660731
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3145709443
Short name T147
Test name
Test status
Simulation time 151291353037 ps
CPU time 1072.22 seconds
Started Mar 26 12:57:38 PM PDT 24
Finished Mar 26 01:15:30 PM PDT 24
Peak memory 264996 kb
Host smart-2825d367-09fe-44d7-9010-86abaeb153c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145709443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3145709443
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1174561271
Short name T184
Test name
Test status
Simulation time 2199409236 ps
CPU time 274.76 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 01:01:42 PM PDT 24
Peak memory 265236 kb
Host smart-da21e088-04cc-4988-91a3-a3119ddfd75d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1174561271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1174561271
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1422185714
Short name T199
Test name
Test status
Simulation time 38613300 ps
CPU time 3.57 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:06:45 PM PDT 24
Peak memory 249136 kb
Host smart-11d77209-1b1c-4dc4-983a-cb35f2618bbf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1422185714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1422185714
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1010584218
Short name T196
Test name
Test status
Simulation time 135168325 ps
CPU time 3.14 seconds
Started Mar 26 02:06:55 PM PDT 24
Finished Mar 26 02:06:59 PM PDT 24
Peak memory 249008 kb
Host smart-976f82ab-7b2e-4c7a-8f07-e2c498ffb1f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1010584218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1010584218
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1787929295
Short name T190
Test name
Test status
Simulation time 539302698 ps
CPU time 3.8 seconds
Started Mar 26 02:07:35 PM PDT 24
Finished Mar 26 02:07:39 PM PDT 24
Peak memory 249128 kb
Host smart-52a8c7fd-9a87-41f1-a9de-03a93b9bc593
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1787929295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1787929295
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.673792298
Short name T202
Test name
Test status
Simulation time 19247613 ps
CPU time 2.65 seconds
Started Mar 26 02:07:49 PM PDT 24
Finished Mar 26 02:07:52 PM PDT 24
Peak memory 249096 kb
Host smart-110e2db0-bedd-461d-8a62-e62e1a6febe9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=673792298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.673792298
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2959041257
Short name T336
Test name
Test status
Simulation time 11751453 ps
CPU time 1.67 seconds
Started Mar 26 12:57:09 PM PDT 24
Finished Mar 26 12:57:11 PM PDT 24
Peak memory 235948 kb
Host smart-b2713577-26b0-44ef-be8b-b0a4922a6f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2959041257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2959041257
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2810037880
Short name T586
Test name
Test status
Simulation time 26224438308 ps
CPU time 354.41 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:13:42 PM PDT 24
Peak memory 248100 kb
Host smart-f72c473d-305f-454c-9323-3cd1f2fd0eac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810037880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2810037880
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3961471887
Short name T108
Test name
Test status
Simulation time 706751382366 ps
CPU time 9435 seconds
Started Mar 26 02:08:52 PM PDT 24
Finished Mar 26 04:46:08 PM PDT 24
Peak memory 394936 kb
Host smart-e9656823-a491-4dd4-b3ec-b5dbd2ef4625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961471887 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3961471887
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3529413409
Short name T274
Test name
Test status
Simulation time 9354720779 ps
CPU time 393.3 seconds
Started Mar 26 02:10:10 PM PDT 24
Finished Mar 26 02:16:43 PM PDT 24
Peak memory 248016 kb
Host smart-ac0e80e3-7961-42f9-bd9f-8015d9325f99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529413409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3529413409
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1030880968
Short name T242
Test name
Test status
Simulation time 69642519525 ps
CPU time 1942.22 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:39:31 PM PDT 24
Peak memory 271796 kb
Host smart-2fba5ea3-3a73-455c-824b-f1243ad0860d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030880968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1030880968
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.57514880
Short name T9
Test name
Test status
Simulation time 513039505 ps
CPU time 14.07 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:06:56 PM PDT 24
Peak memory 270628 kb
Host smart-df58b3fd-fbbe-4ba6-9eaf-68715bc790aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=57514880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.57514880
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1414897734
Short name T131
Test name
Test status
Simulation time 19829232186 ps
CPU time 144.87 seconds
Started Mar 26 12:57:41 PM PDT 24
Finished Mar 26 01:00:06 PM PDT 24
Peak memory 264976 kb
Host smart-1b12d6f3-ba45-4953-913b-4685fabf318d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1414897734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1414897734
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4158179848
Short name T171
Test name
Test status
Simulation time 3567693939 ps
CPU time 61.7 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:58:30 PM PDT 24
Peak memory 246212 kb
Host smart-cd3adc83-55b9-447c-8cf8-f671722679a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4158179848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4158179848
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.495104156
Short name T118
Test name
Test status
Simulation time 3598595752 ps
CPU time 203.73 seconds
Started Mar 26 12:55:47 PM PDT 24
Finished Mar 26 12:59:12 PM PDT 24
Peak memory 265148 kb
Host smart-130123b9-200b-4221-b9d4-cbc64f593211
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=495104156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.495104156
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2483073361
Short name T332
Test name
Test status
Simulation time 9774328894 ps
CPU time 1055.18 seconds
Started Mar 26 02:06:46 PM PDT 24
Finished Mar 26 02:24:21 PM PDT 24
Peak memory 273564 kb
Host smart-c3d28cd2-4263-45a2-af6c-870c26397d38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483073361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2483073361
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3673754349
Short name T307
Test name
Test status
Simulation time 2409239279 ps
CPU time 54.81 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:07:35 PM PDT 24
Peak memory 256148 kb
Host smart-6ee25598-c5ce-46ba-a6b1-8c6ef95ba5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36737
54349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3673754349
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.216928179
Short name T255
Test name
Test status
Simulation time 63230828527 ps
CPU time 3802.6 seconds
Started Mar 26 02:06:45 PM PDT 24
Finished Mar 26 03:10:08 PM PDT 24
Peak memory 306388 kb
Host smart-e292ca23-de52-4ed8-a394-5551c12bc4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216928179 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.216928179
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1884085567
Short name T303
Test name
Test status
Simulation time 27097704934 ps
CPU time 1856.72 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:37:39 PM PDT 24
Peak memory 285120 kb
Host smart-431b6d41-f1ab-417b-af39-fd18458ab531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884085567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1884085567
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2676956527
Short name T298
Test name
Test status
Simulation time 53295021203 ps
CPU time 709.79 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:19:39 PM PDT 24
Peak memory 268708 kb
Host smart-171ec08a-764e-4950-9bdd-a13934201b86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676956527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2676956527
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3698300355
Short name T100
Test name
Test status
Simulation time 9134107767 ps
CPU time 85.79 seconds
Started Mar 26 02:08:02 PM PDT 24
Finished Mar 26 02:09:29 PM PDT 24
Peak memory 248176 kb
Host smart-e689fdd3-5d23-4cc0-a262-297adeee0294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698300355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3698300355
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.370311935
Short name T244
Test name
Test status
Simulation time 3261338703 ps
CPU time 54.33 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:08:58 PM PDT 24
Peak memory 249068 kb
Host smart-d3f76d7d-4f6c-45cb-9e2d-d504605e5d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
1935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.370311935
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.313675343
Short name T286
Test name
Test status
Simulation time 1775118994 ps
CPU time 80.19 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:09:35 PM PDT 24
Peak memory 247776 kb
Host smart-0f3bb94e-987a-40b6-a97b-aa6fb4dac015
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313675343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.313675343
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3820391915
Short name T246
Test name
Test status
Simulation time 181409747202 ps
CPU time 4537.5 seconds
Started Mar 26 02:08:19 PM PDT 24
Finished Mar 26 03:23:57 PM PDT 24
Peak memory 322792 kb
Host smart-02d338a9-20aa-41ef-b4f1-2b28bef00e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820391915 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3820391915
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.269129678
Short name T214
Test name
Test status
Simulation time 30277125344 ps
CPU time 1289.2 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:29:59 PM PDT 24
Peak memory 281728 kb
Host smart-1d908946-7b19-405c-a115-d57c2b806975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269129678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.269129678
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1731076351
Short name T257
Test name
Test status
Simulation time 64547714854 ps
CPU time 5438.12 seconds
Started Mar 26 02:09:17 PM PDT 24
Finished Mar 26 03:39:57 PM PDT 24
Peak memory 306244 kb
Host smart-3e52157d-9777-4264-8d55-d509a1864c47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731076351 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1731076351
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2619369981
Short name T69
Test name
Test status
Simulation time 29153148129 ps
CPU time 116.12 seconds
Started Mar 26 02:09:28 PM PDT 24
Finished Mar 26 02:11:24 PM PDT 24
Peak memory 256664 kb
Host smart-3c837e03-64f4-4e08-b02e-abe0084eb6a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619369981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2619369981
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2407764791
Short name T53
Test name
Test status
Simulation time 5014309793 ps
CPU time 157.86 seconds
Started Mar 26 02:07:00 PM PDT 24
Finished Mar 26 02:09:38 PM PDT 24
Peak memory 256204 kb
Host smart-57538bca-7e45-4435-a2d1-7993adb67f24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407764791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2407764791
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.531733196
Short name T71
Test name
Test status
Simulation time 25640966903 ps
CPU time 1714.67 seconds
Started Mar 26 02:10:50 PM PDT 24
Finished Mar 26 02:39:25 PM PDT 24
Peak memory 285220 kb
Host smart-5eb02531-84d1-414f-974c-bd3396e667ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531733196 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.531733196
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.208917720
Short name T30
Test name
Test status
Simulation time 37798656170 ps
CPU time 861.75 seconds
Started Mar 26 02:10:50 PM PDT 24
Finished Mar 26 02:25:12 PM PDT 24
Peak memory 273532 kb
Host smart-3db7d9e6-61f0-4d62-8749-f15fb895d287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208917720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.208917720
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3057453441
Short name T312
Test name
Test status
Simulation time 2914161143 ps
CPU time 42.77 seconds
Started Mar 26 02:11:19 PM PDT 24
Finished Mar 26 02:12:02 PM PDT 24
Peak memory 248956 kb
Host smart-1bb6bc0c-9883-4f6f-8df2-3d04cc87339b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30574
53441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3057453441
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1964951694
Short name T65
Test name
Test status
Simulation time 235113741 ps
CPU time 15.38 seconds
Started Mar 26 02:11:29 PM PDT 24
Finished Mar 26 02:11:45 PM PDT 24
Peak memory 247412 kb
Host smart-b919e76d-e0e7-47cb-8ced-e4685e5cca5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
51694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1964951694
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.297401723
Short name T49
Test name
Test status
Simulation time 32334651686 ps
CPU time 2190.41 seconds
Started Mar 26 02:12:24 PM PDT 24
Finished Mar 26 02:48:55 PM PDT 24
Peak memory 289228 kb
Host smart-a7fea7e7-ae83-49c9-b4a9-a463631c8a0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297401723 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.297401723
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3708958673
Short name T251
Test name
Test status
Simulation time 14800226718 ps
CPU time 1459.95 seconds
Started Mar 26 02:07:12 PM PDT 24
Finished Mar 26 02:31:32 PM PDT 24
Peak memory 289964 kb
Host smart-a27da5f8-e69f-48a1-a7d0-fcb4691f3a17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708958673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3708958673
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2437995179
Short name T160
Test name
Test status
Simulation time 208977036 ps
CPU time 3.93 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:56:50 PM PDT 24
Peak memory 236624 kb
Host smart-888a5651-d1a6-429f-a5d1-a0e81e49948e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2437995179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2437995179
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.202297874
Short name T163
Test name
Test status
Simulation time 56255518 ps
CPU time 4.62 seconds
Started Mar 26 12:57:37 PM PDT 24
Finished Mar 26 12:57:42 PM PDT 24
Peak memory 236548 kb
Host smart-9bb0e441-c111-45e8-8722-b361cf5bd10c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=202297874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.202297874
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2378320970
Short name T157
Test name
Test status
Simulation time 269214617 ps
CPU time 4.97 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 12:56:42 PM PDT 24
Peak memory 235732 kb
Host smart-f3c9d98d-a764-4249-bf50-914fd1d6c3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2378320970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2378320970
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2051711305
Short name T159
Test name
Test status
Simulation time 464607927 ps
CPU time 32.94 seconds
Started Mar 26 12:55:47 PM PDT 24
Finished Mar 26 12:56:22 PM PDT 24
Peak memory 239316 kb
Host smart-223874fb-fdd8-47bc-98f5-05382f7c3cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2051711305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2051711305
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1940744356
Short name T126
Test name
Test status
Simulation time 5946151375 ps
CPU time 387.5 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 01:02:27 PM PDT 24
Peak memory 265132 kb
Host smart-aada04c7-e8e0-45c8-98a9-bdb0f14b10f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1940744356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1940744356
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3189995974
Short name T167
Test name
Test status
Simulation time 412729746 ps
CPU time 2.16 seconds
Started Mar 26 12:55:57 PM PDT 24
Finished Mar 26 12:55:59 PM PDT 24
Peak memory 235552 kb
Host smart-90896fc4-48c4-4a7a-bbd5-f195f1faada2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3189995974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3189995974
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1847393119
Short name T123
Test name
Test status
Simulation time 2783391352 ps
CPU time 192.08 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 01:00:40 PM PDT 24
Peak memory 265048 kb
Host smart-2bc51498-26d5-40a0-b078-9eeb4da9d918
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1847393119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1847393119
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1577670269
Short name T170
Test name
Test status
Simulation time 1147269111 ps
CPU time 73.27 seconds
Started Mar 26 12:57:30 PM PDT 24
Finished Mar 26 12:58:45 PM PDT 24
Peak memory 240228 kb
Host smart-0923d534-0e07-4d42-addf-4a42cfd3e043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1577670269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1577670269
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3126351549
Short name T150
Test name
Test status
Simulation time 160489011 ps
CPU time 5.01 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:54 PM PDT 24
Peak memory 236528 kb
Host smart-22d0372d-3afe-4ef3-bdbc-8806438c507d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3126351549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3126351549
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4170169839
Short name T142
Test name
Test status
Simulation time 16881305635 ps
CPU time 716.42 seconds
Started Mar 26 12:56:47 PM PDT 24
Finished Mar 26 01:08:44 PM PDT 24
Peak memory 265268 kb
Host smart-4b846df4-af0c-40ec-a61c-c9863c53c729
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170169839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4170169839
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2062704746
Short name T164
Test name
Test status
Simulation time 179269730 ps
CPU time 2.73 seconds
Started Mar 26 12:57:10 PM PDT 24
Finished Mar 26 12:57:13 PM PDT 24
Peak memory 236776 kb
Host smart-7e713e7b-9a2d-493a-b984-8e35ecde35eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2062704746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2062704746
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1811400834
Short name T161
Test name
Test status
Simulation time 50985842 ps
CPU time 2.33 seconds
Started Mar 26 12:57:16 PM PDT 24
Finished Mar 26 12:57:21 PM PDT 24
Peak memory 237096 kb
Host smart-cb21e98b-fbf6-4e42-a564-25f64f39d9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1811400834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1811400834
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1379526085
Short name T162
Test name
Test status
Simulation time 1928491321 ps
CPU time 46.64 seconds
Started Mar 26 12:57:42 PM PDT 24
Finished Mar 26 12:58:29 PM PDT 24
Peak memory 248652 kb
Host smart-7d42ed51-d3f9-4375-bd85-7383900fe8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1379526085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1379526085
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3822291370
Short name T152
Test name
Test status
Simulation time 29666582 ps
CPU time 2.75 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:51 PM PDT 24
Peak memory 236600 kb
Host smart-b5185c68-a22c-4d42-8b51-21d8b2c089e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3822291370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3822291370
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2204396559
Short name T166
Test name
Test status
Simulation time 239519496 ps
CPU time 22.66 seconds
Started Mar 26 12:56:47 PM PDT 24
Finished Mar 26 12:57:10 PM PDT 24
Peak memory 240224 kb
Host smart-edde0599-9e90-43aa-80ac-5d3d3d35754e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2204396559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2204396559
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2918194997
Short name T23
Test name
Test status
Simulation time 18825864304 ps
CPU time 1145.15 seconds
Started Mar 26 02:09:38 PM PDT 24
Finished Mar 26 02:28:43 PM PDT 24
Peak memory 273524 kb
Host smart-f7fcc7c3-fe22-42e4-b12a-6179e94010fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918194997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2918194997
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3124247518
Short name T740
Test name
Test status
Simulation time 3363641113 ps
CPU time 275.33 seconds
Started Mar 26 12:55:51 PM PDT 24
Finished Mar 26 01:00:27 PM PDT 24
Peak memory 240784 kb
Host smart-dc6e95a2-8ea9-4381-b2d0-bd5054419374
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3124247518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3124247518
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3856155120
Short name T811
Test name
Test status
Simulation time 6010628530 ps
CPU time 338.49 seconds
Started Mar 26 12:55:51 PM PDT 24
Finished Mar 26 01:01:30 PM PDT 24
Peak memory 240272 kb
Host smart-967aa075-597c-4fa7-9c65-adfb41a51980
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3856155120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3856155120
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.28214437
Short name T728
Test name
Test status
Simulation time 88031879 ps
CPU time 6.79 seconds
Started Mar 26 12:55:56 PM PDT 24
Finished Mar 26 12:56:03 PM PDT 24
Peak memory 240108 kb
Host smart-8c11c9b0-01c6-49f5-b70a-39855244f94d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=28214437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.28214437
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3385821542
Short name T783
Test name
Test status
Simulation time 459946530 ps
CPU time 12.5 seconds
Started Mar 26 12:55:47 PM PDT 24
Finished Mar 26 12:56:01 PM PDT 24
Peak memory 250436 kb
Host smart-2c715ef2-9f19-40a6-a446-de6fe370df7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385821542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3385821542
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4190694371
Short name T786
Test name
Test status
Simulation time 37243695 ps
CPU time 7.24 seconds
Started Mar 26 12:55:50 PM PDT 24
Finished Mar 26 12:55:59 PM PDT 24
Peak memory 240204 kb
Host smart-4bb3f69a-9f5c-4c4e-a6ab-780d155e12fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4190694371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4190694371
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2793678271
Short name T777
Test name
Test status
Simulation time 12428458 ps
CPU time 1.41 seconds
Started Mar 26 12:55:48 PM PDT 24
Finished Mar 26 12:55:50 PM PDT 24
Peak memory 235756 kb
Host smart-8eaa6096-e24c-49f0-8adc-99740122867c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2793678271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2793678271
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.529290421
Short name T778
Test name
Test status
Simulation time 314868813 ps
CPU time 23.46 seconds
Started Mar 26 12:55:49 PM PDT 24
Finished Mar 26 12:56:13 PM PDT 24
Peak memory 244696 kb
Host smart-542dbc5d-b1f5-4c2d-b9a9-9e5787561bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=529290421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.529290421
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1102209431
Short name T148
Test name
Test status
Simulation time 34873192079 ps
CPU time 1098.64 seconds
Started Mar 26 12:55:50 PM PDT 24
Finished Mar 26 01:14:10 PM PDT 24
Peak memory 264856 kb
Host smart-bbf83606-4bce-4121-9af1-3b6d643b4e54
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102209431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1102209431
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4035096480
Short name T764
Test name
Test status
Simulation time 341896296 ps
CPU time 11.77 seconds
Started Mar 26 12:55:50 PM PDT 24
Finished Mar 26 12:56:03 PM PDT 24
Peak memory 248132 kb
Host smart-8b9e3466-3fc9-4ecd-9521-d22411e04295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4035096480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4035096480
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3430537026
Short name T179
Test name
Test status
Simulation time 551308899 ps
CPU time 73.13 seconds
Started Mar 26 12:56:02 PM PDT 24
Finished Mar 26 12:57:15 PM PDT 24
Peak memory 240064 kb
Host smart-36f2ac88-74c0-4722-849c-1bca5c33ed5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3430537026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3430537026
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3495293259
Short name T814
Test name
Test status
Simulation time 9166851013 ps
CPU time 434.08 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 01:03:14 PM PDT 24
Peak memory 235680 kb
Host smart-d040e12b-6f8a-4446-8c6c-e2a9e40d3e5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3495293259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3495293259
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3387038309
Short name T831
Test name
Test status
Simulation time 173494155 ps
CPU time 5.57 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 12:56:05 PM PDT 24
Peak memory 240252 kb
Host smart-d0f08631-d830-45bf-be6d-57666f922974
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3387038309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3387038309
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2824402506
Short name T771
Test name
Test status
Simulation time 82312854 ps
CPU time 7.51 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 12:56:07 PM PDT 24
Peak memory 238884 kb
Host smart-8e15c032-76ae-40a0-a745-6320b56ca334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824402506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2824402506
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.998636145
Short name T787
Test name
Test status
Simulation time 742445368 ps
CPU time 5.5 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 12:56:05 PM PDT 24
Peak memory 240136 kb
Host smart-a411200f-29f4-4744-a2db-124dc48e4385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=998636145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.998636145
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1624522275
Short name T739
Test name
Test status
Simulation time 8032192 ps
CPU time 1.6 seconds
Started Mar 26 12:55:59 PM PDT 24
Finished Mar 26 12:56:01 PM PDT 24
Peak memory 235712 kb
Host smart-e9906067-ffa1-40be-bf2e-6da9b8a94a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1624522275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1624522275
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.10135877
Short name T810
Test name
Test status
Simulation time 181161536 ps
CPU time 31.91 seconds
Started Mar 26 12:55:57 PM PDT 24
Finished Mar 26 12:56:30 PM PDT 24
Peak memory 245460 kb
Host smart-08d3bca5-d85f-4afb-90b6-71d89e296280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=10135877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outst
anding.10135877
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1350160785
Short name T139
Test name
Test status
Simulation time 69469012531 ps
CPU time 1291.56 seconds
Started Mar 26 12:56:00 PM PDT 24
Finished Mar 26 01:17:32 PM PDT 24
Peak memory 265204 kb
Host smart-36d84af5-0fc9-41ae-8d63-2d2a54f83ab8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350160785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1350160785
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1897911812
Short name T719
Test name
Test status
Simulation time 271953876 ps
CPU time 21.42 seconds
Started Mar 26 12:56:00 PM PDT 24
Finished Mar 26 12:56:22 PM PDT 24
Peak memory 247788 kb
Host smart-f96d6301-41d5-412d-9753-4d71e3ec740c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1897911812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1897911812
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1042859197
Short name T228
Test name
Test status
Simulation time 269127560 ps
CPU time 12.18 seconds
Started Mar 26 12:57:09 PM PDT 24
Finished Mar 26 12:57:21 PM PDT 24
Peak memory 239260 kb
Host smart-9dcff006-8ca6-4a20-bd0c-b9c58516ea9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042859197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1042859197
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1726117425
Short name T718
Test name
Test status
Simulation time 126265445 ps
CPU time 6.63 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 12:57:14 PM PDT 24
Peak memory 236520 kb
Host smart-5785a899-e03c-4e98-bad5-135770069e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1726117425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1726117425
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.329134544
Short name T773
Test name
Test status
Simulation time 8734330 ps
CPU time 1.62 seconds
Started Mar 26 12:57:09 PM PDT 24
Finished Mar 26 12:57:11 PM PDT 24
Peak memory 236500 kb
Host smart-2b44c29f-b2e7-402a-b4cb-72f02f342a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=329134544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.329134544
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1182169226
Short name T230
Test name
Test status
Simulation time 678653677 ps
CPU time 25.89 seconds
Started Mar 26 12:57:10 PM PDT 24
Finished Mar 26 12:57:36 PM PDT 24
Peak memory 244700 kb
Host smart-00532248-6e40-4f0a-a6a0-df3ec4402818
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1182169226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1182169226
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3657728859
Short name T120
Test name
Test status
Simulation time 2189599417 ps
CPU time 233.4 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 01:01:00 PM PDT 24
Peak memory 265144 kb
Host smart-3ebc0ea7-52f7-4b9a-be32-2e4da7027e9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3657728859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3657728859
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1303575809
Short name T132
Test name
Test status
Simulation time 12409058641 ps
CPU time 979.28 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 01:13:26 PM PDT 24
Peak memory 272020 kb
Host smart-82fb129e-ad6a-417e-a317-5bc4bb1bce9b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303575809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1303575809
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4014597003
Short name T724
Test name
Test status
Simulation time 311535764 ps
CPU time 14.55 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 12:57:21 PM PDT 24
Peak memory 251980 kb
Host smart-f523a9c4-aa51-4b62-88b6-7a6658fd5e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4014597003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4014597003
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3533794816
Short name T822
Test name
Test status
Simulation time 755233941 ps
CPU time 10.03 seconds
Started Mar 26 12:57:06 PM PDT 24
Finished Mar 26 12:57:16 PM PDT 24
Peak memory 250824 kb
Host smart-7a1c795b-fdcb-4307-ac4b-d3cda4c5f088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533794816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3533794816
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1305984531
Short name T776
Test name
Test status
Simulation time 65279043 ps
CPU time 5.25 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 12:57:12 PM PDT 24
Peak memory 240148 kb
Host smart-32a6a18d-9c99-4575-af46-c278c5a80622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1305984531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1305984531
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2176378993
Short name T743
Test name
Test status
Simulation time 1501153305 ps
CPU time 31.26 seconds
Started Mar 26 12:57:08 PM PDT 24
Finished Mar 26 12:57:39 PM PDT 24
Peak memory 240320 kb
Host smart-f33f2a3f-56f6-429b-9860-ea0974af1b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2176378993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2176378993
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2805296666
Short name T130
Test name
Test status
Simulation time 56543151396 ps
CPU time 1046.86 seconds
Started Mar 26 12:57:08 PM PDT 24
Finished Mar 26 01:14:35 PM PDT 24
Peak memory 265372 kb
Host smart-62517734-a1be-4f3e-84cc-fca1c725e2b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805296666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2805296666
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2544443061
Short name T816
Test name
Test status
Simulation time 299357382 ps
CPU time 17.94 seconds
Started Mar 26 12:57:05 PM PDT 24
Finished Mar 26 12:57:23 PM PDT 24
Peak memory 253624 kb
Host smart-6b6edb0b-54b8-48d0-9dee-5b6a3bbb5cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2544443061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2544443061
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.450269213
Short name T758
Test name
Test status
Simulation time 91614063 ps
CPU time 7.49 seconds
Started Mar 26 12:57:20 PM PDT 24
Finished Mar 26 12:57:27 PM PDT 24
Peak memory 239340 kb
Host smart-860a5791-c763-47ab-98ab-75446ea8eecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450269213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.450269213
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.680247237
Short name T827
Test name
Test status
Simulation time 124987475 ps
CPU time 5.18 seconds
Started Mar 26 12:57:17 PM PDT 24
Finished Mar 26 12:57:24 PM PDT 24
Peak memory 240244 kb
Host smart-cbca16b0-1ba0-48dc-a421-a3d782db8b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=680247237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.680247237
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.242125006
Short name T800
Test name
Test status
Simulation time 13927123 ps
CPU time 1.78 seconds
Started Mar 26 12:57:18 PM PDT 24
Finished Mar 26 12:57:20 PM PDT 24
Peak memory 236672 kb
Host smart-0edbf638-c685-4f4f-be5c-ca60db36fe0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=242125006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.242125006
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1960294125
Short name T793
Test name
Test status
Simulation time 165849063 ps
CPU time 20.53 seconds
Started Mar 26 12:57:17 PM PDT 24
Finished Mar 26 12:57:39 PM PDT 24
Peak memory 248376 kb
Host smart-5b8252d8-ce03-4b0f-8b5b-87a250188b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1960294125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1960294125
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2471413063
Short name T124
Test name
Test status
Simulation time 3281737754 ps
CPU time 118.24 seconds
Started Mar 26 12:57:22 PM PDT 24
Finished Mar 26 12:59:21 PM PDT 24
Peak memory 264912 kb
Host smart-9aca5534-2094-4dd7-81c2-20bacaea553d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2471413063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2471413063
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.79602093
Short name T136
Test name
Test status
Simulation time 8853159469 ps
CPU time 281.45 seconds
Started Mar 26 12:57:08 PM PDT 24
Finished Mar 26 01:01:49 PM PDT 24
Peak memory 265024 kb
Host smart-7aa717a1-9f02-4ff7-a96b-7f7e75ff43d4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79602093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.79602093
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2694766109
Short name T817
Test name
Test status
Simulation time 1766185844 ps
CPU time 19.73 seconds
Started Mar 26 12:57:16 PM PDT 24
Finished Mar 26 12:57:38 PM PDT 24
Peak memory 248480 kb
Host smart-9db5e56b-5913-49e3-97c8-e6db21ff8fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2694766109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2694766109
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.243749846
Short name T343
Test name
Test status
Simulation time 248533655 ps
CPU time 4.53 seconds
Started Mar 26 12:57:27 PM PDT 24
Finished Mar 26 12:57:32 PM PDT 24
Peak memory 239688 kb
Host smart-9b90d9c0-393f-4de2-b018-a628ea650574
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243749846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.243749846
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.4000148789
Short name T181
Test name
Test status
Simulation time 20699639 ps
CPU time 3.56 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:57:32 PM PDT 24
Peak memory 236300 kb
Host smart-dfc3b660-109f-4ff5-afca-0aa3147cead3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4000148789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4000148789
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.462473882
Short name T733
Test name
Test status
Simulation time 16532857 ps
CPU time 1.65 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:57:30 PM PDT 24
Peak memory 236560 kb
Host smart-d57ba509-54a9-4e79-8ca1-b00f7a488a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=462473882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.462473882
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2835479109
Short name T180
Test name
Test status
Simulation time 372556566 ps
CPU time 23.78 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:57:53 PM PDT 24
Peak memory 248276 kb
Host smart-74a1ff44-d378-43a6-94a7-4b097cda1f5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2835479109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2835479109
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3157602213
Short name T149
Test name
Test status
Simulation time 4449118560 ps
CPU time 767.14 seconds
Started Mar 26 12:57:16 PM PDT 24
Finished Mar 26 01:10:06 PM PDT 24
Peak memory 265056 kb
Host smart-a5550216-36ea-41e7-9f2f-bfa8006fbedf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157602213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3157602213
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.508959909
Short name T729
Test name
Test status
Simulation time 1041554546 ps
CPU time 17.41 seconds
Started Mar 26 12:57:32 PM PDT 24
Finished Mar 26 12:57:50 PM PDT 24
Peak memory 248480 kb
Host smart-870c0e23-2934-40a5-a914-34f9a19d9f7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508959909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.508959909
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4196028154
Short name T169
Test name
Test status
Simulation time 162076514 ps
CPU time 14.73 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:57:44 PM PDT 24
Peak memory 255204 kb
Host smart-6b7132fc-3b82-43e9-bc36-651d38a98b82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196028154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4196028154
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1248050114
Short name T790
Test name
Test status
Simulation time 92728392 ps
CPU time 8.1 seconds
Started Mar 26 12:57:33 PM PDT 24
Finished Mar 26 12:57:41 PM PDT 24
Peak memory 240148 kb
Host smart-dc89d439-0a98-405e-97b4-8580b39e6c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1248050114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1248050114
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2709157091
Short name T725
Test name
Test status
Simulation time 1079530336 ps
CPU time 25.3 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:57:55 PM PDT 24
Peak memory 248388 kb
Host smart-506a241a-8764-4a93-98f7-bbcf61b46d07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2709157091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2709157091
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3889928832
Short name T144
Test name
Test status
Simulation time 3438520147 ps
CPU time 109.59 seconds
Started Mar 26 12:57:33 PM PDT 24
Finished Mar 26 12:59:23 PM PDT 24
Peak memory 256848 kb
Host smart-7f024d3b-edcf-4f9e-9aec-9e70c49a816f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3889928832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3889928832
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1145883449
Short name T770
Test name
Test status
Simulation time 1261289516 ps
CPU time 12.13 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:57:41 PM PDT 24
Peak memory 253136 kb
Host smart-c20ea083-9274-4781-92c4-310e110d389f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1145883449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1145883449
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.972179093
Short name T156
Test name
Test status
Simulation time 5642039452 ps
CPU time 48.41 seconds
Started Mar 26 12:57:28 PM PDT 24
Finished Mar 26 12:58:17 PM PDT 24
Peak memory 240260 kb
Host smart-8e5a5c42-a912-4973-b092-8f3c4651098c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=972179093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.972179093
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.148671691
Short name T796
Test name
Test status
Simulation time 46819169 ps
CPU time 6.39 seconds
Started Mar 26 12:57:37 PM PDT 24
Finished Mar 26 12:57:44 PM PDT 24
Peak memory 255732 kb
Host smart-f4946e63-ec1c-4cab-a971-33f8f0aa9f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148671691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.148671691
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.303405062
Short name T340
Test name
Test status
Simulation time 9871623 ps
CPU time 1.6 seconds
Started Mar 26 12:57:36 PM PDT 24
Finished Mar 26 12:57:38 PM PDT 24
Peak memory 234812 kb
Host smart-00f4d38d-fead-4c08-b0a8-a44a213537df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=303405062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.303405062
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2584253192
Short name T759
Test name
Test status
Simulation time 103442343 ps
CPU time 13.22 seconds
Started Mar 26 12:57:41 PM PDT 24
Finished Mar 26 12:57:55 PM PDT 24
Peak memory 244120 kb
Host smart-41e7e34a-5eb4-4893-b505-2a27cac96eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2584253192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2584253192
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.311070917
Short name T129
Test name
Test status
Simulation time 16661133991 ps
CPU time 536.85 seconds
Started Mar 26 12:57:33 PM PDT 24
Finished Mar 26 01:06:30 PM PDT 24
Peak memory 268968 kb
Host smart-3a5a000f-21fd-4b21-823f-bae1eb123acb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311070917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.311070917
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2282540028
Short name T797
Test name
Test status
Simulation time 98355961 ps
CPU time 14.59 seconds
Started Mar 26 12:57:29 PM PDT 24
Finished Mar 26 12:57:44 PM PDT 24
Peak memory 248420 kb
Host smart-4649c8a6-820c-486d-a3f9-d11cb9fbebfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2282540028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2282540028
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2735133259
Short name T717
Test name
Test status
Simulation time 31911192 ps
CPU time 5.54 seconds
Started Mar 26 12:57:41 PM PDT 24
Finished Mar 26 12:57:47 PM PDT 24
Peak memory 238664 kb
Host smart-f79982c0-3c52-490e-9b34-a91f86b3b19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735133259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2735133259
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1795902908
Short name T229
Test name
Test status
Simulation time 131222940 ps
CPU time 9.41 seconds
Started Mar 26 12:57:38 PM PDT 24
Finished Mar 26 12:57:47 PM PDT 24
Peak memory 240156 kb
Host smart-f78ef38b-c98d-4a7e-9025-b7e3de466b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1795902908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1795902908
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2846025228
Short name T798
Test name
Test status
Simulation time 19838011 ps
CPU time 1.4 seconds
Started Mar 26 12:57:42 PM PDT 24
Finished Mar 26 12:57:43 PM PDT 24
Peak memory 235932 kb
Host smart-d53cc6cf-dba2-48c3-9c46-a0b29d9f736a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2846025228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2846025228
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1127631317
Short name T231
Test name
Test status
Simulation time 599141759 ps
CPU time 37.08 seconds
Started Mar 26 12:57:37 PM PDT 24
Finished Mar 26 12:58:15 PM PDT 24
Peak memory 248420 kb
Host smart-fb8fb1ea-3be9-4fd5-ba32-17bb093f99e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1127631317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1127631317
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.330342145
Short name T819
Test name
Test status
Simulation time 331515436 ps
CPU time 27.74 seconds
Started Mar 26 12:57:41 PM PDT 24
Finished Mar 26 12:58:09 PM PDT 24
Peak memory 248436 kb
Host smart-f80b6c98-faae-44c0-aca1-44e299bb62fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=330342145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.330342145
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.148559701
Short name T227
Test name
Test status
Simulation time 625971788 ps
CPU time 9.46 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:58 PM PDT 24
Peak memory 237732 kb
Host smart-f4b45d09-dc1f-45a7-aab9-bfaba0683782
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148559701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.148559701
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.996891651
Short name T168
Test name
Test status
Simulation time 282093533 ps
CPU time 6.53 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:55 PM PDT 24
Peak memory 236480 kb
Host smart-6e45f23a-c775-4bc3-9174-c7e4fcc86cd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=996891651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.996891651
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4161432319
Short name T746
Test name
Test status
Simulation time 12582937 ps
CPU time 1.66 seconds
Started Mar 26 12:57:42 PM PDT 24
Finished Mar 26 12:57:44 PM PDT 24
Peak memory 236796 kb
Host smart-840c7a92-5936-41a6-b1ff-2a50a6a8f68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4161432319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4161432319
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2803551956
Short name T780
Test name
Test status
Simulation time 350068200 ps
CPU time 23.14 seconds
Started Mar 26 12:57:48 PM PDT 24
Finished Mar 26 12:58:12 PM PDT 24
Peak memory 244748 kb
Host smart-dad090fe-8a61-4f85-bebf-8ba610ffad69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2803551956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2803551956
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1363178364
Short name T830
Test name
Test status
Simulation time 173384717 ps
CPU time 13.73 seconds
Started Mar 26 12:57:38 PM PDT 24
Finished Mar 26 12:57:52 PM PDT 24
Peak memory 248480 kb
Host smart-0657d1e6-fd88-460c-ae04-41ad96704aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1363178364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1363178364
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.241282091
Short name T825
Test name
Test status
Simulation time 3363008998 ps
CPU time 11.84 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 250936 kb
Host smart-741dd861-b103-487d-9bb4-d40b4d6de12d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241282091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.241282091
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2918012364
Short name T772
Test name
Test status
Simulation time 51239247 ps
CPU time 5.76 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:54 PM PDT 24
Peak memory 236472 kb
Host smart-1a5b3e05-8da4-4888-a75f-901f420df5d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2918012364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2918012364
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2679743220
Short name T732
Test name
Test status
Simulation time 10497449 ps
CPU time 1.29 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:51 PM PDT 24
Peak memory 236528 kb
Host smart-4fa2c883-780a-42e9-b29b-9d05ecf2fc21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2679743220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2679743220
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1014077857
Short name T794
Test name
Test status
Simulation time 503603090 ps
CPU time 33.25 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:58:22 PM PDT 24
Peak memory 244740 kb
Host smart-a51dc93e-2df4-45de-ab25-314a7154eb00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1014077857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1014077857
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4236863039
Short name T815
Test name
Test status
Simulation time 2701590906 ps
CPU time 178.95 seconds
Started Mar 26 12:57:48 PM PDT 24
Finished Mar 26 01:00:47 PM PDT 24
Peak memory 265020 kb
Host smart-12bbcbfc-00f8-482f-ba8b-6da62e30c214
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4236863039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4236863039
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1687879901
Short name T789
Test name
Test status
Simulation time 233093380 ps
CPU time 7.49 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:57 PM PDT 24
Peak memory 248476 kb
Host smart-ecc46d66-2578-41e1-83c6-89fec98a33b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1687879901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1687879901
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2116842265
Short name T791
Test name
Test status
Simulation time 517775849 ps
CPU time 11.37 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 250684 kb
Host smart-aeb0c3fa-7a2e-4d7a-81f0-1919b0170402
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116842265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2116842265
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2609275535
Short name T716
Test name
Test status
Simulation time 44277211 ps
CPU time 5.07 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 12:57:54 PM PDT 24
Peak memory 235568 kb
Host smart-d4105573-e4ae-4a1a-a6da-c08ee717cc59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2609275535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2609275535
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2682649485
Short name T755
Test name
Test status
Simulation time 21410567 ps
CPU time 1.34 seconds
Started Mar 26 12:57:48 PM PDT 24
Finished Mar 26 12:57:49 PM PDT 24
Peak memory 234676 kb
Host smart-d6218235-b163-4ae9-98d3-775cb088bd64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2682649485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2682649485
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2742874175
Short name T803
Test name
Test status
Simulation time 1614270914 ps
CPU time 43.28 seconds
Started Mar 26 12:57:51 PM PDT 24
Finished Mar 26 12:58:34 PM PDT 24
Peak memory 243828 kb
Host smart-bc6e942a-33f8-4e87-9265-7db0cc61077b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2742874175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2742874175
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2622515850
Short name T133
Test name
Test status
Simulation time 12870033652 ps
CPU time 425.93 seconds
Started Mar 26 12:57:49 PM PDT 24
Finished Mar 26 01:04:56 PM PDT 24
Peak memory 269924 kb
Host smart-eca5b41f-db3b-4007-8091-740d571e2344
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622515850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2622515850
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.975900967
Short name T805
Test name
Test status
Simulation time 962406390 ps
CPU time 20.18 seconds
Started Mar 26 12:57:52 PM PDT 24
Finished Mar 26 12:58:12 PM PDT 24
Peak memory 252676 kb
Host smart-9ba40d74-184d-4f03-9efa-46f29f49f66f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=975900967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.975900967
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.377418953
Short name T807
Test name
Test status
Simulation time 18087622560 ps
CPU time 373.11 seconds
Started Mar 26 12:56:09 PM PDT 24
Finished Mar 26 01:02:22 PM PDT 24
Peak memory 240268 kb
Host smart-66d5d4ee-95aa-47ab-b184-140269b9adb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=377418953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.377418953
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3967069209
Short name T345
Test name
Test status
Simulation time 1704526735 ps
CPU time 278.15 seconds
Started Mar 26 12:56:11 PM PDT 24
Finished Mar 26 01:00:50 PM PDT 24
Peak memory 240120 kb
Host smart-7dd42128-1b8e-465d-befb-d5b29f40ef16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3967069209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3967069209
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3880300950
Short name T720
Test name
Test status
Simulation time 22945109 ps
CPU time 5.04 seconds
Started Mar 26 12:56:00 PM PDT 24
Finished Mar 26 12:56:05 PM PDT 24
Peak memory 240136 kb
Host smart-2ec04fa2-aa5e-4cd9-8dec-290a8323bbcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3880300950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3880300950
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2066748126
Short name T186
Test name
Test status
Simulation time 209403688 ps
CPU time 8.88 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:56:19 PM PDT 24
Peak memory 250820 kb
Host smart-e38fc4c5-bc08-478a-8ec3-32954f22143c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066748126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2066748126
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3288998398
Short name T781
Test name
Test status
Simulation time 34821570 ps
CPU time 6.3 seconds
Started Mar 26 12:56:12 PM PDT 24
Finished Mar 26 12:56:18 PM PDT 24
Peak memory 236716 kb
Host smart-e1010723-01c5-4e60-b468-a8ea0a045943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3288998398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3288998398
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1862371763
Short name T788
Test name
Test status
Simulation time 6124552 ps
CPU time 1.45 seconds
Started Mar 26 12:56:01 PM PDT 24
Finished Mar 26 12:56:03 PM PDT 24
Peak memory 236560 kb
Host smart-b9b3e4af-ca31-4539-8b4e-799730048ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1862371763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1862371763
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1301129947
Short name T774
Test name
Test status
Simulation time 91249955 ps
CPU time 15.13 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:56:25 PM PDT 24
Peak memory 240264 kb
Host smart-84a8fb6e-cd98-4efb-a754-7641163dbd3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1301129947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1301129947
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2485845196
Short name T112
Test name
Test status
Simulation time 46633631602 ps
CPU time 657.89 seconds
Started Mar 26 12:56:00 PM PDT 24
Finished Mar 26 01:06:58 PM PDT 24
Peak memory 265156 kb
Host smart-c583520a-94c6-4119-9b41-fe5eb525e221
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485845196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2485845196
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3872815677
Short name T714
Test name
Test status
Simulation time 155966861 ps
CPU time 10.96 seconds
Started Mar 26 12:56:02 PM PDT 24
Finished Mar 26 12:56:13 PM PDT 24
Peak memory 251524 kb
Host smart-a5925ace-65cc-4659-967b-784085991911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3872815677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3872815677
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1333067045
Short name T752
Test name
Test status
Simulation time 21210610 ps
CPU time 1.51 seconds
Started Mar 26 12:57:47 PM PDT 24
Finished Mar 26 12:57:49 PM PDT 24
Peak memory 235800 kb
Host smart-b893afc6-8e92-4c00-9529-75bdfc48e27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1333067045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1333067045
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3050505260
Short name T760
Test name
Test status
Simulation time 13211286 ps
CPU time 1.26 seconds
Started Mar 26 12:57:48 PM PDT 24
Finished Mar 26 12:57:49 PM PDT 24
Peak memory 236568 kb
Host smart-86f14adb-b95a-4681-9bef-0e023ac35f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3050505260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3050505260
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2521433089
Short name T339
Test name
Test status
Simulation time 8057225 ps
CPU time 1.44 seconds
Started Mar 26 12:57:48 PM PDT 24
Finished Mar 26 12:57:50 PM PDT 24
Peak memory 235728 kb
Host smart-e24df425-ee4d-4049-b838-3f1987df004f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2521433089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2521433089
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1410941033
Short name T221
Test name
Test status
Simulation time 15408727 ps
CPU time 1.82 seconds
Started Mar 26 12:58:00 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 235800 kb
Host smart-385a3edd-9290-4962-a5ec-e7b23d9b28e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1410941033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1410941033
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.46291030
Short name T808
Test name
Test status
Simulation time 19823937 ps
CPU time 1.45 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 234756 kb
Host smart-89c6fb94-5564-4112-881f-6824b5e5e5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=46291030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.46291030
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4040161163
Short name T765
Test name
Test status
Simulation time 7617052 ps
CPU time 1.47 seconds
Started Mar 26 12:58:03 PM PDT 24
Finished Mar 26 12:58:05 PM PDT 24
Peak memory 236612 kb
Host smart-7cd60a48-04eb-4910-a9bb-e6fc69f5283f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4040161163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4040161163
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.198709466
Short name T782
Test name
Test status
Simulation time 16035536 ps
CPU time 1.33 seconds
Started Mar 26 12:58:01 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 234800 kb
Host smart-c3e36367-8177-4762-af60-1b991ffdf75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=198709466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.198709466
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2098009087
Short name T754
Test name
Test status
Simulation time 8391856 ps
CPU time 1.52 seconds
Started Mar 26 12:58:02 PM PDT 24
Finished Mar 26 12:58:04 PM PDT 24
Peak memory 235796 kb
Host smart-df0d4718-a1d3-4a73-b31a-57a645be9b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2098009087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2098009087
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1626700760
Short name T826
Test name
Test status
Simulation time 12800767 ps
CPU time 1.5 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:00 PM PDT 24
Peak memory 235608 kb
Host smart-2d12e3a9-6c67-42f8-91c8-7a0b46d9afcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1626700760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1626700760
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2030734937
Short name T767
Test name
Test status
Simulation time 1091585466 ps
CPU time 150.23 seconds
Started Mar 26 12:56:26 PM PDT 24
Finished Mar 26 12:58:56 PM PDT 24
Peak memory 240120 kb
Host smart-5b19c515-7bd9-4502-8c59-8b6242493bec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2030734937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2030734937
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.98063265
Short name T344
Test name
Test status
Simulation time 3406876275 ps
CPU time 115.86 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:58:06 PM PDT 24
Peak memory 236532 kb
Host smart-c962f811-6a77-4b0c-b5a6-68b5fd440658
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=98063265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.98063265
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2954287417
Short name T823
Test name
Test status
Simulation time 55694792 ps
CPU time 5.63 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:56:16 PM PDT 24
Peak memory 240104 kb
Host smart-cd9d9f62-bcfa-43bc-8bbb-b361f2abaeb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2954287417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2954287417
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1241422200
Short name T756
Test name
Test status
Simulation time 112008013 ps
CPU time 5.36 seconds
Started Mar 26 12:56:26 PM PDT 24
Finished Mar 26 12:56:31 PM PDT 24
Peak memory 241272 kb
Host smart-fb457c80-70d9-47b4-a63b-f196333094a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241422200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1241422200
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1123322381
Short name T820
Test name
Test status
Simulation time 389302809 ps
CPU time 7.65 seconds
Started Mar 26 12:56:11 PM PDT 24
Finished Mar 26 12:56:18 PM PDT 24
Peak memory 240252 kb
Host smart-1a7fbd8d-940d-4c24-a90a-0bf597160397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1123322381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1123322381
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3134976863
Short name T730
Test name
Test status
Simulation time 12134096 ps
CPU time 1.5 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:56:12 PM PDT 24
Peak memory 236516 kb
Host smart-ee8938c4-1bf6-4456-9229-d2405362b010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3134976863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3134976863
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2281203098
Short name T750
Test name
Test status
Simulation time 169114978 ps
CPU time 24.55 seconds
Started Mar 26 12:56:23 PM PDT 24
Finished Mar 26 12:56:48 PM PDT 24
Peak memory 244688 kb
Host smart-7c8bb12b-9914-477b-a43f-a4a52f300e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2281203098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2281203098
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3748721823
Short name T715
Test name
Test status
Simulation time 511010402 ps
CPU time 14.42 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:56:25 PM PDT 24
Peak memory 248512 kb
Host smart-aa33bb1a-3cb7-4806-bd75-c8b7659210a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3748721823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3748721823
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1066005663
Short name T799
Test name
Test status
Simulation time 158308766 ps
CPU time 20.75 seconds
Started Mar 26 12:56:10 PM PDT 24
Finished Mar 26 12:56:31 PM PDT 24
Peak memory 248408 kb
Host smart-14ec20a5-e928-4d84-b063-60e6dbf5ef01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1066005663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1066005663
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1136401862
Short name T154
Test name
Test status
Simulation time 9658585 ps
CPU time 1.41 seconds
Started Mar 26 12:58:00 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 236560 kb
Host smart-297afdda-5b1a-47e7-bbd1-886bac2424aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1136401862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1136401862
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3334573444
Short name T338
Test name
Test status
Simulation time 13551924 ps
CPU time 1.71 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 236548 kb
Host smart-91ad2ea3-376f-4d5b-b89d-f3dd22e1d724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3334573444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3334573444
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1487751414
Short name T741
Test name
Test status
Simulation time 10402545 ps
CPU time 1.36 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 236500 kb
Host smart-3e78a976-3ef4-4abd-89bf-885c39fb4192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1487751414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1487751414
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1658208932
Short name T337
Test name
Test status
Simulation time 7324104 ps
CPU time 1.59 seconds
Started Mar 26 12:58:00 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 236664 kb
Host smart-ea9e0b27-02a5-47e1-96ff-794f4b500f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1658208932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1658208932
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2601780391
Short name T335
Test name
Test status
Simulation time 10393049 ps
CPU time 1.4 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 236660 kb
Host smart-fc5ccfe8-547f-4635-b738-b6f3177c83b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2601780391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2601780391
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2706335503
Short name T821
Test name
Test status
Simulation time 23324893 ps
CPU time 1.51 seconds
Started Mar 26 12:58:03 PM PDT 24
Finished Mar 26 12:58:05 PM PDT 24
Peak memory 236660 kb
Host smart-f4746d98-6d6e-4465-a8c9-c71865a6c19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2706335503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2706335503
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2051944817
Short name T341
Test name
Test status
Simulation time 27799844 ps
CPU time 1.56 seconds
Started Mar 26 12:58:01 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 236552 kb
Host smart-7544c57a-d3af-4b4a-a805-27de32cc4dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2051944817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2051944817
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2560705243
Short name T723
Test name
Test status
Simulation time 10737604 ps
CPU time 1.3 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 236608 kb
Host smart-977aa50b-ddc8-4a75-820e-aaa500c5f9fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2560705243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2560705243
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.456196639
Short name T727
Test name
Test status
Simulation time 23537905 ps
CPU time 1.26 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 235800 kb
Host smart-58dab4ef-4a59-4d69-8b62-33895b60c163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=456196639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.456196639
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1796706013
Short name T761
Test name
Test status
Simulation time 24408819 ps
CPU time 1.54 seconds
Started Mar 26 12:58:02 PM PDT 24
Finished Mar 26 12:58:04 PM PDT 24
Peak memory 236700 kb
Host smart-fcbc3164-7d9d-47dd-8818-0964228645bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1796706013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1796706013
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1932084526
Short name T824
Test name
Test status
Simulation time 8438611807 ps
CPU time 153.34 seconds
Started Mar 26 12:56:36 PM PDT 24
Finished Mar 26 12:59:09 PM PDT 24
Peak memory 240132 kb
Host smart-e06631e4-d268-4702-a122-3afc6958292b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1932084526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1932084526
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1828756927
Short name T792
Test name
Test status
Simulation time 5835525095 ps
CPU time 191.08 seconds
Started Mar 26 12:56:38 PM PDT 24
Finished Mar 26 12:59:49 PM PDT 24
Peak memory 236552 kb
Host smart-8271ad2c-b1b9-4f2d-a6ae-b559cdb18547
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1828756927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1828756927
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.791499392
Short name T153
Test name
Test status
Simulation time 420956139 ps
CPU time 8.31 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 12:56:46 PM PDT 24
Peak memory 240196 kb
Host smart-1a99c4ba-5a66-4390-8708-288f4004cbab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=791499392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.791499392
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2331102172
Short name T342
Test name
Test status
Simulation time 104375650 ps
CPU time 6.3 seconds
Started Mar 26 12:56:36 PM PDT 24
Finished Mar 26 12:56:42 PM PDT 24
Peak memory 242544 kb
Host smart-3db9b0ce-83c4-4f38-8361-1ab67667fc0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331102172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2331102172
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1606875923
Short name T769
Test name
Test status
Simulation time 175684487 ps
CPU time 4.54 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 12:56:42 PM PDT 24
Peak memory 236476 kb
Host smart-fe2a9870-f31f-4894-b406-dc9719389894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1606875923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1606875923
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2413733295
Short name T809
Test name
Test status
Simulation time 14338545 ps
CPU time 1.52 seconds
Started Mar 26 12:56:36 PM PDT 24
Finished Mar 26 12:56:38 PM PDT 24
Peak memory 235796 kb
Host smart-dad4455d-5415-4e5a-a254-dcedc50c8faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2413733295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2413733295
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.4178760818
Short name T735
Test name
Test status
Simulation time 366516552 ps
CPU time 30.15 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 12:57:08 PM PDT 24
Peak memory 245932 kb
Host smart-dbf08196-6adc-4baf-a7bc-a76580157496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4178760818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.4178760818
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3501371825
Short name T125
Test name
Test status
Simulation time 2637538576 ps
CPU time 243.14 seconds
Started Mar 26 12:56:27 PM PDT 24
Finished Mar 26 01:00:30 PM PDT 24
Peak memory 265012 kb
Host smart-e9949554-7514-499a-9448-9e76364b43c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3501371825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3501371825
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.358919487
Short name T140
Test name
Test status
Simulation time 19112143114 ps
CPU time 1224.58 seconds
Started Mar 26 12:56:27 PM PDT 24
Finished Mar 26 01:16:52 PM PDT 24
Peak memory 272812 kb
Host smart-6a9cfaba-0ebc-458f-ab2e-cdbb21c8dc8c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358919487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.358919487
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3524975016
Short name T726
Test name
Test status
Simulation time 39699285 ps
CPU time 4.92 seconds
Started Mar 26 12:56:36 PM PDT 24
Finished Mar 26 12:56:41 PM PDT 24
Peak memory 248492 kb
Host smart-c33f9f6f-57cf-451c-be38-d77e7b3458ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3524975016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3524975016
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2993884014
Short name T775
Test name
Test status
Simulation time 8108824 ps
CPU time 1.47 seconds
Started Mar 26 12:58:00 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 235680 kb
Host smart-2f30b03d-090e-4f2d-a72a-fd8aa29f8515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2993884014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2993884014
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2838162633
Short name T731
Test name
Test status
Simulation time 11143227 ps
CPU time 1.32 seconds
Started Mar 26 12:58:00 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 236524 kb
Host smart-f23c4a5b-5715-48fd-b4ca-46d3581a8ca3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2838162633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2838162633
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1386493641
Short name T748
Test name
Test status
Simulation time 14501646 ps
CPU time 1.5 seconds
Started Mar 26 12:57:59 PM PDT 24
Finished Mar 26 12:58:01 PM PDT 24
Peak memory 235760 kb
Host smart-bd9eb1d6-5b47-4f75-b998-86f5257bb01b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1386493641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1386493641
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2691456600
Short name T738
Test name
Test status
Simulation time 13136662 ps
CPU time 1.56 seconds
Started Mar 26 12:58:00 PM PDT 24
Finished Mar 26 12:58:02 PM PDT 24
Peak memory 235728 kb
Host smart-7edb970c-26cd-4740-bb08-c63692519022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2691456600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2691456600
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.265392678
Short name T757
Test name
Test status
Simulation time 7237808 ps
CPU time 1.4 seconds
Started Mar 26 12:58:15 PM PDT 24
Finished Mar 26 12:58:17 PM PDT 24
Peak memory 236568 kb
Host smart-c167451a-2fa1-40a1-9eb5-3c55c3c91293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=265392678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.265392678
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.23209510
Short name T155
Test name
Test status
Simulation time 8459985 ps
CPU time 1.54 seconds
Started Mar 26 12:58:12 PM PDT 24
Finished Mar 26 12:58:15 PM PDT 24
Peak memory 234708 kb
Host smart-b0f0ed72-683a-4788-aaf8-c09dd4b79976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=23209510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.23209510
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1274313483
Short name T785
Test name
Test status
Simulation time 8124849 ps
CPU time 1.37 seconds
Started Mar 26 12:58:12 PM PDT 24
Finished Mar 26 12:58:14 PM PDT 24
Peak memory 236552 kb
Host smart-248090b8-c871-4a70-ba54-d9de9e16814f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1274313483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1274313483
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3031139045
Short name T722
Test name
Test status
Simulation time 9862794 ps
CPU time 1.51 seconds
Started Mar 26 12:58:13 PM PDT 24
Finished Mar 26 12:58:16 PM PDT 24
Peak memory 235652 kb
Host smart-b1663d57-1863-46af-9013-1a4acacc6ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3031139045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3031139045
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3677958290
Short name T751
Test name
Test status
Simulation time 8386050 ps
CPU time 1.42 seconds
Started Mar 26 12:58:11 PM PDT 24
Finished Mar 26 12:58:13 PM PDT 24
Peak memory 235752 kb
Host smart-8fcf1511-dbf8-4ae6-b725-04a076b988ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3677958290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3677958290
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3595265119
Short name T828
Test name
Test status
Simulation time 9509222 ps
CPU time 1.36 seconds
Started Mar 26 12:58:11 PM PDT 24
Finished Mar 26 12:58:13 PM PDT 24
Peak memory 236560 kb
Host smart-a6bd891c-1c63-4590-ab12-a94e1bc41770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3595265119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3595265119
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2027610304
Short name T804
Test name
Test status
Simulation time 162060947 ps
CPU time 9.4 seconds
Started Mar 26 12:56:47 PM PDT 24
Finished Mar 26 12:56:56 PM PDT 24
Peak memory 252268 kb
Host smart-b49ad45f-4861-4208-939e-9a863a3a7946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027610304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2027610304
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1247576936
Short name T813
Test name
Test status
Simulation time 63480869 ps
CPU time 3.17 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:56:50 PM PDT 24
Peak memory 239300 kb
Host smart-b1279705-9bed-44dc-8e88-c1ab47acc4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1247576936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1247576936
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4136861467
Short name T737
Test name
Test status
Simulation time 11322043 ps
CPU time 1.36 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:56:48 PM PDT 24
Peak memory 236560 kb
Host smart-7a41712b-1ec5-48bc-a2d1-148775f812e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4136861467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4136861467
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.673201499
Short name T721
Test name
Test status
Simulation time 178495746 ps
CPU time 23.26 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:57:10 PM PDT 24
Peak memory 248472 kb
Host smart-e3442ca9-945b-4afb-ab39-c8aca0791e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=673201499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.673201499
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.123874988
Short name T119
Test name
Test status
Simulation time 1614208932 ps
CPU time 97.38 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 12:58:15 PM PDT 24
Peak memory 268488 kb
Host smart-a15c484e-b6d2-47db-b1de-252d0eb84a3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=123874988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.123874988
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.992096834
Short name T233
Test name
Test status
Simulation time 1478308453 ps
CPU time 29.8 seconds
Started Mar 26 12:56:37 PM PDT 24
Finished Mar 26 12:57:07 PM PDT 24
Peak memory 248252 kb
Host smart-bb08a9d4-85aa-425e-a710-d45cff2c82f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=992096834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.992096834
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.69550550
Short name T802
Test name
Test status
Simulation time 713019228 ps
CPU time 55.86 seconds
Started Mar 26 12:56:36 PM PDT 24
Finished Mar 26 12:57:32 PM PDT 24
Peak memory 236732 kb
Host smart-74346fa6-57a8-4bf6-897d-b1e815b02a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=69550550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.69550550
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1707956809
Short name T185
Test name
Test status
Simulation time 303057796 ps
CPU time 9.2 seconds
Started Mar 26 12:56:51 PM PDT 24
Finished Mar 26 12:57:00 PM PDT 24
Peak memory 251320 kb
Host smart-3f939b9b-6459-4d8a-9af8-1132473aa40a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707956809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1707956809
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.497976202
Short name T806
Test name
Test status
Simulation time 19365416 ps
CPU time 3.14 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:56:49 PM PDT 24
Peak memory 235616 kb
Host smart-4f12124a-aa8e-4b09-8402-f1c8fea99d22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=497976202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.497976202
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2046178802
Short name T762
Test name
Test status
Simulation time 27061755 ps
CPU time 1.5 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 12:56:50 PM PDT 24
Peak memory 235692 kb
Host smart-1eb53ac7-2ea7-4c7b-ab18-c68f6c2a51f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2046178802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2046178802
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.192087380
Short name T779
Test name
Test status
Simulation time 999014650 ps
CPU time 49.04 seconds
Started Mar 26 12:56:47 PM PDT 24
Finished Mar 26 12:57:36 PM PDT 24
Peak memory 248396 kb
Host smart-80590739-0aba-4404-88cb-965d4d55ec93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=192087380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.192087380
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2411204561
Short name T135
Test name
Test status
Simulation time 2341593828 ps
CPU time 123.5 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 12:58:51 PM PDT 24
Peak memory 269072 kb
Host smart-f11462de-1f9e-428b-aaa8-10bfe438ee20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2411204561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2411204561
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1847993308
Short name T812
Test name
Test status
Simulation time 541363320 ps
CPU time 19.54 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 12:57:08 PM PDT 24
Peak memory 248680 kb
Host smart-8f6b16d5-cf41-4279-8936-9cf8fcfc25c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1847993308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1847993308
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.775188246
Short name T801
Test name
Test status
Simulation time 580979625 ps
CPU time 12.12 seconds
Started Mar 26 12:56:47 PM PDT 24
Finished Mar 26 12:56:59 PM PDT 24
Peak memory 255692 kb
Host smart-1dad086c-8edc-44ef-b081-0604cfaa57df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775188246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.775188246
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3633857525
Short name T818
Test name
Test status
Simulation time 97287176 ps
CPU time 4.79 seconds
Started Mar 26 12:56:50 PM PDT 24
Finished Mar 26 12:56:55 PM PDT 24
Peak memory 236472 kb
Host smart-b7d2001b-2058-48ad-9421-3d45341fe63e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3633857525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3633857525
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1171937497
Short name T734
Test name
Test status
Simulation time 8573649 ps
CPU time 1.5 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 12:56:49 PM PDT 24
Peak memory 236568 kb
Host smart-48b1560c-8d14-4320-af88-50c7d5bd904f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1171937497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1171937497
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2544843793
Short name T742
Test name
Test status
Simulation time 1034619056 ps
CPU time 11.33 seconds
Started Mar 26 12:56:49 PM PDT 24
Finished Mar 26 12:57:01 PM PDT 24
Peak memory 243988 kb
Host smart-38645e06-2e79-49f7-8fac-1316b32052df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2544843793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2544843793
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1503998704
Short name T113
Test name
Test status
Simulation time 2617719933 ps
CPU time 162.65 seconds
Started Mar 26 12:56:46 PM PDT 24
Finished Mar 26 12:59:28 PM PDT 24
Peak memory 256808 kb
Host smart-4c2efd92-ca02-4bc9-8579-f33d2ab285b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1503998704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1503998704
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3034617223
Short name T137
Test name
Test status
Simulation time 2335009474 ps
CPU time 333.57 seconds
Started Mar 26 12:56:49 PM PDT 24
Finished Mar 26 01:02:22 PM PDT 24
Peak memory 265144 kb
Host smart-3d1a751f-86f4-4e53-9307-b745d81f34fa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034617223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3034617223
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3032823520
Short name T736
Test name
Test status
Simulation time 1029428680 ps
CPU time 16.27 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 12:57:04 PM PDT 24
Peak memory 247808 kb
Host smart-90d4f2c0-131d-4a8a-a7a6-31e39b72f003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3032823520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3032823520
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2878971655
Short name T763
Test name
Test status
Simulation time 1088479029 ps
CPU time 8.07 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:57:05 PM PDT 24
Peak memory 251632 kb
Host smart-1da61e1d-e3ed-43af-a5b2-f60b832fd4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878971655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2878971655
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3088480579
Short name T744
Test name
Test status
Simulation time 264387153 ps
CPU time 6.67 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:57:04 PM PDT 24
Peak memory 240100 kb
Host smart-1ecc90b3-735e-46b3-aa5d-9fef94e03419
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3088480579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3088480579
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2978027468
Short name T753
Test name
Test status
Simulation time 7645897 ps
CPU time 1.51 seconds
Started Mar 26 12:57:00 PM PDT 24
Finished Mar 26 12:57:02 PM PDT 24
Peak memory 234648 kb
Host smart-3a356cd6-56fd-4c82-ac09-eb419e8d0ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2978027468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2978027468
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.201010379
Short name T784
Test name
Test status
Simulation time 353738682 ps
CPU time 12.74 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:57:10 PM PDT 24
Peak memory 244848 kb
Host smart-a4391f02-7c3b-4c85-984f-6b0e8d1d63ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=201010379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.201010379
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4261865377
Short name T143
Test name
Test status
Simulation time 8430895282 ps
CPU time 538.21 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 01:05:46 PM PDT 24
Peak memory 268872 kb
Host smart-111672c4-7ed6-4432-bdad-b5bd84432f53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261865377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4261865377
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3987259820
Short name T745
Test name
Test status
Simulation time 151435614 ps
CPU time 7 seconds
Started Mar 26 12:56:48 PM PDT 24
Finished Mar 26 12:56:55 PM PDT 24
Peak memory 247668 kb
Host smart-c9d0220a-d577-4cc9-88e7-25d8f9d9aadf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987259820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3987259820
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2761896238
Short name T829
Test name
Test status
Simulation time 188412364 ps
CPU time 24.95 seconds
Started Mar 26 12:56:47 PM PDT 24
Finished Mar 26 12:57:12 PM PDT 24
Peak memory 240204 kb
Host smart-2a9bb438-2a04-4a0a-95b2-2a408dd249f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2761896238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2761896238
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1839004483
Short name T766
Test name
Test status
Simulation time 59330941 ps
CPU time 10.32 seconds
Started Mar 26 12:57:07 PM PDT 24
Finished Mar 26 12:57:17 PM PDT 24
Peak memory 254096 kb
Host smart-9eb8c435-3254-4aa8-8fb1-b984a08d6f6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839004483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1839004483
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1570094870
Short name T747
Test name
Test status
Simulation time 103120654 ps
CPU time 8.21 seconds
Started Mar 26 12:56:59 PM PDT 24
Finished Mar 26 12:57:07 PM PDT 24
Peak memory 240116 kb
Host smart-04b7f058-458d-4069-a4ca-4f7e4f4fc0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1570094870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1570094870
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4291774342
Short name T795
Test name
Test status
Simulation time 12411599 ps
CPU time 1.27 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:56:58 PM PDT 24
Peak memory 236520 kb
Host smart-d3325715-eb3e-448f-8cd1-c98b836a8377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4291774342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4291774342
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.738508686
Short name T768
Test name
Test status
Simulation time 176278253 ps
CPU time 23.22 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:57:20 PM PDT 24
Peak memory 244748 kb
Host smart-d57678ed-32c5-43fe-afbe-9b486f581e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=738508686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.738508686
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3828587336
Short name T138
Test name
Test status
Simulation time 2442118084 ps
CPU time 178.64 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:59:56 PM PDT 24
Peak memory 265000 kb
Host smart-3aa184c0-4a27-45cd-994e-e6a7d9865b11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3828587336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3828587336
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3897741955
Short name T122
Test name
Test status
Simulation time 2441860676 ps
CPU time 334.23 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 01:02:31 PM PDT 24
Peak memory 268540 kb
Host smart-c355e2c7-e7ec-4d3e-910d-7dde126cd1e9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897741955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3897741955
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.767508142
Short name T749
Test name
Test status
Simulation time 38033727 ps
CPU time 3.91 seconds
Started Mar 26 12:56:58 PM PDT 24
Finished Mar 26 12:57:02 PM PDT 24
Peak memory 248584 kb
Host smart-4c174420-cbe4-42f8-9c06-0985adf4c28d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767508142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.767508142
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3394934515
Short name T165
Test name
Test status
Simulation time 116607885 ps
CPU time 2.69 seconds
Started Mar 26 12:56:57 PM PDT 24
Finished Mar 26 12:57:00 PM PDT 24
Peak memory 236964 kb
Host smart-3eff4175-a6ea-4580-ad9e-177d4c180d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3394934515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3394934515
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.370431465
Short name T390
Test name
Test status
Simulation time 34665791685 ps
CPU time 2201.61 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:43:24 PM PDT 24
Peak memory 289256 kb
Host smart-d9ce9fe2-c4ce-4204-83a7-850e565f258f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370431465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.370431465
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2030614473
Short name T459
Test name
Test status
Simulation time 734932831 ps
CPU time 10.95 seconds
Started Mar 26 02:06:44 PM PDT 24
Finished Mar 26 02:06:55 PM PDT 24
Peak memory 248772 kb
Host smart-c4b73e45-a653-4a82-a2b3-df190c4ea6fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2030614473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2030614473
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1491008201
Short name T455
Test name
Test status
Simulation time 10517686176 ps
CPU time 140.11 seconds
Started Mar 26 02:06:44 PM PDT 24
Finished Mar 26 02:09:06 PM PDT 24
Peak memory 256924 kb
Host smart-eacd092d-3567-49ef-bc26-e8b730bf6e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14910
08201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1491008201
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2064691883
Short name T527
Test name
Test status
Simulation time 618783841 ps
CPU time 14.31 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:06:56 PM PDT 24
Peak memory 255120 kb
Host smart-c406f62c-64bd-4110-b9dc-438e0443e819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20646
91883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2064691883
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2735366850
Short name T518
Test name
Test status
Simulation time 8208742392 ps
CPU time 767.59 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:19:29 PM PDT 24
Peak memory 272060 kb
Host smart-b0631383-4618-484c-a20e-a4cb36ff6c7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735366850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2735366850
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3217285088
Short name T283
Test name
Test status
Simulation time 9270809069 ps
CPU time 271.51 seconds
Started Mar 26 02:06:45 PM PDT 24
Finished Mar 26 02:11:17 PM PDT 24
Peak memory 248324 kb
Host smart-aed59f27-bd6e-44ad-af28-d6dfa1ebd565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217285088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3217285088
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1023670140
Short name T76
Test name
Test status
Simulation time 120692012 ps
CPU time 9.85 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:06:52 PM PDT 24
Peak memory 248840 kb
Host smart-65665b0c-1539-4fe3-878c-73388cb0cff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10236
70140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1023670140
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1941522307
Short name T583
Test name
Test status
Simulation time 1900595365 ps
CPU time 65.99 seconds
Started Mar 26 02:06:46 PM PDT 24
Finished Mar 26 02:07:52 PM PDT 24
Peak memory 256036 kb
Host smart-828dbe6a-76c9-4d17-bfaa-b9ee64115139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19415
22307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1941522307
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3560014373
Short name T474
Test name
Test status
Simulation time 910230291 ps
CPU time 14.02 seconds
Started Mar 26 02:06:44 PM PDT 24
Finished Mar 26 02:06:58 PM PDT 24
Peak memory 251868 kb
Host smart-70276061-8987-4570-b261-abd3d4562b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600
14373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3560014373
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2995007039
Short name T44
Test name
Test status
Simulation time 63054871940 ps
CPU time 1433.52 seconds
Started Mar 26 02:06:44 PM PDT 24
Finished Mar 26 02:30:38 PM PDT 24
Peak memory 289336 kb
Host smart-d6a4337b-0a24-423f-821a-f0dc2b8516d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995007039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2995007039
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3211740887
Short name T386
Test name
Test status
Simulation time 339259879 ps
CPU time 16.12 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:06:58 PM PDT 24
Peak memory 240672 kb
Host smart-70edfec9-1c99-4d91-9e20-e50852179e1d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3211740887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3211740887
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2923919052
Short name T212
Test name
Test status
Simulation time 5869134609 ps
CPU time 310.55 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:11:52 PM PDT 24
Peak memory 256712 kb
Host smart-ea4d14ca-6cff-47e9-a235-2c7cacc855ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
19052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2923919052
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2257376492
Short name T61
Test name
Test status
Simulation time 826491250 ps
CPU time 54.2 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:07:36 PM PDT 24
Peak memory 255584 kb
Host smart-ab445615-1f57-4497-b752-94576989c473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22573
76492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2257376492
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2378120838
Short name T539
Test name
Test status
Simulation time 156123136720 ps
CPU time 513.87 seconds
Started Mar 26 02:06:43 PM PDT 24
Finished Mar 26 02:15:18 PM PDT 24
Peak memory 247972 kb
Host smart-4ad52a04-6e55-487e-b401-961f946b8f49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378120838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2378120838
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2249652802
Short name T364
Test name
Test status
Simulation time 914323862 ps
CPU time 54.3 seconds
Started Mar 26 02:06:40 PM PDT 24
Finished Mar 26 02:07:35 PM PDT 24
Peak memory 256036 kb
Host smart-15896c73-5702-4b3f-8d14-088b68525ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22496
52802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2249652802
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2662483355
Short name T504
Test name
Test status
Simulation time 184304643 ps
CPU time 19.61 seconds
Started Mar 26 02:06:41 PM PDT 24
Finished Mar 26 02:07:01 PM PDT 24
Peak memory 247208 kb
Host smart-4c71ace2-d167-4584-a4fb-9b35602da1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
83355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2662483355
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.447063282
Short name T31
Test name
Test status
Simulation time 4105220760 ps
CPU time 25.35 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:25 PM PDT 24
Peak memory 278628 kb
Host smart-eb4f137e-0329-4428-a347-81f99230597b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=447063282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.447063282
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1680561500
Short name T379
Test name
Test status
Simulation time 581348750 ps
CPU time 12.47 seconds
Started Mar 26 02:06:42 PM PDT 24
Finished Mar 26 02:06:54 PM PDT 24
Peak memory 252052 kb
Host smart-1d9c6caa-e716-4548-917f-149e2decf16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
61500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1680561500
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2600586337
Short name T359
Test name
Test status
Simulation time 676780480 ps
CPU time 5.21 seconds
Started Mar 26 02:06:43 PM PDT 24
Finished Mar 26 02:06:49 PM PDT 24
Peak memory 248768 kb
Host smart-98091952-f4c0-4c9b-aa0c-8faa5cfa7fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26005
86337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2600586337
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.953506938
Short name T99
Test name
Test status
Simulation time 102863760737 ps
CPU time 1871.41 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:38:07 PM PDT 24
Peak memory 271668 kb
Host smart-7430946d-7145-46e3-87f7-b8297d98e95c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953506938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.953506938
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4144852146
Short name T601
Test name
Test status
Simulation time 52881209157 ps
CPU time 1495.83 seconds
Started Mar 26 02:07:36 PM PDT 24
Finished Mar 26 02:32:32 PM PDT 24
Peak memory 273408 kb
Host smart-9e115efe-f28a-4b88-bd51-d0ac29318eeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144852146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4144852146
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2518181424
Short name T492
Test name
Test status
Simulation time 1241272190 ps
CPU time 9.08 seconds
Started Mar 26 02:07:34 PM PDT 24
Finished Mar 26 02:07:43 PM PDT 24
Peak memory 240600 kb
Host smart-13da42b6-9e86-4c17-8f79-6bca27eb0a1a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2518181424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2518181424
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3930788605
Short name T418
Test name
Test status
Simulation time 52499331 ps
CPU time 4.46 seconds
Started Mar 26 02:07:36 PM PDT 24
Finished Mar 26 02:07:41 PM PDT 24
Peak memory 239048 kb
Host smart-d4ca3a4c-bff7-4338-b9d8-3479341a855d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39307
88605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3930788605
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4224251463
Short name T641
Test name
Test status
Simulation time 891570417 ps
CPU time 36.56 seconds
Started Mar 26 02:07:41 PM PDT 24
Finished Mar 26 02:08:19 PM PDT 24
Peak memory 255448 kb
Host smart-dd7fc22e-bcb6-4345-af0a-6f05b3a40fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42242
51463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4224251463
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1022973383
Short name T322
Test name
Test status
Simulation time 115686838107 ps
CPU time 1703.26 seconds
Started Mar 26 02:07:37 PM PDT 24
Finished Mar 26 02:36:01 PM PDT 24
Peak memory 266344 kb
Host smart-bc3f7c20-765d-4614-95dc-5772da292ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022973383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1022973383
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1406960317
Short name T530
Test name
Test status
Simulation time 25867967327 ps
CPU time 1368.62 seconds
Started Mar 26 02:07:40 PM PDT 24
Finished Mar 26 02:30:30 PM PDT 24
Peak memory 289620 kb
Host smart-c090ca49-7a62-4923-94ae-898dfe581c1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406960317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1406960317
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.4241848337
Short name T609
Test name
Test status
Simulation time 411322672 ps
CPU time 18.88 seconds
Started Mar 26 02:07:40 PM PDT 24
Finished Mar 26 02:08:00 PM PDT 24
Peak memory 255660 kb
Host smart-5b621571-f97e-43c9-9ead-7f9cbd52fb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42418
48337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.4241848337
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1051230999
Short name T72
Test name
Test status
Simulation time 1269305778 ps
CPU time 23.93 seconds
Started Mar 26 02:07:37 PM PDT 24
Finished Mar 26 02:08:01 PM PDT 24
Peak memory 255068 kb
Host smart-ed1fe6f5-b978-4f2e-b730-1ff74f8fae89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10512
30999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1051230999
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.392359338
Short name T452
Test name
Test status
Simulation time 1520676643 ps
CPU time 25.84 seconds
Started Mar 26 02:07:40 PM PDT 24
Finished Mar 26 02:08:07 PM PDT 24
Peak memory 256948 kb
Host smart-591e5d7f-1897-4f5a-8354-483e26110043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39235
9338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.392359338
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3413227472
Short name T566
Test name
Test status
Simulation time 4261538835 ps
CPU time 60.99 seconds
Started Mar 26 02:07:25 PM PDT 24
Finished Mar 26 02:08:26 PM PDT 24
Peak memory 255980 kb
Host smart-91ce29f9-e373-4980-b31b-858db2c69d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34132
27472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3413227472
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1540203042
Short name T500
Test name
Test status
Simulation time 334501927227 ps
CPU time 3003.52 seconds
Started Mar 26 02:07:43 PM PDT 24
Finished Mar 26 02:57:49 PM PDT 24
Peak memory 289808 kb
Host smart-c032f919-430f-4040-af36-8c72436864a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540203042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1540203042
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.72710842
Short name T240
Test name
Test status
Simulation time 37947765624 ps
CPU time 1882.01 seconds
Started Mar 26 02:07:34 PM PDT 24
Finished Mar 26 02:38:57 PM PDT 24
Peak memory 289204 kb
Host smart-93a07809-d9d7-4668-a111-be9112634687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72710842 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.72710842
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.398277488
Short name T191
Test name
Test status
Simulation time 27057610 ps
CPU time 2.7 seconds
Started Mar 26 02:07:35 PM PDT 24
Finished Mar 26 02:07:38 PM PDT 24
Peak memory 249080 kb
Host smart-bc2fb85c-6afb-4152-ada8-64a5f28602c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=398277488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.398277488
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2621277401
Short name T576
Test name
Test status
Simulation time 40014035502 ps
CPU time 2355.37 seconds
Started Mar 26 02:07:36 PM PDT 24
Finished Mar 26 02:46:52 PM PDT 24
Peak memory 289628 kb
Host smart-6679ea82-8092-42d5-b33c-1e960e5d264b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621277401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2621277401
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2067781139
Short name T577
Test name
Test status
Simulation time 163203360 ps
CPU time 9.85 seconds
Started Mar 26 02:07:37 PM PDT 24
Finished Mar 26 02:07:47 PM PDT 24
Peak memory 240584 kb
Host smart-4ace2107-a0d9-413b-8fb8-e9a690dc5d5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2067781139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2067781139
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1679385066
Short name T668
Test name
Test status
Simulation time 9428533150 ps
CPU time 161.27 seconds
Started Mar 26 02:07:34 PM PDT 24
Finished Mar 26 02:10:15 PM PDT 24
Peak memory 249940 kb
Host smart-99cf55ff-8ea6-4af0-bbc7-ceca0ed02fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16793
85066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1679385066
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2734561121
Short name T449
Test name
Test status
Simulation time 1137712015 ps
CPU time 22.04 seconds
Started Mar 26 02:07:44 PM PDT 24
Finished Mar 26 02:08:07 PM PDT 24
Peak memory 255280 kb
Host smart-b4f4e711-b671-4627-9e2c-12223ff3c348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27345
61121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2734561121
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2519147669
Short name T383
Test name
Test status
Simulation time 334707208224 ps
CPU time 1608.11 seconds
Started Mar 26 02:07:37 PM PDT 24
Finished Mar 26 02:34:26 PM PDT 24
Peak memory 289788 kb
Host smart-c2ab0b43-186c-4c37-8142-820eb3371198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519147669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2519147669
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.997920250
Short name T382
Test name
Test status
Simulation time 209623748 ps
CPU time 19.36 seconds
Started Mar 26 02:07:34 PM PDT 24
Finished Mar 26 02:07:54 PM PDT 24
Peak memory 255988 kb
Host smart-86f2f714-741e-4e99-9f43-6b372b9b3cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99792
0250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.997920250
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2764353217
Short name T177
Test name
Test status
Simulation time 117678847 ps
CPU time 4.89 seconds
Started Mar 26 02:07:37 PM PDT 24
Finished Mar 26 02:07:42 PM PDT 24
Peak memory 239084 kb
Host smart-dfdf4b4f-7c68-424c-9935-6995a80c9718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
53217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2764353217
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.439375753
Short name T494
Test name
Test status
Simulation time 692415262 ps
CPU time 11.39 seconds
Started Mar 26 02:07:38 PM PDT 24
Finished Mar 26 02:07:50 PM PDT 24
Peak memory 248856 kb
Host smart-cd02624c-c73e-4f60-8410-44f0dca5fd0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43937
5753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.439375753
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.792562340
Short name T462
Test name
Test status
Simulation time 2886688016 ps
CPU time 27.68 seconds
Started Mar 26 02:07:35 PM PDT 24
Finished Mar 26 02:08:03 PM PDT 24
Peak memory 248988 kb
Host smart-10d2edb1-d8da-4e89-9af1-e9dc3b7d13b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79256
2340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.792562340
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.2370552988
Short name T306
Test name
Test status
Simulation time 82154295837 ps
CPU time 8095.2 seconds
Started Mar 26 02:07:43 PM PDT 24
Finished Mar 26 04:22:42 PM PDT 24
Peak memory 339148 kb
Host smart-9f23d729-dfcb-4bb1-9aa6-74b1b6c5cb96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370552988 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.2370552988
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2481839933
Short name T621
Test name
Test status
Simulation time 108191285538 ps
CPU time 1793.89 seconds
Started Mar 26 02:07:46 PM PDT 24
Finished Mar 26 02:37:41 PM PDT 24
Peak memory 281760 kb
Host smart-2a480e3a-6093-4805-b456-0acfd5896147
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481839933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2481839933
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3487419797
Short name T555
Test name
Test status
Simulation time 3458351432 ps
CPU time 76.7 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:09:06 PM PDT 24
Peak memory 248876 kb
Host smart-732ffab4-6510-4954-b4d9-8be7d44ba613
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3487419797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3487419797
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1488386899
Short name T414
Test name
Test status
Simulation time 14376134338 ps
CPU time 219.63 seconds
Started Mar 26 02:07:38 PM PDT 24
Finished Mar 26 02:11:18 PM PDT 24
Peak memory 249916 kb
Host smart-8c741571-c8ed-4d5b-b26e-2c582059667c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14883
86899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1488386899
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2461434086
Short name T396
Test name
Test status
Simulation time 121182157 ps
CPU time 9.85 seconds
Started Mar 26 02:07:43 PM PDT 24
Finished Mar 26 02:07:56 PM PDT 24
Peak memory 251920 kb
Host smart-d622b792-7475-4ae1-aae0-dcc65e50db1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24614
34086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2461434086
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.901525022
Short name T607
Test name
Test status
Simulation time 33446511709 ps
CPU time 1312.65 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:29:41 PM PDT 24
Peak memory 289072 kb
Host smart-6add7414-b0cf-45f2-b7df-98ea003e8836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901525022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.901525022
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3332558581
Short name T693
Test name
Test status
Simulation time 54630802259 ps
CPU time 1743.9 seconds
Started Mar 26 02:07:49 PM PDT 24
Finished Mar 26 02:36:53 PM PDT 24
Peak memory 289444 kb
Host smart-919f528b-8414-4c58-88fa-d04f9be86749
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332558581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3332558581
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3728629273
Short name T550
Test name
Test status
Simulation time 189355781 ps
CPU time 21.72 seconds
Started Mar 26 02:07:34 PM PDT 24
Finished Mar 26 02:07:56 PM PDT 24
Peak memory 248868 kb
Host smart-0ef90704-5a70-4df7-9371-1b3112b589fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
29273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3728629273
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3198095721
Short name T451
Test name
Test status
Simulation time 1570599545 ps
CPU time 51.39 seconds
Started Mar 26 02:07:36 PM PDT 24
Finished Mar 26 02:08:28 PM PDT 24
Peak memory 255524 kb
Host smart-b5a9bfeb-0582-46cd-a627-2ccde869e0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
95721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3198095721
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1844416197
Short name T679
Test name
Test status
Simulation time 428214902 ps
CPU time 33.9 seconds
Started Mar 26 02:07:44 PM PDT 24
Finished Mar 26 02:08:19 PM PDT 24
Peak memory 247440 kb
Host smart-6c0eff31-f768-48d1-8272-53199013a7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444
16197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1844416197
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3432896056
Short name T401
Test name
Test status
Simulation time 587932415 ps
CPU time 38.96 seconds
Started Mar 26 02:07:37 PM PDT 24
Finished Mar 26 02:08:16 PM PDT 24
Peak memory 255764 kb
Host smart-ef13e51b-45eb-4669-b3c3-a02ae4977abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
96056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3432896056
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.982170059
Short name T54
Test name
Test status
Simulation time 56572696613 ps
CPU time 6038.19 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 03:48:28 PM PDT 24
Peak memory 355536 kb
Host smart-00f3beed-f4e6-40e9-99c7-f372e3f3086a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982170059 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.982170059
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2959499979
Short name T194
Test name
Test status
Simulation time 53107793 ps
CPU time 2.44 seconds
Started Mar 26 02:07:49 PM PDT 24
Finished Mar 26 02:07:52 PM PDT 24
Peak memory 249116 kb
Host smart-5b3f28d0-081d-4651-98f3-4e253184ddb1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2959499979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2959499979
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3690144191
Short name T308
Test name
Test status
Simulation time 50739007549 ps
CPU time 3179.09 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 03:00:47 PM PDT 24
Peak memory 288640 kb
Host smart-efa699f4-adf9-4c25-b66c-3cb13438acb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690144191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3690144191
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.757287794
Short name T223
Test name
Test status
Simulation time 194365879 ps
CPU time 10.64 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:07:58 PM PDT 24
Peak memory 248856 kb
Host smart-6b8cd045-c56f-46eb-97c7-d68eda849a9f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=757287794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.757287794
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2337381502
Short name T488
Test name
Test status
Simulation time 597668253 ps
CPU time 56.35 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:08:44 PM PDT 24
Peak memory 256600 kb
Host smart-8b5571f7-4ca4-4a3a-a3e9-a2b2e0ffe029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
81502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2337381502
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2722428783
Short name T378
Test name
Test status
Simulation time 82163060 ps
CPU time 9.55 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:07:57 PM PDT 24
Peak memory 248836 kb
Host smart-aca8a433-7f97-4772-aaa8-5859120fe2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27224
28783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2722428783
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3652531191
Short name T318
Test name
Test status
Simulation time 13694793265 ps
CPU time 991.87 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:24:20 PM PDT 24
Peak memory 273460 kb
Host smart-4d6502da-202e-4c25-bfa9-2926a0eb58bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652531191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3652531191
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.390471488
Short name T437
Test name
Test status
Simulation time 25355042721 ps
CPU time 651.88 seconds
Started Mar 26 02:07:46 PM PDT 24
Finished Mar 26 02:18:39 PM PDT 24
Peak memory 265364 kb
Host smart-fc9090f2-f6d8-4f86-a628-017f69d394ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390471488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.390471488
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3184881403
Short name T374
Test name
Test status
Simulation time 422472039 ps
CPU time 32.87 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:08:21 PM PDT 24
Peak memory 257024 kb
Host smart-523c4f37-bf41-45b6-a9da-ee87886c4a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31848
81403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3184881403
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1256523309
Short name T35
Test name
Test status
Simulation time 587407342 ps
CPU time 36.73 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:08:25 PM PDT 24
Peak memory 255444 kb
Host smart-07abdafb-8e16-437a-b7db-deb39b400e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12565
23309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1256523309
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2176933037
Short name T91
Test name
Test status
Simulation time 423613700 ps
CPU time 28.82 seconds
Started Mar 26 02:07:52 PM PDT 24
Finished Mar 26 02:08:21 PM PDT 24
Peak memory 255460 kb
Host smart-8b2cc438-4d24-43be-a42b-911d054923a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21769
33037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2176933037
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.423614747
Short name T593
Test name
Test status
Simulation time 895095723 ps
CPU time 54.3 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:08:42 PM PDT 24
Peak memory 249084 kb
Host smart-d782381e-6ee3-44e4-a798-566d960a3cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42361
4747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.423614747
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.675092306
Short name T45
Test name
Test status
Simulation time 929811172180 ps
CPU time 10602 seconds
Started Mar 26 02:07:49 PM PDT 24
Finished Mar 26 05:04:33 PM PDT 24
Peak memory 394356 kb
Host smart-73f3b49f-4664-4ab0-b690-bc1c4570feca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675092306 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.675092306
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.4274904018
Short name T204
Test name
Test status
Simulation time 33399984 ps
CPU time 3.23 seconds
Started Mar 26 02:08:05 PM PDT 24
Finished Mar 26 02:08:08 PM PDT 24
Peak memory 249092 kb
Host smart-e83235b1-3b73-4030-93bd-9fb715364c56
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4274904018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4274904018
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.506809566
Short name T709
Test name
Test status
Simulation time 3254880918 ps
CPU time 38.67 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:08:42 PM PDT 24
Peak memory 251972 kb
Host smart-bc24ba99-2f14-457a-a7dd-43ecf7fb6f99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=506809566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.506809566
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3440400611
Short name T674
Test name
Test status
Simulation time 10415618988 ps
CPU time 285.63 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:12:35 PM PDT 24
Peak memory 257172 kb
Host smart-e19d2fbb-e0e2-43b3-9be7-7349fe2fee07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34404
00611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3440400611
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3673931715
Short name T569
Test name
Test status
Simulation time 756331735 ps
CPU time 40.53 seconds
Started Mar 26 02:07:46 PM PDT 24
Finished Mar 26 02:08:27 PM PDT 24
Peak memory 255996 kb
Host smart-c3526966-4595-4804-b1c3-0b555f5c600b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36739
31715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3673931715
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.585943427
Short name T258
Test name
Test status
Simulation time 289350334991 ps
CPU time 3193.53 seconds
Started Mar 26 02:08:01 PM PDT 24
Finished Mar 26 03:01:15 PM PDT 24
Peak memory 289156 kb
Host smart-ddbdf489-94f9-4be3-a0f6-0f6501f3a857
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585943427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.585943427
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2093775405
Short name T568
Test name
Test status
Simulation time 199695835038 ps
CPU time 2590.62 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:51:14 PM PDT 24
Peak memory 289412 kb
Host smart-4a6e341e-5359-4c8f-98e9-e79089688b1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093775405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2093775405
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2780768411
Short name T699
Test name
Test status
Simulation time 11323560029 ps
CPU time 379.52 seconds
Started Mar 26 02:07:49 PM PDT 24
Finished Mar 26 02:14:09 PM PDT 24
Peak memory 247916 kb
Host smart-9000de47-3016-453a-93f3-e99585bedfd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780768411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2780768411
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2353135703
Short name T483
Test name
Test status
Simulation time 3522523393 ps
CPU time 49.66 seconds
Started Mar 26 02:07:46 PM PDT 24
Finished Mar 26 02:08:36 PM PDT 24
Peak memory 257056 kb
Host smart-09bede14-b386-4b7e-8600-8ee1b5ecfa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
35703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2353135703
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3712757273
Short name T42
Test name
Test status
Simulation time 291435820 ps
CPU time 25.45 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:08:13 PM PDT 24
Peak memory 255332 kb
Host smart-97732df3-4bf4-4fd9-8df8-d5b24b92159e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37127
57273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3712757273
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3506885974
Short name T521
Test name
Test status
Simulation time 3637016655 ps
CPU time 29.81 seconds
Started Mar 26 02:07:48 PM PDT 24
Finished Mar 26 02:08:18 PM PDT 24
Peak memory 248700 kb
Host smart-af646a00-8bad-448f-bf7e-18355f1a08e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
85974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3506885974
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3560629434
Short name T350
Test name
Test status
Simulation time 33832935 ps
CPU time 4.17 seconds
Started Mar 26 02:07:47 PM PDT 24
Finished Mar 26 02:07:52 PM PDT 24
Peak memory 240592 kb
Host smart-b766dd0f-8dc0-4aae-9d14-7f510221ad0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
29434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3560629434
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4145514425
Short name T60
Test name
Test status
Simulation time 86144199821 ps
CPU time 1069.82 seconds
Started Mar 26 02:08:01 PM PDT 24
Finished Mar 26 02:25:52 PM PDT 24
Peak memory 265460 kb
Host smart-f718e41c-1616-48f0-9e91-518ce7ff03f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145514425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4145514425
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2015632270
Short name T189
Test name
Test status
Simulation time 107256073 ps
CPU time 3.08 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:08:06 PM PDT 24
Peak memory 249072 kb
Host smart-e6bb0165-618d-4422-aecd-b8085b6d936b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2015632270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2015632270
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2833763412
Short name T400
Test name
Test status
Simulation time 26885096257 ps
CPU time 1767.07 seconds
Started Mar 26 02:08:02 PM PDT 24
Finished Mar 26 02:37:29 PM PDT 24
Peak memory 289452 kb
Host smart-2fc38185-ed16-4ddd-b680-5d9b3d4638bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833763412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2833763412
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2224057095
Short name T642
Test name
Test status
Simulation time 13151477313 ps
CPU time 250.84 seconds
Started Mar 26 02:08:05 PM PDT 24
Finished Mar 26 02:12:16 PM PDT 24
Peak memory 256728 kb
Host smart-5fbe552a-2062-4462-ab45-bee3ecbd2091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22240
57095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2224057095
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2108930087
Short name T237
Test name
Test status
Simulation time 5566842309 ps
CPU time 73.23 seconds
Started Mar 26 02:08:02 PM PDT 24
Finished Mar 26 02:09:16 PM PDT 24
Peak memory 255088 kb
Host smart-236914f6-61bb-46a6-9971-366c1bbba978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21089
30087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2108930087
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.687372503
Short name T174
Test name
Test status
Simulation time 45543394018 ps
CPU time 1067.47 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:25:50 PM PDT 24
Peak memory 272532 kb
Host smart-419541f6-83bd-4d5a-aaba-ddf4f57daea8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687372503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.687372503
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3187320971
Short name T596
Test name
Test status
Simulation time 197157792464 ps
CPU time 3326.66 seconds
Started Mar 26 02:08:05 PM PDT 24
Finished Mar 26 03:03:32 PM PDT 24
Peak memory 289376 kb
Host smart-dbafa2df-8893-4568-89ce-faeccf4dc330
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187320971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3187320971
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1008273947
Short name T689
Test name
Test status
Simulation time 384058158 ps
CPU time 14.1 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:08:18 PM PDT 24
Peak memory 248872 kb
Host smart-19d3458f-19e2-4802-8361-e9ae6aec65b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10082
73947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1008273947
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.442944299
Short name T696
Test name
Test status
Simulation time 443856914 ps
CPU time 26.58 seconds
Started Mar 26 02:08:05 PM PDT 24
Finished Mar 26 02:08:31 PM PDT 24
Peak memory 255368 kb
Host smart-a12c837d-d856-42bd-b530-d262df817d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44294
4299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.442944299
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3699314645
Short name T595
Test name
Test status
Simulation time 4205307830 ps
CPU time 67.35 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:09:10 PM PDT 24
Peak memory 248876 kb
Host smart-cc06bf9c-a1b1-4daf-acb3-8be27468979d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
14645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3699314645
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3167291315
Short name T710
Test name
Test status
Simulation time 771619459 ps
CPU time 63.17 seconds
Started Mar 26 02:08:03 PM PDT 24
Finished Mar 26 02:09:07 PM PDT 24
Peak memory 256232 kb
Host smart-b7cc8f7b-8909-4c24-98e9-43d318c38b52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167291315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3167291315
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1934206163
Short name T188
Test name
Test status
Simulation time 49015629 ps
CPU time 4.29 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:08:19 PM PDT 24
Peak memory 249028 kb
Host smart-9bead234-ff86-4020-9879-2f55e753a4ab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1934206163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1934206163
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.734341872
Short name T637
Test name
Test status
Simulation time 37811912824 ps
CPU time 996.97 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:24:51 PM PDT 24
Peak memory 269648 kb
Host smart-b4e2e2a2-3a73-4b06-b2a0-ace6aacedbf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734341872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.734341872
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1876830768
Short name T589
Test name
Test status
Simulation time 5639930173 ps
CPU time 44.12 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 02:08:58 PM PDT 24
Peak memory 248996 kb
Host smart-c43dd183-99b6-4494-abd2-cdb27d23bb1a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1876830768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1876830768
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1915206521
Short name T664
Test name
Test status
Simulation time 959659186 ps
CPU time 71.36 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 02:09:24 PM PDT 24
Peak memory 256608 kb
Host smart-07cb089f-e7b6-4f55-8a0f-0c6702b29fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19152
06521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1915206521
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.60636623
Short name T59
Test name
Test status
Simulation time 1784623235 ps
CPU time 40.22 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 02:08:54 PM PDT 24
Peak memory 255364 kb
Host smart-385d0e46-fc98-4abb-8a40-7933d558e41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60636
623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.60636623
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3953018835
Short name T324
Test name
Test status
Simulation time 28455888702 ps
CPU time 1613.84 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:35:08 PM PDT 24
Peak memory 273576 kb
Host smart-fc29204d-7a5f-46f6-a5e4-f4b6f4a5c323
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953018835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3953018835
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3188450383
Short name T460
Test name
Test status
Simulation time 41456384996 ps
CPU time 1088.73 seconds
Started Mar 26 02:08:12 PM PDT 24
Finished Mar 26 02:26:21 PM PDT 24
Peak memory 273564 kb
Host smart-d7e5da3c-9b66-4473-b940-8effe5d33644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188450383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3188450383
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.140727979
Short name T269
Test name
Test status
Simulation time 61223519633 ps
CPU time 311.02 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 02:13:25 PM PDT 24
Peak memory 248024 kb
Host smart-8b6e01b9-6945-481a-a01c-3a40d8a6b84d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140727979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.140727979
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2921154849
Short name T1
Test name
Test status
Simulation time 5840667461 ps
CPU time 49.71 seconds
Started Mar 26 02:08:15 PM PDT 24
Finished Mar 26 02:09:05 PM PDT 24
Peak memory 249012 kb
Host smart-b30c3a39-d5bf-43b1-afb5-e5ea7c1fbf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
54849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2921154849
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2682056792
Short name T426
Test name
Test status
Simulation time 495099945 ps
CPU time 10.95 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:08:25 PM PDT 24
Peak memory 254996 kb
Host smart-2d02ba8d-8619-4f67-a942-d3b83de5bf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26820
56792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2682056792
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4196132982
Short name T256
Test name
Test status
Simulation time 424744224 ps
CPU time 24.24 seconds
Started Mar 26 02:08:12 PM PDT 24
Finished Mar 26 02:08:37 PM PDT 24
Peak memory 247924 kb
Host smart-bf255403-ed5e-4869-91ba-7becb9542699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41961
32982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4196132982
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4183505849
Short name T681
Test name
Test status
Simulation time 1860203588 ps
CPU time 57.25 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:09:11 PM PDT 24
Peak memory 248808 kb
Host smart-04c5dc2e-4f8b-4702-b1b3-bb87eff6c65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41835
05849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4183505849
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3992069933
Short name T300
Test name
Test status
Simulation time 9816168335 ps
CPU time 662.31 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:19:17 PM PDT 24
Peak memory 273540 kb
Host smart-dc5aca83-1c6c-404a-86d3-a6a4fb44e08b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992069933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3992069933
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1038966912
Short name T200
Test name
Test status
Simulation time 281372990 ps
CPU time 3.92 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:08:34 PM PDT 24
Peak memory 249008 kb
Host smart-f1c0911a-971f-423c-8295-50b7051b1a77
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1038966912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1038966912
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2030938078
Short name T412
Test name
Test status
Simulation time 155292589072 ps
CPU time 2460.82 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:49:16 PM PDT 24
Peak memory 271784 kb
Host smart-48297fe5-13ef-4695-a08c-bf92e315070e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030938078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2030938078
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1609060190
Short name T393
Test name
Test status
Simulation time 159871471 ps
CPU time 9.71 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:08:40 PM PDT 24
Peak memory 240596 kb
Host smart-c13bb20c-6cef-43e4-ba10-e385e8c3f56b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1609060190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1609060190
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2965770084
Short name T433
Test name
Test status
Simulation time 4921549687 ps
CPU time 233.92 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:12:08 PM PDT 24
Peak memory 256828 kb
Host smart-b9696f44-0a3b-463b-8974-1d402ed2bd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29657
70084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2965770084
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.18807977
Short name T111
Test name
Test status
Simulation time 1793148398 ps
CPU time 52.81 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 02:09:06 PM PDT 24
Peak memory 248968 kb
Host smart-20205057-8543-40cb-ad91-713150e41930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18807
977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.18807977
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.672238435
Short name T208
Test name
Test status
Simulation time 48464567615 ps
CPU time 2174.97 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:44:45 PM PDT 24
Peak memory 289080 kb
Host smart-a57fa321-4d4c-45d3-9c1a-33d43b54c02f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672238435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.672238435
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3324936468
Short name T618
Test name
Test status
Simulation time 28154462161 ps
CPU time 1194.99 seconds
Started Mar 26 02:08:22 PM PDT 24
Finished Mar 26 02:28:18 PM PDT 24
Peak memory 288132 kb
Host smart-ce3cca70-4680-4922-bddc-c08ce19ebe9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324936468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3324936468
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3570025151
Short name T415
Test name
Test status
Simulation time 397690700 ps
CPU time 6.31 seconds
Started Mar 26 02:08:13 PM PDT 24
Finished Mar 26 02:08:20 PM PDT 24
Peak memory 248864 kb
Host smart-553d0909-1793-4158-bc7d-be6a7fe55acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35700
25151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3570025151
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2091095904
Short name T541
Test name
Test status
Simulation time 2174414604 ps
CPU time 75.94 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:09:31 PM PDT 24
Peak memory 248756 kb
Host smart-96d0f8b1-eab2-4d64-b147-65e918da51eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20910
95904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2091095904
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.898188675
Short name T253
Test name
Test status
Simulation time 320405504 ps
CPU time 30.8 seconds
Started Mar 26 02:08:14 PM PDT 24
Finished Mar 26 02:08:45 PM PDT 24
Peak memory 247588 kb
Host smart-6bb474ee-31a2-4aaf-8b09-a740705b5a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89818
8675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.898188675
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.967918039
Short name T591
Test name
Test status
Simulation time 5013824264 ps
CPU time 24.97 seconds
Started Mar 26 02:08:15 PM PDT 24
Finished Mar 26 02:08:40 PM PDT 24
Peak memory 248972 kb
Host smart-f3cdf9af-8ee2-452d-8dc0-b0a7281981cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96791
8039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.967918039
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2500386754
Short name T557
Test name
Test status
Simulation time 16400381424 ps
CPU time 1600.76 seconds
Started Mar 26 02:08:23 PM PDT 24
Finished Mar 26 02:35:04 PM PDT 24
Peak memory 289284 kb
Host smart-1363ebfb-98b7-4a58-ab3d-ea58c035e2ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500386754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2500386754
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2802522620
Short name T198
Test name
Test status
Simulation time 24505943 ps
CPU time 2.51 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:08:32 PM PDT 24
Peak memory 249008 kb
Host smart-7f6b1980-1d8c-4123-a61b-96f66ad0338f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2802522620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2802522620
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.835358481
Short name T479
Test name
Test status
Simulation time 102354499281 ps
CPU time 2039.36 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:42:29 PM PDT 24
Peak memory 272672 kb
Host smart-76072f63-7d7b-4d35-8d19-ece6a28bb393
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835358481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.835358481
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1319324890
Short name T542
Test name
Test status
Simulation time 187007769 ps
CPU time 8.41 seconds
Started Mar 26 02:08:25 PM PDT 24
Finished Mar 26 02:08:34 PM PDT 24
Peak memory 240544 kb
Host smart-3ddfb938-82f0-4e61-98a9-9afb427efbb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1319324890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1319324890
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.941738730
Short name T219
Test name
Test status
Simulation time 6934249763 ps
CPU time 130.41 seconds
Started Mar 26 02:08:19 PM PDT 24
Finished Mar 26 02:10:29 PM PDT 24
Peak memory 257112 kb
Host smart-51552262-5299-4042-a743-bd40cb3e3f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94173
8730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.941738730
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3310212130
Short name T554
Test name
Test status
Simulation time 8525423114 ps
CPU time 50.75 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:09:12 PM PDT 24
Peak memory 255660 kb
Host smart-c6155bb6-8c4b-4cb3-81dc-05737a5f3061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
12130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3310212130
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2373318686
Short name T321
Test name
Test status
Simulation time 26747253043 ps
CPU time 1482.15 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:33:03 PM PDT 24
Peak memory 287944 kb
Host smart-40dee433-2227-4b9c-bb5a-c5459be08876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373318686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2373318686
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.406781903
Short name T36
Test name
Test status
Simulation time 9779631634 ps
CPU time 1106.87 seconds
Started Mar 26 02:08:25 PM PDT 24
Finished Mar 26 02:26:52 PM PDT 24
Peak memory 286156 kb
Host smart-1af6b3a6-b96c-4263-880c-fe31a14744c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406781903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.406781903
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2248327461
Short name T407
Test name
Test status
Simulation time 85668086 ps
CPU time 4.24 seconds
Started Mar 26 02:08:24 PM PDT 24
Finished Mar 26 02:08:28 PM PDT 24
Peak memory 240676 kb
Host smart-afe2c88b-a949-4531-b717-aa6427a4610f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22483
27461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2248327461
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.287944884
Short name T509
Test name
Test status
Simulation time 2342365748 ps
CPU time 80.27 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:09:42 PM PDT 24
Peak memory 256668 kb
Host smart-ba9e21b9-615d-4505-8185-2cc76dc97212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28794
4884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.287944884
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.504952112
Short name T582
Test name
Test status
Simulation time 260064558 ps
CPU time 19.71 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:08:41 PM PDT 24
Peak memory 247380 kb
Host smart-857e52db-29cd-432e-afcd-64501a229d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50495
2112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.504952112
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.726716682
Short name T428
Test name
Test status
Simulation time 10254327072 ps
CPU time 58.92 seconds
Started Mar 26 02:08:20 PM PDT 24
Finished Mar 26 02:09:20 PM PDT 24
Peak memory 256120 kb
Host smart-99e63019-2cbb-4195-94c6-77bad2310136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72671
6682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.726716682
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1815056059
Short name T172
Test name
Test status
Simulation time 132386115 ps
CPU time 3.77 seconds
Started Mar 26 02:08:31 PM PDT 24
Finished Mar 26 02:08:35 PM PDT 24
Peak memory 249088 kb
Host smart-9dfb7660-540b-445d-8dc4-c3b3cab5ef22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1815056059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1815056059
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2592920997
Short name T517
Test name
Test status
Simulation time 41955246329 ps
CPU time 2254.42 seconds
Started Mar 26 02:08:20 PM PDT 24
Finished Mar 26 02:45:55 PM PDT 24
Peak memory 281612 kb
Host smart-0737c94a-edfc-4f3c-a52d-b74b7b499c39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592920997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2592920997
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1182127969
Short name T410
Test name
Test status
Simulation time 130311293 ps
CPU time 9.23 seconds
Started Mar 26 02:08:20 PM PDT 24
Finished Mar 26 02:08:29 PM PDT 24
Peak memory 240612 kb
Host smart-611ce88e-8bf2-4e5f-8af3-ba4b547c2da5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1182127969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1182127969
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.4239115291
Short name T377
Test name
Test status
Simulation time 1028398175 ps
CPU time 95.26 seconds
Started Mar 26 02:08:20 PM PDT 24
Finished Mar 26 02:09:56 PM PDT 24
Peak memory 256680 kb
Host smart-9918f02b-df9e-48cd-8583-02d3e51db491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
15291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4239115291
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4273424218
Short name T408
Test name
Test status
Simulation time 532050675 ps
CPU time 4.26 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:08:25 PM PDT 24
Peak memory 239112 kb
Host smart-6e26b3f2-5864-4c13-8801-4a1b49d7691d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42734
24218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4273424218
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.498668046
Short name T489
Test name
Test status
Simulation time 57249188879 ps
CPU time 1592.23 seconds
Started Mar 26 02:08:21 PM PDT 24
Finished Mar 26 02:34:54 PM PDT 24
Peak memory 273260 kb
Host smart-c8d24ada-b555-499d-a198-7aae0c43b8bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498668046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.498668046
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2138378885
Short name T291
Test name
Test status
Simulation time 9467540743 ps
CPU time 407.07 seconds
Started Mar 26 02:08:19 PM PDT 24
Finished Mar 26 02:15:07 PM PDT 24
Peak memory 248032 kb
Host smart-4b4622b8-9425-4f4f-a714-07f00498c323
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138378885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2138378885
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.827870477
Short name T499
Test name
Test status
Simulation time 841582292 ps
CPU time 40.4 seconds
Started Mar 26 02:08:23 PM PDT 24
Finished Mar 26 02:09:04 PM PDT 24
Peak memory 256704 kb
Host smart-8da32a8c-cf9a-4322-9a34-a8a39f1ca093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82787
0477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.827870477
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3691997003
Short name T506
Test name
Test status
Simulation time 319051573 ps
CPU time 39.09 seconds
Started Mar 26 02:08:18 PM PDT 24
Finished Mar 26 02:08:58 PM PDT 24
Peak memory 256260 kb
Host smart-2e38c0a1-52d7-4adc-ae3e-6710c84a2fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
97003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3691997003
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.830146360
Short name T503
Test name
Test status
Simulation time 135169949 ps
CPU time 16.44 seconds
Started Mar 26 02:08:25 PM PDT 24
Finished Mar 26 02:08:42 PM PDT 24
Peak memory 255128 kb
Host smart-5ac74c12-3dcc-4f28-a222-a7eedaa4ecf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83014
6360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.830146360
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1979540835
Short name T63
Test name
Test status
Simulation time 381813171 ps
CPU time 18.4 seconds
Started Mar 26 02:08:20 PM PDT 24
Finished Mar 26 02:08:39 PM PDT 24
Peak memory 249036 kb
Host smart-9f017552-c062-4e08-843d-0abcde16cb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19795
40835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1979540835
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.477506004
Short name T532
Test name
Test status
Simulation time 58384224300 ps
CPU time 3558.98 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 03:07:49 PM PDT 24
Peak memory 289424 kb
Host smart-18c141e9-c2bf-46df-87a2-3815bf138f33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477506004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.477506004
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1924587295
Short name T187
Test name
Test status
Simulation time 77589852 ps
CPU time 3.81 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:03 PM PDT 24
Peak memory 249104 kb
Host smart-cc531992-4276-44f5-ad1f-4e183682593e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1924587295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1924587295
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1000212880
Short name T522
Test name
Test status
Simulation time 34883978725 ps
CPU time 2258.29 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:44:35 PM PDT 24
Peak memory 289684 kb
Host smart-67ca2ef3-0cc8-4b19-8a1e-f3e2c45874cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000212880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1000212880
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2103452554
Short name T643
Test name
Test status
Simulation time 2091923500 ps
CPU time 45.18 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:07:42 PM PDT 24
Peak memory 240644 kb
Host smart-bf844b2c-3541-4077-ac55-d85a726c6bed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2103452554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2103452554
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2146027107
Short name T646
Test name
Test status
Simulation time 9804333229 ps
CPU time 99.18 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:08:39 PM PDT 24
Peak memory 257064 kb
Host smart-dc47d68c-0d00-4ba2-a0f9-daea5dd9f21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21460
27107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2146027107
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1461019137
Short name T480
Test name
Test status
Simulation time 240413657 ps
CPU time 17.8 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:07:15 PM PDT 24
Peak memory 255584 kb
Host smart-2c5206d8-c5e4-4149-a65d-09b0bd26c2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14610
19137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1461019137
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4111528012
Short name T331
Test name
Test status
Simulation time 53787570474 ps
CPU time 1784.62 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:36:42 PM PDT 24
Peak memory 270484 kb
Host smart-9f44bb1a-5dca-4663-9ea9-b14cc706b943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111528012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4111528012
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.885266962
Short name T216
Test name
Test status
Simulation time 23175062625 ps
CPU time 1415.32 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:30:32 PM PDT 24
Peak memory 265332 kb
Host smart-e1e0ab89-955d-48ba-a257-3ab2d09eb5f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885266962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.885266962
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2266578809
Short name T287
Test name
Test status
Simulation time 51630437879 ps
CPU time 312.82 seconds
Started Mar 26 02:06:58 PM PDT 24
Finished Mar 26 02:12:11 PM PDT 24
Peak memory 247924 kb
Host smart-5b3ed759-349a-471c-b65b-0f8853b17c28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266578809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2266578809
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3026512937
Short name T469
Test name
Test status
Simulation time 1869820703 ps
CPU time 30.27 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:07:26 PM PDT 24
Peak memory 248844 kb
Host smart-d761ae13-c2a5-4b75-b7d9-aab61a90aac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
12937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3026512937
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.437445288
Short name T106
Test name
Test status
Simulation time 365877024 ps
CPU time 38.81 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:39 PM PDT 24
Peak memory 247372 kb
Host smart-8e4e225a-0b7b-4ecd-8f88-6ed1e1c38338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43744
5288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.437445288
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3699905744
Short name T247
Test name
Test status
Simulation time 1821762026 ps
CPU time 60.83 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:07:57 PM PDT 24
Peak memory 255168 kb
Host smart-bd198d41-2b3f-4368-a758-1dcb0791c40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999
05744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3699905744
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3655941957
Short name T604
Test name
Test status
Simulation time 330995664 ps
CPU time 18.76 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:07:16 PM PDT 24
Peak memory 248856 kb
Host smart-a58771cf-5339-42d0-84fe-3cb598195f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36559
41957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3655941957
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2412509650
Short name T360
Test name
Test status
Simulation time 53122024459 ps
CPU time 1258.71 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:27:59 PM PDT 24
Peak memory 288680 kb
Host smart-0e51b537-56f5-42f1-8eb4-9d25fc96e066
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412509650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2412509650
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.917098146
Short name T218
Test name
Test status
Simulation time 153192516455 ps
CPU time 1630.24 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:35:40 PM PDT 24
Peak memory 269456 kb
Host smart-39f3b758-08c2-4cd1-870e-427fad5b2231
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917098146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.917098146
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3651713765
Short name T56
Test name
Test status
Simulation time 17854430191 ps
CPU time 261.79 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:12:52 PM PDT 24
Peak memory 257124 kb
Host smart-0c78fbec-72ef-4b03-adf1-3add7086308e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36517
13765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3651713765
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1283199012
Short name T654
Test name
Test status
Simulation time 1253532881 ps
CPU time 9.89 seconds
Started Mar 26 02:08:31 PM PDT 24
Finished Mar 26 02:08:41 PM PDT 24
Peak memory 254204 kb
Host smart-f5cf5ff8-ffd3-4a84-bdb9-5882a8e85722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831
99012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1283199012
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1137060030
Short name T398
Test name
Test status
Simulation time 131946607206 ps
CPU time 2961.34 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:57:51 PM PDT 24
Peak memory 281596 kb
Host smart-caa61f0c-9a39-4c8f-9208-72800ec53ae9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137060030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1137060030
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3409217925
Short name T264
Test name
Test status
Simulation time 19517592780 ps
CPU time 226.29 seconds
Started Mar 26 02:08:31 PM PDT 24
Finished Mar 26 02:12:17 PM PDT 24
Peak memory 248304 kb
Host smart-7407f4f7-b624-4804-987b-fe659f2725b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409217925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3409217925
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.494461536
Short name T435
Test name
Test status
Simulation time 371108560 ps
CPU time 6.87 seconds
Started Mar 26 02:08:31 PM PDT 24
Finished Mar 26 02:08:38 PM PDT 24
Peak memory 240844 kb
Host smart-61dfdecc-8b1d-4b22-bcbb-20103ececc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49446
1536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.494461536
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3306340909
Short name T614
Test name
Test status
Simulation time 156078491 ps
CPU time 14.36 seconds
Started Mar 26 02:08:29 PM PDT 24
Finished Mar 26 02:08:44 PM PDT 24
Peak memory 254576 kb
Host smart-b6801e0f-6fbc-48ff-a8cf-0bb0a3224d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33063
40909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3306340909
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.598702735
Short name T655
Test name
Test status
Simulation time 1210556063 ps
CPU time 42.49 seconds
Started Mar 26 02:08:32 PM PDT 24
Finished Mar 26 02:09:14 PM PDT 24
Peak memory 256068 kb
Host smart-48998b13-1b11-4812-99c6-18a63cfdb438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59870
2735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.598702735
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2340986853
Short name T347
Test name
Test status
Simulation time 49740434 ps
CPU time 3.06 seconds
Started Mar 26 02:08:30 PM PDT 24
Finished Mar 26 02:08:33 PM PDT 24
Peak memory 240592 kb
Host smart-8350f040-7c3d-4be1-9715-c4c02c221c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
86853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2340986853
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1831137813
Short name T365
Test name
Test status
Simulation time 25920341757 ps
CPU time 244.83 seconds
Started Mar 26 02:08:31 PM PDT 24
Finished Mar 26 02:12:36 PM PDT 24
Peak memory 256556 kb
Host smart-b6f77d17-a78c-45ea-9d9b-3977ee8d4a16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831137813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1831137813
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.908463668
Short name T313
Test name
Test status
Simulation time 90943057413 ps
CPU time 6931.17 seconds
Started Mar 26 02:08:32 PM PDT 24
Finished Mar 26 04:04:04 PM PDT 24
Peak memory 333520 kb
Host smart-399b11df-7ea6-41e2-b2f6-46a775c8d30e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908463668 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.908463668
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3486224165
Short name T13
Test name
Test status
Simulation time 50469146389 ps
CPU time 1516.61 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:33:57 PM PDT 24
Peak memory 267344 kb
Host smart-14c332a6-421c-4fb5-93ef-04238d088b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486224165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3486224165
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.513275518
Short name T21
Test name
Test status
Simulation time 347642209 ps
CPU time 33.85 seconds
Started Mar 26 02:08:44 PM PDT 24
Finished Mar 26 02:09:17 PM PDT 24
Peak memory 256676 kb
Host smart-fdb1f78c-6c60-4da4-8bc4-66f95a84be56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51327
5518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.513275518
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.330242556
Short name T563
Test name
Test status
Simulation time 247193593 ps
CPU time 19.25 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:09:00 PM PDT 24
Peak memory 255584 kb
Host smart-588ef086-7e9e-4e64-a8b9-af7937ec80af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33024
2556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.330242556
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2686889967
Short name T320
Test name
Test status
Simulation time 97047194518 ps
CPU time 2719.62 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:54:02 PM PDT 24
Peak memory 281696 kb
Host smart-2e68610f-0a56-4259-8517-d14712ecef87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686889967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2686889967
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3602398700
Short name T505
Test name
Test status
Simulation time 15096904148 ps
CPU time 1447.19 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:32:49 PM PDT 24
Peak memory 287288 kb
Host smart-0627f9ce-313a-44a8-8528-847820dba6c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602398700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3602398700
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1971006966
Short name T275
Test name
Test status
Simulation time 64611853245 ps
CPU time 477.95 seconds
Started Mar 26 02:08:40 PM PDT 24
Finished Mar 26 02:16:39 PM PDT 24
Peak memory 247940 kb
Host smart-17a974df-c498-4a23-84b5-ad708082fe83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971006966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1971006966
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1320007460
Short name T598
Test name
Test status
Simulation time 1340527004 ps
CPU time 35.73 seconds
Started Mar 26 02:08:39 PM PDT 24
Finished Mar 26 02:09:15 PM PDT 24
Peak memory 255892 kb
Host smart-0b5aa188-56f6-4525-aba4-aa795e506b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13200
07460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1320007460
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3598197912
Short name T652
Test name
Test status
Simulation time 1373454104 ps
CPU time 18.12 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:09:00 PM PDT 24
Peak memory 248888 kb
Host smart-df8f9911-c979-4ec3-ad15-fdc260875fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35981
97912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3598197912
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.177690935
Short name T57
Test name
Test status
Simulation time 607255796 ps
CPU time 19.64 seconds
Started Mar 26 02:08:39 PM PDT 24
Finished Mar 26 02:08:59 PM PDT 24
Peak memory 255164 kb
Host smart-b7124eb1-c498-4549-af7b-8685057fbf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
0935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.177690935
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.826568413
Short name T431
Test name
Test status
Simulation time 1865840001 ps
CPU time 34.69 seconds
Started Mar 26 02:08:32 PM PDT 24
Finished Mar 26 02:09:06 PM PDT 24
Peak memory 248916 kb
Host smart-7a67ba00-55c5-4e49-a432-bebd0b2c9fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82656
8413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.826568413
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3107346987
Short name T628
Test name
Test status
Simulation time 131806883334 ps
CPU time 1279.37 seconds
Started Mar 26 02:08:40 PM PDT 24
Finished Mar 26 02:30:00 PM PDT 24
Peak memory 284764 kb
Host smart-fe53d4c4-93e6-4b5d-a9ce-c4c136c234f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107346987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3107346987
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3810725590
Short name T173
Test name
Test status
Simulation time 122356892 ps
CPU time 15.58 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:08:57 PM PDT 24
Peak memory 255792 kb
Host smart-41abb13c-46ad-4cf5-bce9-d1a9e031537b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38107
25590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3810725590
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.636058051
Short name T507
Test name
Test status
Simulation time 569135059 ps
CPU time 40.31 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:09:22 PM PDT 24
Peak memory 248728 kb
Host smart-c72b9751-35b5-4a9d-ba7a-f85682ac4dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63605
8051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.636058051
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.808162191
Short name T211
Test name
Test status
Simulation time 49582305915 ps
CPU time 972.04 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:24:54 PM PDT 24
Peak memory 268352 kb
Host smart-5842d076-9b31-4243-9e87-ef4e7ad05b3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808162191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.808162191
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2216744433
Short name T295
Test name
Test status
Simulation time 127476302183 ps
CPU time 1726.62 seconds
Started Mar 26 02:08:43 PM PDT 24
Finished Mar 26 02:37:30 PM PDT 24
Peak memory 272776 kb
Host smart-610b5a02-189b-4f3b-ac34-2f5d74c38b81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216744433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2216744433
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1556324475
Short name T6
Test name
Test status
Simulation time 11304187475 ps
CPU time 469.72 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:16:32 PM PDT 24
Peak memory 255404 kb
Host smart-d2953558-7b65-4361-931c-2db884b04389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556324475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1556324475
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1460955196
Short name T454
Test name
Test status
Simulation time 705321493 ps
CPU time 9.21 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:08:52 PM PDT 24
Peak memory 248904 kb
Host smart-5de8ad61-83e9-47ba-85bc-d41ab55e5047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14609
55196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1460955196
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.779127308
Short name T103
Test name
Test status
Simulation time 334929254 ps
CPU time 9.67 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:08:51 PM PDT 24
Peak memory 252224 kb
Host smart-14a6d578-23c9-42fe-acbb-28063f9a2dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77912
7308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.779127308
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3929096976
Short name T445
Test name
Test status
Simulation time 128275007 ps
CPU time 15.64 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:08:57 PM PDT 24
Peak memory 255952 kb
Host smart-534e7a82-321f-4e14-ae56-e2d38f27eafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39290
96976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3929096976
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.176836499
Short name T669
Test name
Test status
Simulation time 3384482116 ps
CPU time 52.62 seconds
Started Mar 26 02:08:42 PM PDT 24
Finished Mar 26 02:09:34 PM PDT 24
Peak memory 249024 kb
Host smart-13ccb74c-c29b-4109-b795-c175abbc737d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
6499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.176836499
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.4270586957
Short name T81
Test name
Test status
Simulation time 331537438355 ps
CPU time 3036.61 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:59:18 PM PDT 24
Peak memory 289452 kb
Host smart-bbabc3ec-edb8-425c-a7c6-a2536fa25f24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270586957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.4270586957
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1034492169
Short name T78
Test name
Test status
Simulation time 21095366957 ps
CPU time 1524.82 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:34:06 PM PDT 24
Peak memory 282896 kb
Host smart-08785c6b-355e-4ab3-98cc-d1134a0620d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034492169 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1034492169
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2340954564
Short name T685
Test name
Test status
Simulation time 144740686318 ps
CPU time 2484.55 seconds
Started Mar 26 02:08:55 PM PDT 24
Finished Mar 26 02:50:20 PM PDT 24
Peak memory 289576 kb
Host smart-bdc59fb8-cb08-4b43-bb56-9bda48ed8954
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340954564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2340954564
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.765573301
Short name T430
Test name
Test status
Simulation time 15975253058 ps
CPU time 357.81 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:14:49 PM PDT 24
Peak memory 251016 kb
Host smart-c4b0ad3f-d38d-4d42-9ce2-bc8e5a1e39ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76557
3301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.765573301
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.85713739
Short name T570
Test name
Test status
Simulation time 5907284865 ps
CPU time 29.11 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:09:20 PM PDT 24
Peak memory 248728 kb
Host smart-99ee0944-c536-4780-8f2a-6bb4bd590c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85713
739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.85713739
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2962803098
Short name T419
Test name
Test status
Simulation time 26330225573 ps
CPU time 1368.15 seconds
Started Mar 26 02:08:52 PM PDT 24
Finished Mar 26 02:31:41 PM PDT 24
Peak memory 288296 kb
Host smart-445aff12-1de3-4d04-a170-4067f8c49480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962803098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2962803098
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3707066863
Short name T606
Test name
Test status
Simulation time 7556070283 ps
CPU time 333.44 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:14:25 PM PDT 24
Peak memory 248204 kb
Host smart-65ca13e6-c40a-4a28-8cbb-0b4c0c78188b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707066863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3707066863
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1073525069
Short name T620
Test name
Test status
Simulation time 810393763 ps
CPU time 33.15 seconds
Started Mar 26 02:08:52 PM PDT 24
Finished Mar 26 02:09:26 PM PDT 24
Peak memory 248840 kb
Host smart-216ef9e9-c88a-4179-81f5-5579d6dba7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10735
25069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1073525069
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3481454197
Short name T310
Test name
Test status
Simulation time 800521956 ps
CPU time 36.93 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:09:28 PM PDT 24
Peak memory 247620 kb
Host smart-d48fae2a-2815-43f5-9ba5-234c845d0914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
54197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3481454197
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2828741751
Short name T51
Test name
Test status
Simulation time 979246289 ps
CPU time 26.77 seconds
Started Mar 26 02:08:55 PM PDT 24
Finished Mar 26 02:09:22 PM PDT 24
Peak memory 249164 kb
Host smart-54356aa5-87c2-447f-a7cf-352921bc0415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28287
41751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2828741751
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1799052414
Short name T413
Test name
Test status
Simulation time 240820331 ps
CPU time 30.97 seconds
Started Mar 26 02:08:41 PM PDT 24
Finished Mar 26 02:09:12 PM PDT 24
Peak memory 256076 kb
Host smart-969ec28e-979e-4d48-83c0-731162188759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17990
52414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1799052414
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1669411699
Short name T629
Test name
Test status
Simulation time 8289797929 ps
CPU time 830.14 seconds
Started Mar 26 02:08:55 PM PDT 24
Finished Mar 26 02:22:46 PM PDT 24
Peak memory 272844 kb
Host smart-d41064a0-b3c9-421c-a467-36b44c3326a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669411699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1669411699
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.929098066
Short name T631
Test name
Test status
Simulation time 16650053610 ps
CPU time 1078.91 seconds
Started Mar 26 02:08:52 PM PDT 24
Finished Mar 26 02:26:51 PM PDT 24
Peak memory 265392 kb
Host smart-9909219e-ee3b-455e-a67a-ec4e5231a71f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929098066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.929098066
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3951691287
Short name T352
Test name
Test status
Simulation time 4362571264 ps
CPU time 93.97 seconds
Started Mar 26 02:08:52 PM PDT 24
Finished Mar 26 02:10:26 PM PDT 24
Peak memory 250108 kb
Host smart-65f0db19-7930-4088-a0ba-49bde1ed70fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39516
91287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3951691287
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3769617952
Short name T633
Test name
Test status
Simulation time 1582988238 ps
CPU time 24.57 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:09:16 PM PDT 24
Peak memory 248936 kb
Host smart-35d363fe-ad32-40e1-9edc-2dcee2956b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37696
17952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3769617952
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.399760992
Short name T319
Test name
Test status
Simulation time 157030950969 ps
CPU time 2239.94 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:46:20 PM PDT 24
Peak memory 289108 kb
Host smart-eefbeff1-b268-4601-85be-8e8b18c1b84e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399760992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.399760992
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2256983167
Short name T630
Test name
Test status
Simulation time 184653462742 ps
CPU time 2988.99 seconds
Started Mar 26 02:09:01 PM PDT 24
Finished Mar 26 02:58:50 PM PDT 24
Peak memory 289400 kb
Host smart-adebb7fc-d7c2-4acb-be45-19a770f181c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256983167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2256983167
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.982476158
Short name T476
Test name
Test status
Simulation time 1457803945 ps
CPU time 43 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:09:34 PM PDT 24
Peak memory 256048 kb
Host smart-1097d7b2-215f-42dd-9c45-4623a3c6cdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98247
6158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.982476158
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.933890882
Short name T649
Test name
Test status
Simulation time 2105342823 ps
CPU time 53.26 seconds
Started Mar 26 02:08:52 PM PDT 24
Finished Mar 26 02:09:45 PM PDT 24
Peak memory 249036 kb
Host smart-28e0f54e-0693-4f1c-8932-3689b6586c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93389
0882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.933890882
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.223931805
Short name T706
Test name
Test status
Simulation time 158125130 ps
CPU time 22.25 seconds
Started Mar 26 02:08:51 PM PDT 24
Finished Mar 26 02:09:14 PM PDT 24
Peak memory 255696 kb
Host smart-32853944-fb9e-4835-9cff-aa9bc4e98611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22393
1805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.223931805
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.676637977
Short name T588
Test name
Test status
Simulation time 1344483837 ps
CPU time 28.6 seconds
Started Mar 26 02:08:50 PM PDT 24
Finished Mar 26 02:09:19 PM PDT 24
Peak memory 255692 kb
Host smart-655e307f-3821-42ff-aa62-ba68d63404a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67663
7977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.676637977
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3846285343
Short name T52
Test name
Test status
Simulation time 43836383597 ps
CPU time 1130.06 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:27:50 PM PDT 24
Peak memory 272268 kb
Host smart-cae7a70c-b503-43f3-bb05-65a356052e01
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846285343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3846285343
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2693012189
Short name T603
Test name
Test status
Simulation time 9927060915 ps
CPU time 1114.93 seconds
Started Mar 26 02:08:59 PM PDT 24
Finished Mar 26 02:27:34 PM PDT 24
Peak memory 287868 kb
Host smart-0b6545da-1a1c-4ba7-a74c-955f51185706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693012189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2693012189
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1158482706
Short name T351
Test name
Test status
Simulation time 3042443132 ps
CPU time 79.41 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:10:20 PM PDT 24
Peak memory 256620 kb
Host smart-4ced6547-bdb5-4162-b257-cb9b7dcd66c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11584
82706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1158482706
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3302326069
Short name T665
Test name
Test status
Simulation time 1751738401 ps
CPU time 42.09 seconds
Started Mar 26 02:08:59 PM PDT 24
Finished Mar 26 02:09:41 PM PDT 24
Peak memory 255776 kb
Host smart-88036364-f134-499b-8eb3-64be50ff2808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33023
26069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3302326069
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2726862870
Short name T376
Test name
Test status
Simulation time 120529706793 ps
CPU time 1091.68 seconds
Started Mar 26 02:09:01 PM PDT 24
Finished Mar 26 02:27:13 PM PDT 24
Peak memory 283800 kb
Host smart-7f54adda-b934-443f-a1d3-490727a19990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726862870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2726862870
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3513079004
Short name T578
Test name
Test status
Simulation time 7193369957 ps
CPU time 110.77 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:11:02 PM PDT 24
Peak memory 248060 kb
Host smart-3c39447d-2ec7-4c7d-8efe-4234f50877cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513079004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3513079004
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4200324643
Short name T366
Test name
Test status
Simulation time 246359332 ps
CPU time 8.71 seconds
Started Mar 26 02:08:59 PM PDT 24
Finished Mar 26 02:09:08 PM PDT 24
Peak memory 248912 kb
Host smart-9e62b117-6d47-4665-9c34-454080cca40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42003
24643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4200324643
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2303059628
Short name T502
Test name
Test status
Simulation time 1071187805 ps
CPU time 67.14 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:10:08 PM PDT 24
Peak memory 255492 kb
Host smart-822f2f7c-d130-4e20-b0e6-690796158f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23030
59628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2303059628
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1353789025
Short name T88
Test name
Test status
Simulation time 205798028 ps
CPU time 24.71 seconds
Started Mar 26 02:09:00 PM PDT 24
Finished Mar 26 02:09:25 PM PDT 24
Peak memory 255340 kb
Host smart-727d28d8-06b3-4f80-991a-a329ddaa11e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537
89025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1353789025
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3112773872
Short name T543
Test name
Test status
Simulation time 56702231 ps
CPU time 3.36 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:09:15 PM PDT 24
Peak memory 240540 kb
Host smart-569e8aeb-ea96-41d6-8e3f-bb22ea04d3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31127
73872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3112773872
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3179304168
Short name T673
Test name
Test status
Simulation time 91185668041 ps
CPU time 1250.34 seconds
Started Mar 26 02:09:01 PM PDT 24
Finished Mar 26 02:29:52 PM PDT 24
Peak memory 273220 kb
Host smart-052490aa-7241-4143-90eb-ee3731e93e1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179304168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3179304168
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2647177549
Short name T624
Test name
Test status
Simulation time 57570194486 ps
CPU time 3453.85 seconds
Started Mar 26 02:09:10 PM PDT 24
Finished Mar 26 03:06:44 PM PDT 24
Peak memory 289336 kb
Host smart-36ffad3b-6542-462f-b6a9-09d6e581d356
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647177549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2647177549
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3942624339
Short name T457
Test name
Test status
Simulation time 2642856747 ps
CPU time 180.8 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:12:12 PM PDT 24
Peak memory 256932 kb
Host smart-83d992c3-f6da-486e-b04d-942cdcdf0a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39426
24339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3942624339
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2082411445
Short name T547
Test name
Test status
Simulation time 2882749675 ps
CPU time 35.69 seconds
Started Mar 26 02:09:09 PM PDT 24
Finished Mar 26 02:09:44 PM PDT 24
Peak memory 248932 kb
Host smart-aac8e0c9-d969-4f10-b637-9ee3e98921e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20824
11445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2082411445
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4085513938
Short name T259
Test name
Test status
Simulation time 18013693954 ps
CPU time 1537.8 seconds
Started Mar 26 02:09:09 PM PDT 24
Finished Mar 26 02:34:48 PM PDT 24
Peak memory 288880 kb
Host smart-2efd0bd2-aeee-428f-8dd4-08b99d47daec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085513938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4085513938
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1137296039
Short name T323
Test name
Test status
Simulation time 17788730455 ps
CPU time 1593.78 seconds
Started Mar 26 02:09:10 PM PDT 24
Finished Mar 26 02:35:44 PM PDT 24
Peak memory 289584 kb
Host smart-fee77bcb-161b-478f-a2b0-9b13d517e603
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137296039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1137296039
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2897310819
Short name T640
Test name
Test status
Simulation time 31757571709 ps
CPU time 344.46 seconds
Started Mar 26 02:09:10 PM PDT 24
Finished Mar 26 02:14:54 PM PDT 24
Peak memory 247872 kb
Host smart-52ac8ecc-dedb-453d-9f96-88c448d1c597
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897310819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2897310819
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2711802910
Short name T610
Test name
Test status
Simulation time 370570601 ps
CPU time 21.92 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:09:33 PM PDT 24
Peak memory 255908 kb
Host smart-e27aa727-f14e-45cc-8034-8426b265c912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27118
02910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2711802910
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.868494496
Short name T86
Test name
Test status
Simulation time 479081236 ps
CPU time 26.95 seconds
Started Mar 26 02:09:10 PM PDT 24
Finished Mar 26 02:09:37 PM PDT 24
Peak memory 254320 kb
Host smart-82200555-d8cf-4017-a1d3-8cfe0eee157f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86849
4496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.868494496
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.437502706
Short name T395
Test name
Test status
Simulation time 88553069 ps
CPU time 13.76 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:09:26 PM PDT 24
Peak memory 254560 kb
Host smart-042a2c95-f29a-42f3-a97a-1ad25361147d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43750
2706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.437502706
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.383669224
Short name T510
Test name
Test status
Simulation time 2962981297 ps
CPU time 46.48 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:09:58 PM PDT 24
Peak memory 248864 kb
Host smart-24d2b7f3-9893-415b-826f-7157527ffdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38366
9224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.383669224
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3931962988
Short name T441
Test name
Test status
Simulation time 53274194492 ps
CPU time 2997.86 seconds
Started Mar 26 02:09:09 PM PDT 24
Finished Mar 26 02:59:07 PM PDT 24
Peak memory 289292 kb
Host smart-b9c92e62-5014-4e04-9388-7561021b128f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931962988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3931962988
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3402312161
Short name T520
Test name
Test status
Simulation time 9865352561 ps
CPU time 1082.14 seconds
Started Mar 26 02:09:19 PM PDT 24
Finished Mar 26 02:27:22 PM PDT 24
Peak memory 282720 kb
Host smart-1404d75e-2017-4c4f-886b-b4ed23c3ff38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402312161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3402312161
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.245603763
Short name T508
Test name
Test status
Simulation time 5607592542 ps
CPU time 161.16 seconds
Started Mar 26 02:09:12 PM PDT 24
Finished Mar 26 02:11:53 PM PDT 24
Peak memory 250028 kb
Host smart-5b8822d5-5e4e-4b93-8ce9-02cac2b4afea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24560
3763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.245603763
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.473420967
Short name T448
Test name
Test status
Simulation time 855999851 ps
CPU time 24.48 seconds
Started Mar 26 02:09:10 PM PDT 24
Finished Mar 26 02:09:35 PM PDT 24
Peak memory 256952 kb
Host smart-8f135fd0-dced-4ab1-b5f0-2a02bf837d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47342
0967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.473420967
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2533447335
Short name T632
Test name
Test status
Simulation time 19374949653 ps
CPU time 1330.74 seconds
Started Mar 26 02:09:18 PM PDT 24
Finished Mar 26 02:31:29 PM PDT 24
Peak memory 265380 kb
Host smart-216a2ffe-6de5-4b8d-a126-f6e2f82bfb39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533447335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2533447335
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2522574972
Short name T485
Test name
Test status
Simulation time 11379789819 ps
CPU time 972.9 seconds
Started Mar 26 02:09:18 PM PDT 24
Finished Mar 26 02:25:31 PM PDT 24
Peak memory 273540 kb
Host smart-fdad2bab-29d8-4ca8-821e-6108154a6fc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522574972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2522574972
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2987388562
Short name T644
Test name
Test status
Simulation time 17911694139 ps
CPU time 79.41 seconds
Started Mar 26 02:09:24 PM PDT 24
Finished Mar 26 02:10:44 PM PDT 24
Peak memory 248148 kb
Host smart-578a7776-e22b-4f18-aa69-9caecbc29dc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987388562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2987388562
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1828979411
Short name T432
Test name
Test status
Simulation time 1346486422 ps
CPU time 18.99 seconds
Started Mar 26 02:09:10 PM PDT 24
Finished Mar 26 02:09:29 PM PDT 24
Peak memory 256060 kb
Host smart-c4983510-2bb1-4f04-b15b-cf9a23da0004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
79411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1828979411
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2221615087
Short name T363
Test name
Test status
Simulation time 103587202 ps
CPU time 11.3 seconds
Started Mar 26 02:09:09 PM PDT 24
Finished Mar 26 02:09:21 PM PDT 24
Peak memory 249084 kb
Host smart-083c23a1-9a9d-440f-a9c1-526481d0b643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22216
15087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2221615087
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2343116626
Short name T252
Test name
Test status
Simulation time 12178574660 ps
CPU time 43.55 seconds
Started Mar 26 02:09:11 PM PDT 24
Finished Mar 26 02:09:54 PM PDT 24
Peak memory 255568 kb
Host smart-9f240cb8-76f3-48b2-9152-8937160950fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
16626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2343116626
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.4025410237
Short name T461
Test name
Test status
Simulation time 69873544 ps
CPU time 6.03 seconds
Started Mar 26 02:09:09 PM PDT 24
Finished Mar 26 02:09:15 PM PDT 24
Peak memory 240596 kb
Host smart-dd32c1e6-1d6e-4114-a715-b3f5081e7bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40254
10237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.4025410237
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3510652134
Short name T311
Test name
Test status
Simulation time 81836051190 ps
CPU time 2648.11 seconds
Started Mar 26 02:09:30 PM PDT 24
Finished Mar 26 02:53:39 PM PDT 24
Peak memory 289600 kb
Host smart-4b1d3c1d-c67d-44af-ba1b-a93ca6525ec3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510652134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3510652134
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.530580668
Short name T206
Test name
Test status
Simulation time 18337144986 ps
CPU time 349.15 seconds
Started Mar 26 02:09:19 PM PDT 24
Finished Mar 26 02:15:09 PM PDT 24
Peak memory 257040 kb
Host smart-35f663f6-7521-4271-9e5a-08801fffdf1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53058
0668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.530580668
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.752960635
Short name T411
Test name
Test status
Simulation time 1268523567 ps
CPU time 47.19 seconds
Started Mar 26 02:09:19 PM PDT 24
Finished Mar 26 02:10:06 PM PDT 24
Peak memory 255544 kb
Host smart-03ef8e0f-6774-4d07-b6bd-20e0e4566533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75296
0635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.752960635
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2402646200
Short name T260
Test name
Test status
Simulation time 61833846626 ps
CPU time 1161.94 seconds
Started Mar 26 02:09:30 PM PDT 24
Finished Mar 26 02:28:53 PM PDT 24
Peak memory 288860 kb
Host smart-08ad5e12-9237-4e45-b03d-417db8e7e284
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402646200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2402646200
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2486857136
Short name T297
Test name
Test status
Simulation time 208941341686 ps
CPU time 3314.5 seconds
Started Mar 26 02:09:30 PM PDT 24
Finished Mar 26 03:04:45 PM PDT 24
Peak memory 289624 kb
Host smart-72762851-2a3a-4a75-893b-91fa65b4b6dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486857136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2486857136
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1201071819
Short name T619
Test name
Test status
Simulation time 12573709514 ps
CPU time 482.86 seconds
Started Mar 26 02:09:30 PM PDT 24
Finished Mar 26 02:17:33 PM PDT 24
Peak memory 248052 kb
Host smart-d17464ff-3878-49ce-9912-3f512bd8cb80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201071819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1201071819
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1810909758
Short name T305
Test name
Test status
Simulation time 154882431 ps
CPU time 11.55 seconds
Started Mar 26 02:09:18 PM PDT 24
Finished Mar 26 02:09:29 PM PDT 24
Peak memory 249224 kb
Host smart-1f74fdc3-f102-46cf-8875-46e0fa29d8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18109
09758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1810909758
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2475062655
Short name T94
Test name
Test status
Simulation time 7373574260 ps
CPU time 45.67 seconds
Started Mar 26 02:09:22 PM PDT 24
Finished Mar 26 02:10:08 PM PDT 24
Peak memory 256380 kb
Host smart-bb4ffd89-8e8c-48d3-98e7-4c100009af5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24750
62655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2475062655
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2962446524
Short name T18
Test name
Test status
Simulation time 153876253 ps
CPU time 21.86 seconds
Started Mar 26 02:09:18 PM PDT 24
Finished Mar 26 02:09:40 PM PDT 24
Peak memory 247472 kb
Host smart-6a167908-f713-480e-98e7-885508fd07b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29624
46524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2962446524
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1888413800
Short name T661
Test name
Test status
Simulation time 223522636 ps
CPU time 21.9 seconds
Started Mar 26 02:09:19 PM PDT 24
Finished Mar 26 02:09:41 PM PDT 24
Peak memory 248868 kb
Host smart-b7998a77-3315-45c8-8234-956575b588dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18884
13800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1888413800
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4151436487
Short name T623
Test name
Test status
Simulation time 289394837888 ps
CPU time 3950.19 seconds
Started Mar 26 02:09:22 PM PDT 24
Finished Mar 26 03:15:13 PM PDT 24
Peak memory 306136 kb
Host smart-7e7af233-0b12-4b32-a6af-a89be15eae1b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151436487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4151436487
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1774838499
Short name T388
Test name
Test status
Simulation time 119431385384 ps
CPU time 1222.43 seconds
Started Mar 26 02:09:31 PM PDT 24
Finished Mar 26 02:29:53 PM PDT 24
Peak memory 289152 kb
Host smart-768baa26-f5cf-46f3-b3aa-fcb647b41bd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774838499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1774838499
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.1590838724
Short name T531
Test name
Test status
Simulation time 719781280 ps
CPU time 45.05 seconds
Started Mar 26 02:09:27 PM PDT 24
Finished Mar 26 02:10:13 PM PDT 24
Peak memory 248388 kb
Host smart-f690978d-9eed-413e-8f5f-ebd56d016120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908
38724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1590838724
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4185850280
Short name T713
Test name
Test status
Simulation time 11504107768 ps
CPU time 49.52 seconds
Started Mar 26 02:09:30 PM PDT 24
Finished Mar 26 02:10:20 PM PDT 24
Peak memory 255468 kb
Host smart-acc835fd-dea4-4438-a5f8-1d8cba159dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
50280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4185850280
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2413627830
Short name T285
Test name
Test status
Simulation time 91885525670 ps
CPU time 1358.22 seconds
Started Mar 26 02:09:28 PM PDT 24
Finished Mar 26 02:32:06 PM PDT 24
Peak memory 288620 kb
Host smart-45424972-0335-44d9-8b27-a6d62d0f0ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413627830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2413627830
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3539917744
Short name T12
Test name
Test status
Simulation time 28762608283 ps
CPU time 1353.19 seconds
Started Mar 26 02:09:27 PM PDT 24
Finished Mar 26 02:32:01 PM PDT 24
Peak memory 289428 kb
Host smart-8849c6e2-8201-42fd-9a70-839e2b2665bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539917744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3539917744
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1431485157
Short name T278
Test name
Test status
Simulation time 32262576777 ps
CPU time 370.82 seconds
Started Mar 26 02:09:27 PM PDT 24
Finished Mar 26 02:15:39 PM PDT 24
Peak memory 255512 kb
Host smart-40ef23ea-46bc-4348-b69a-755932bae394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431485157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1431485157
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.61694147
Short name T587
Test name
Test status
Simulation time 4962110575 ps
CPU time 73.71 seconds
Started Mar 26 02:09:26 PM PDT 24
Finished Mar 26 02:10:40 PM PDT 24
Peak memory 256232 kb
Host smart-67051938-3d58-4ba6-bfa3-0fe2a916b2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61694
147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.61694147
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2098913119
Short name T368
Test name
Test status
Simulation time 229709651 ps
CPU time 15.74 seconds
Started Mar 26 02:09:27 PM PDT 24
Finished Mar 26 02:09:43 PM PDT 24
Peak memory 251692 kb
Host smart-ee0c5255-ddc2-4910-abdf-eb053e09fb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20989
13119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2098913119
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1366892460
Short name T110
Test name
Test status
Simulation time 677042398 ps
CPU time 42.01 seconds
Started Mar 26 02:09:27 PM PDT 24
Finished Mar 26 02:10:09 PM PDT 24
Peak memory 248896 kb
Host smart-d69ec478-c70c-4627-b52a-2ee5f493f273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
92460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1366892460
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2337231662
Short name T389
Test name
Test status
Simulation time 110072194 ps
CPU time 9.23 seconds
Started Mar 26 02:09:27 PM PDT 24
Finished Mar 26 02:09:36 PM PDT 24
Peak memory 254136 kb
Host smart-0b0d6b1f-bcd9-46f6-992e-8dd1699d9b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23372
31662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2337231662
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3102134696
Short name T203
Test name
Test status
Simulation time 141516998 ps
CPU time 3.67 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:07:00 PM PDT 24
Peak memory 249132 kb
Host smart-5c4f1879-a79b-41dc-b5c6-1a5bbccfe6cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3102134696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3102134696
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.393315840
Short name T516
Test name
Test status
Simulation time 23750030245 ps
CPU time 1635.29 seconds
Started Mar 26 02:06:58 PM PDT 24
Finished Mar 26 02:34:14 PM PDT 24
Peak memory 287680 kb
Host smart-209007b4-319c-4f49-adf3-0ad01e4b6cb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393315840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.393315840
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4172940580
Short name T439
Test name
Test status
Simulation time 484105818 ps
CPU time 22.31 seconds
Started Mar 26 02:06:55 PM PDT 24
Finished Mar 26 02:07:18 PM PDT 24
Peak memory 240880 kb
Host smart-73903ec1-7684-4b53-9319-b0724e178752
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4172940580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4172940580
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2314138131
Short name T425
Test name
Test status
Simulation time 3293018659 ps
CPU time 178.45 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:09:55 PM PDT 24
Peak memory 249940 kb
Host smart-551b1086-2bdc-4920-a5d3-de03bd01bac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23141
38131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2314138131
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4023904262
Short name T463
Test name
Test status
Simulation time 2744301326 ps
CPU time 31.6 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:07:28 PM PDT 24
Peak memory 255760 kb
Host smart-ac6e87f8-b156-48f6-94a5-d69e5301e57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40239
04262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4023904262
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3700300347
Short name T657
Test name
Test status
Simulation time 82617430557 ps
CPU time 2520.84 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:48:58 PM PDT 24
Peak memory 289956 kb
Host smart-08abe8bf-d960-485c-8848-2e8df54e0458
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700300347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3700300347
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2066530077
Short name T16
Test name
Test status
Simulation time 18718863256 ps
CPU time 1043.33 seconds
Started Mar 26 02:07:00 PM PDT 24
Finished Mar 26 02:24:24 PM PDT 24
Peak memory 273512 kb
Host smart-0bb48229-6f71-44fc-896a-b9039e8d9771
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066530077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2066530077
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.461820538
Short name T263
Test name
Test status
Simulation time 11566886395 ps
CPU time 472.5 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:14:50 PM PDT 24
Peak memory 247892 kb
Host smart-eca3fb68-c44f-4302-a4ed-2f9ebd3bfc76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461820538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.461820538
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3577420586
Short name T529
Test name
Test status
Simulation time 243682650 ps
CPU time 16.01 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:16 PM PDT 24
Peak memory 248872 kb
Host smart-cd1fd0a5-1530-4fcf-9db9-ebd279b56da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35774
20586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3577420586
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.375087929
Short name T468
Test name
Test status
Simulation time 473130831 ps
CPU time 29.79 seconds
Started Mar 26 02:06:58 PM PDT 24
Finished Mar 26 02:07:28 PM PDT 24
Peak memory 254008 kb
Host smart-9618ae02-0b39-4261-96e6-a9f5c9396e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37508
7929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.375087929
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2855747578
Short name T32
Test name
Test status
Simulation time 1874107493 ps
CPU time 21.66 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:07:19 PM PDT 24
Peak memory 277136 kb
Host smart-b5ae59e0-6272-4cec-9d35-e5b414ab9b02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2855747578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2855747578
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.500523475
Short name T80
Test name
Test status
Simulation time 214201178 ps
CPU time 18.09 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:18 PM PDT 24
Peak memory 247612 kb
Host smart-27c1a2ee-568a-4bfb-9117-1558237e2f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50052
3475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.500523475
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3407779846
Short name T711
Test name
Test status
Simulation time 813737157 ps
CPU time 35.47 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:36 PM PDT 24
Peak memory 255660 kb
Host smart-03247aa0-6fe1-443a-a66a-39058875e29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
79846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3407779846
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1153919743
Short name T48
Test name
Test status
Simulation time 84705898665 ps
CPU time 2108.47 seconds
Started Mar 26 02:06:57 PM PDT 24
Finished Mar 26 02:42:06 PM PDT 24
Peak memory 298200 kb
Host smart-51f9f4b3-277f-4acf-bae4-c1454a1335bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153919743 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1153919743
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1550481353
Short name T694
Test name
Test status
Simulation time 17544955868 ps
CPU time 1314.56 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:31:32 PM PDT 24
Peak memory 265400 kb
Host smart-9389fffd-e9bf-4a6a-8172-3a6cb2510a7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550481353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1550481353
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1501778471
Short name T421
Test name
Test status
Simulation time 685390043 ps
CPU time 25.38 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:10:02 PM PDT 24
Peak memory 247312 kb
Host smart-dee2aae4-33f1-4a17-a72e-540af4b0b623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15017
78471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1501778471
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2009626256
Short name T424
Test name
Test status
Simulation time 3406502559 ps
CPU time 58.09 seconds
Started Mar 26 02:09:38 PM PDT 24
Finished Mar 26 02:10:37 PM PDT 24
Peak memory 255600 kb
Host smart-d9c7e725-5a49-48ef-8661-fcce340fa846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20096
26256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2009626256
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.40944073
Short name T3
Test name
Test status
Simulation time 8916140288 ps
CPU time 732.38 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:21:49 PM PDT 24
Peak memory 265308 kb
Host smart-512efa04-864b-4d82-98bd-b8877977cbd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40944073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.40944073
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.715514844
Short name T280
Test name
Test status
Simulation time 12285125098 ps
CPU time 504.33 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:18:01 PM PDT 24
Peak memory 248104 kb
Host smart-b774dfd5-b1b7-4dbe-b1a6-cc0ae063942e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715514844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.715514844
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1754171328
Short name T533
Test name
Test status
Simulation time 735642902 ps
CPU time 57.77 seconds
Started Mar 26 02:09:38 PM PDT 24
Finished Mar 26 02:10:36 PM PDT 24
Peak memory 248884 kb
Host smart-7607f8e9-24e1-4391-9101-e11aa971a667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541
71328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1754171328
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3802125653
Short name T466
Test name
Test status
Simulation time 125899834 ps
CPU time 10.97 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:09:48 PM PDT 24
Peak memory 251780 kb
Host smart-1e04f5c1-7dfc-4235-a5a8-88d4b452a0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
25653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3802125653
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1567134141
Short name T605
Test name
Test status
Simulation time 453258617 ps
CPU time 31.08 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:10:08 PM PDT 24
Peak memory 256020 kb
Host smart-26777f68-827f-432b-b3b6-4f3e9f0667b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15671
34141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1567134141
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3347955706
Short name T559
Test name
Test status
Simulation time 633811033 ps
CPU time 45.99 seconds
Started Mar 26 02:09:26 PM PDT 24
Finished Mar 26 02:10:12 PM PDT 24
Peak memory 249000 kb
Host smart-ab265c12-102e-465a-ba4f-537b3fe992a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33479
55706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3347955706
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1066988842
Short name T574
Test name
Test status
Simulation time 788340338 ps
CPU time 33.44 seconds
Started Mar 26 02:09:36 PM PDT 24
Finished Mar 26 02:10:10 PM PDT 24
Peak memory 248880 kb
Host smart-794e8eec-4937-4ad2-90b1-9ca13f25f3a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066988842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1066988842
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3605256630
Short name T671
Test name
Test status
Simulation time 13592306167 ps
CPU time 1290.63 seconds
Started Mar 26 02:09:48 PM PDT 24
Finished Mar 26 02:31:19 PM PDT 24
Peak memory 285340 kb
Host smart-6af2a811-60a4-44b0-8121-6ce2240ad021
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605256630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3605256630
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4212496667
Short name T399
Test name
Test status
Simulation time 2157551909 ps
CPU time 179.04 seconds
Started Mar 26 02:09:48 PM PDT 24
Finished Mar 26 02:12:47 PM PDT 24
Peak memory 257092 kb
Host smart-6162cd13-6d32-4d42-8b6d-3ab1ad9bfdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42124
96667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4212496667
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2306836035
Short name T487
Test name
Test status
Simulation time 23372833 ps
CPU time 3.1 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:09:50 PM PDT 24
Peak memory 240620 kb
Host smart-704205a0-449e-4e5a-80dd-903ca2be7c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23068
36035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2306836035
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3559503640
Short name T481
Test name
Test status
Simulation time 41174464072 ps
CPU time 1986.21 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:42:55 PM PDT 24
Peak memory 272836 kb
Host smart-28a18b1c-d2f2-4828-8069-ee1e776cc28e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559503640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3559503640
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.432771928
Short name T636
Test name
Test status
Simulation time 50069852604 ps
CPU time 2668.1 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:54:16 PM PDT 24
Peak memory 281680 kb
Host smart-7944986f-672d-4665-a528-c7bd692ca17f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432771928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.432771928
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1988396585
Short name T273
Test name
Test status
Simulation time 10411102800 ps
CPU time 459.23 seconds
Started Mar 26 02:09:48 PM PDT 24
Finished Mar 26 02:17:28 PM PDT 24
Peak memory 248212 kb
Host smart-e4cfdda4-fd78-4944-91d4-3ac476e4c862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988396585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1988396585
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4076840595
Short name T700
Test name
Test status
Simulation time 228344508 ps
CPU time 9.29 seconds
Started Mar 26 02:09:37 PM PDT 24
Finished Mar 26 02:09:47 PM PDT 24
Peak memory 254092 kb
Host smart-92caa8a1-3fde-4338-8788-3a8b6698e0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40768
40595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4076840595
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3107489417
Short name T645
Test name
Test status
Simulation time 692553026 ps
CPU time 19.78 seconds
Started Mar 26 02:09:40 PM PDT 24
Finished Mar 26 02:10:00 PM PDT 24
Peak memory 248940 kb
Host smart-7c1dc6e9-0221-4824-943b-e5bb118f4dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31074
89417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3107489417
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.540150947
Short name T24
Test name
Test status
Simulation time 230138777 ps
CPU time 28.02 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:10:15 PM PDT 24
Peak memory 247340 kb
Host smart-7abb3a35-43dc-47d6-b791-1860d16fea32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54015
0947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.540150947
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1051376338
Short name T501
Test name
Test status
Simulation time 1191402795 ps
CPU time 38.85 seconds
Started Mar 26 02:09:39 PM PDT 24
Finished Mar 26 02:10:18 PM PDT 24
Peak memory 254684 kb
Host smart-fe902c91-a9f4-4bb1-b180-49a8885fbba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10513
76338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1051376338
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1940888971
Short name T482
Test name
Test status
Simulation time 80375511302 ps
CPU time 1705.03 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:38:13 PM PDT 24
Peak memory 305800 kb
Host smart-4c0143ce-de09-44ce-ba26-69ef01974b78
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940888971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1940888971
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1914685693
Short name T182
Test name
Test status
Simulation time 55546023655 ps
CPU time 4055.4 seconds
Started Mar 26 02:09:46 PM PDT 24
Finished Mar 26 03:17:22 PM PDT 24
Peak memory 305636 kb
Host smart-dab5c1ce-c6fa-47b6-995a-0c07268e1c77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914685693 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1914685693
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1564670222
Short name T473
Test name
Test status
Simulation time 140962655610 ps
CPU time 2479.09 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:51:18 PM PDT 24
Peak memory 289528 kb
Host smart-c718f06e-fc87-4748-97d5-53626192cd6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564670222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1564670222
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.708931813
Short name T232
Test name
Test status
Simulation time 1273177044 ps
CPU time 129.19 seconds
Started Mar 26 02:09:48 PM PDT 24
Finished Mar 26 02:11:58 PM PDT 24
Peak memory 256888 kb
Host smart-4b629e6c-0134-4677-917a-8c65cc7cf992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70893
1813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.708931813
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1682342394
Short name T683
Test name
Test status
Simulation time 536914415 ps
CPU time 27.52 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:10:15 PM PDT 24
Peak memory 255508 kb
Host smart-0d2ae73e-2489-44f6-9d4a-79de499fa544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16823
42394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1682342394
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2646408665
Short name T261
Test name
Test status
Simulation time 131169762742 ps
CPU time 2188.83 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:46:28 PM PDT 24
Peak memory 285700 kb
Host smart-814a8fd4-a723-42f6-98af-8225c1ce467c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646408665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2646408665
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1968737586
Short name T17
Test name
Test status
Simulation time 39986131525 ps
CPU time 2669.24 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:54:28 PM PDT 24
Peak memory 289384 kb
Host smart-beb3992c-85e9-4488-aa0a-e4f81154c9eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968737586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1968737586
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2400183164
Short name T528
Test name
Test status
Simulation time 18389437272 ps
CPU time 561.6 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:19:20 PM PDT 24
Peak memory 247324 kb
Host smart-18fd8b72-b4a2-4549-bbbb-270b6698be3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400183164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2400183164
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1428952655
Short name T561
Test name
Test status
Simulation time 856556672 ps
CPU time 13.15 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:10:00 PM PDT 24
Peak memory 254156 kb
Host smart-41ba79e0-6589-4dd1-939e-25249d33e809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14289
52655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1428952655
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1369586968
Short name T209
Test name
Test status
Simulation time 490681499 ps
CPU time 20.88 seconds
Started Mar 26 02:09:47 PM PDT 24
Finished Mar 26 02:10:08 PM PDT 24
Peak memory 256652 kb
Host smart-041c77be-0d93-4949-b24f-3d087290409b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13695
86968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1369586968
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.199938409
Short name T573
Test name
Test status
Simulation time 373552912 ps
CPU time 25.54 seconds
Started Mar 26 02:09:46 PM PDT 24
Finished Mar 26 02:10:12 PM PDT 24
Peak memory 254992 kb
Host smart-395b60de-3d12-4617-a878-9bcc3c616e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19993
8409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.199938409
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1563389910
Short name T602
Test name
Test status
Simulation time 98368971 ps
CPU time 11.51 seconds
Started Mar 26 02:09:49 PM PDT 24
Finished Mar 26 02:10:01 PM PDT 24
Peak memory 248820 kb
Host smart-7c035bb8-b637-4519-87e0-9f7702c625f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15633
89910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1563389910
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2083704958
Short name T514
Test name
Test status
Simulation time 90287962010 ps
CPU time 552.39 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:19:10 PM PDT 24
Peak memory 257120 kb
Host smart-0e7c165f-8b04-4da3-b9be-e9ec632af1ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083704958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2083704958
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1813934468
Short name T70
Test name
Test status
Simulation time 158455556174 ps
CPU time 4890.25 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 03:31:29 PM PDT 24
Peak memory 355184 kb
Host smart-d86650d6-241f-4f83-9cc3-242aed0145c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813934468 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1813934468
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2023624050
Short name T87
Test name
Test status
Simulation time 33777379329 ps
CPU time 2111.7 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:45:10 PM PDT 24
Peak memory 273536 kb
Host smart-1b716084-a666-43d2-9d24-0ae73b4d7c9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023624050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2023624050
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2269683449
Short name T39
Test name
Test status
Simulation time 167893834 ps
CPU time 20.77 seconds
Started Mar 26 02:09:59 PM PDT 24
Finished Mar 26 02:10:20 PM PDT 24
Peak memory 255948 kb
Host smart-0f3067d2-5fa1-4193-b440-ba41a78e4b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22696
83449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2269683449
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3403115489
Short name T567
Test name
Test status
Simulation time 1404000293 ps
CPU time 48.69 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:10:46 PM PDT 24
Peak memory 255448 kb
Host smart-bb2cd4ea-00e0-4e37-801e-1375448ef634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34031
15489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3403115489
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1044966091
Short name T328
Test name
Test status
Simulation time 9390299321 ps
CPU time 853.52 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:24:11 PM PDT 24
Peak memory 272224 kb
Host smart-9f21e67a-0b98-493c-be99-e66a890e5997
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044966091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1044966091
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.632927962
Short name T406
Test name
Test status
Simulation time 124351980365 ps
CPU time 2123.55 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:45:22 PM PDT 24
Peak memory 273524 kb
Host smart-45d7aefd-7928-4f12-a6df-3e3de25c9d5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632927962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.632927962
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.718187631
Short name T615
Test name
Test status
Simulation time 13196383007 ps
CPU time 283.46 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:14:41 PM PDT 24
Peak memory 247760 kb
Host smart-9259c4ea-91c4-4c52-957c-4c3a2273e149
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718187631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.718187631
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.413496570
Short name T490
Test name
Test status
Simulation time 610695110 ps
CPU time 13.44 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:10:11 PM PDT 24
Peak memory 248956 kb
Host smart-5f5da935-886d-4eaa-9620-298ebc391c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41349
6570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.413496570
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.989882280
Short name T92
Test name
Test status
Simulation time 317281761 ps
CPU time 30.73 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:10:29 PM PDT 24
Peak memory 256648 kb
Host smart-e47096e2-75ab-4350-b8f0-8f4464870a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98988
2280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.989882280
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3320921779
Short name T592
Test name
Test status
Simulation time 292340166 ps
CPU time 40.53 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:10:38 PM PDT 24
Peak memory 256680 kb
Host smart-8eadec4c-f773-44c7-99ab-1ac2786df3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33209
21779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3320921779
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3570840142
Short name T43
Test name
Test status
Simulation time 1102891624 ps
CPU time 70.72 seconds
Started Mar 26 02:09:58 PM PDT 24
Finished Mar 26 02:11:09 PM PDT 24
Peak memory 257188 kb
Host smart-761f2e85-3d46-4d83-83be-a71b5e205d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35708
40142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3570840142
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1377827309
Short name T302
Test name
Test status
Simulation time 11422696074 ps
CPU time 309.6 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:15:08 PM PDT 24
Peak memory 257056 kb
Host smart-11b3e8df-c318-45af-bf3b-eba33a4de20b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377827309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1377827309
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.4080445475
Short name T653
Test name
Test status
Simulation time 115366627259 ps
CPU time 7265.59 seconds
Started Mar 26 02:09:59 PM PDT 24
Finished Mar 26 04:11:05 PM PDT 24
Peak memory 371140 kb
Host smart-5755f65b-498d-4bef-8ffb-9eedad8f792c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080445475 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.4080445475
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1371189371
Short name T635
Test name
Test status
Simulation time 114480097327 ps
CPU time 1929.13 seconds
Started Mar 26 02:10:08 PM PDT 24
Finished Mar 26 02:42:18 PM PDT 24
Peak memory 273520 kb
Host smart-9fc7e1e2-af74-4d01-85b7-330d21fab72a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371189371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1371189371
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1287713322
Short name T176
Test name
Test status
Simulation time 9086756063 ps
CPU time 289.76 seconds
Started Mar 26 02:10:09 PM PDT 24
Finished Mar 26 02:14:59 PM PDT 24
Peak memory 256884 kb
Host smart-d15fba54-35c5-4309-94ab-faa54669edcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
13322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1287713322
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2950525271
Short name T611
Test name
Test status
Simulation time 360220715 ps
CPU time 35.53 seconds
Started Mar 26 02:10:07 PM PDT 24
Finished Mar 26 02:10:43 PM PDT 24
Peak memory 248800 kb
Host smart-8942b1a0-cdc0-4c85-99d2-9d2939fe7cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29505
25271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2950525271
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3041338107
Short name T333
Test name
Test status
Simulation time 79984828808 ps
CPU time 1254.08 seconds
Started Mar 26 02:10:07 PM PDT 24
Finished Mar 26 02:31:02 PM PDT 24
Peak memory 265292 kb
Host smart-7196a333-0b05-4259-8ada-d80a84e96653
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041338107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3041338107
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.17636631
Short name T590
Test name
Test status
Simulation time 141807813052 ps
CPU time 3445.45 seconds
Started Mar 26 02:10:07 PM PDT 24
Finished Mar 26 03:07:33 PM PDT 24
Peak memory 289352 kb
Host smart-d2431d58-bb8a-4911-b293-8b8b84881067
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17636631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.17636631
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.516374399
Short name T22
Test name
Test status
Simulation time 310555425 ps
CPU time 27.06 seconds
Started Mar 26 02:10:07 PM PDT 24
Finished Mar 26 02:10:34 PM PDT 24
Peak memory 248884 kb
Host smart-8166296b-dece-4f8c-807f-65da0a5cf246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51637
4399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.516374399
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2425137496
Short name T58
Test name
Test status
Simulation time 941456519 ps
CPU time 32.37 seconds
Started Mar 26 02:10:05 PM PDT 24
Finished Mar 26 02:10:38 PM PDT 24
Peak memory 255484 kb
Host smart-15b74e33-7904-42c6-a597-1c69ffaf5995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
37496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2425137496
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1094349797
Short name T109
Test name
Test status
Simulation time 527885853 ps
CPU time 14.47 seconds
Started Mar 26 02:10:10 PM PDT 24
Finished Mar 26 02:10:25 PM PDT 24
Peak memory 255828 kb
Host smart-0eee13de-b940-44dc-9b98-0c6ff01826c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
49797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1094349797
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4091446597
Short name T659
Test name
Test status
Simulation time 382656731 ps
CPU time 38.61 seconds
Started Mar 26 02:09:57 PM PDT 24
Finished Mar 26 02:10:37 PM PDT 24
Peak memory 248844 kb
Host smart-68a179ca-da8b-4d88-a4ad-075faec61670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40914
46597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4091446597
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2692848578
Short name T107
Test name
Test status
Simulation time 19561238640 ps
CPU time 1390.77 seconds
Started Mar 26 02:10:08 PM PDT 24
Finished Mar 26 02:33:19 PM PDT 24
Peak memory 273484 kb
Host smart-989576c7-e7f5-41cb-8a04-9b583ae48c10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692848578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2692848578
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1190627712
Short name T74
Test name
Test status
Simulation time 145476229268 ps
CPU time 4708.17 seconds
Started Mar 26 02:10:09 PM PDT 24
Finished Mar 26 03:28:38 PM PDT 24
Peak memory 322040 kb
Host smart-0318e09b-ba4c-4c19-8d42-fb938c10ae8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190627712 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1190627712
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.270091938
Short name T560
Test name
Test status
Simulation time 30222849517 ps
CPU time 1770.93 seconds
Started Mar 26 02:10:18 PM PDT 24
Finished Mar 26 02:39:49 PM PDT 24
Peak memory 269532 kb
Host smart-0a118368-b97a-4d49-87aa-39d16722f6f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270091938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.270091938
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1798000013
Short name T370
Test name
Test status
Simulation time 1485002281 ps
CPU time 87.51 seconds
Started Mar 26 02:10:19 PM PDT 24
Finished Mar 26 02:11:46 PM PDT 24
Peak memory 256704 kb
Host smart-7243c1fa-ad88-4429-a676-d8384c7bb243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17980
00013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1798000013
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4146616725
Short name T540
Test name
Test status
Simulation time 2909388262 ps
CPU time 30.18 seconds
Started Mar 26 02:10:17 PM PDT 24
Finished Mar 26 02:10:48 PM PDT 24
Peak memory 255620 kb
Host smart-860aea12-ec22-4069-9df6-aed3649bfdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41466
16725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4146616725
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.501722150
Short name T334
Test name
Test status
Simulation time 79367213712 ps
CPU time 2575.66 seconds
Started Mar 26 02:10:19 PM PDT 24
Finished Mar 26 02:53:15 PM PDT 24
Peak memory 282612 kb
Host smart-fba3ad0f-95ec-49d5-8e0c-3348e75f8123
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501722150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.501722150
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.474356728
Short name T15
Test name
Test status
Simulation time 25792230963 ps
CPU time 717.29 seconds
Started Mar 26 02:10:18 PM PDT 24
Finished Mar 26 02:22:16 PM PDT 24
Peak memory 272784 kb
Host smart-13adf7e4-62dc-446b-a7c3-81b77169b690
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474356728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.474356728
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4170514882
Short name T224
Test name
Test status
Simulation time 25822248695 ps
CPU time 294.96 seconds
Started Mar 26 02:10:24 PM PDT 24
Finished Mar 26 02:15:19 PM PDT 24
Peak memory 248132 kb
Host smart-b74f6a7f-33dc-4068-8e97-6114ef0e1464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170514882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4170514882
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3853096189
Short name T558
Test name
Test status
Simulation time 569590094 ps
CPU time 35.22 seconds
Started Mar 26 02:10:08 PM PDT 24
Finished Mar 26 02:10:43 PM PDT 24
Peak memory 257072 kb
Host smart-5f19ef59-5c6c-4db7-9951-7171f4990a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
96189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3853096189
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.400571307
Short name T470
Test name
Test status
Simulation time 380855971 ps
CPU time 25.88 seconds
Started Mar 26 02:10:08 PM PDT 24
Finished Mar 26 02:10:34 PM PDT 24
Peak memory 254548 kb
Host smart-28addb02-6e0b-490b-b8fc-b16e7c8de538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40057
1307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.400571307
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3969529111
Short name T422
Test name
Test status
Simulation time 634697832 ps
CPU time 37.46 seconds
Started Mar 26 02:10:18 PM PDT 24
Finished Mar 26 02:10:55 PM PDT 24
Peak memory 255776 kb
Host smart-78e6bab2-f660-4d08-bbed-53b90b4383ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39695
29111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3969529111
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2004404841
Short name T392
Test name
Test status
Simulation time 623372240 ps
CPU time 28.09 seconds
Started Mar 26 02:10:10 PM PDT 24
Finished Mar 26 02:10:38 PM PDT 24
Peak memory 248844 kb
Host smart-6dffec37-e574-42b5-9ef8-d8fd31fdc55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
04841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2004404841
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3143770210
Short name T235
Test name
Test status
Simulation time 19049257057 ps
CPU time 1721.42 seconds
Started Mar 26 02:10:24 PM PDT 24
Finished Mar 26 02:39:06 PM PDT 24
Peak memory 289736 kb
Host smart-b8b1d660-d54b-430a-8ae6-3b9f6b2373b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143770210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3143770210
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2097141911
Short name T613
Test name
Test status
Simulation time 375202226077 ps
CPU time 3640.54 seconds
Started Mar 26 02:10:24 PM PDT 24
Finished Mar 26 03:11:05 PM PDT 24
Peak memory 306296 kb
Host smart-236271af-995d-44df-9362-4f28cc9720e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097141911 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2097141911
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2654364572
Short name T97
Test name
Test status
Simulation time 15608209010 ps
CPU time 1482.97 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:35:11 PM PDT 24
Peak memory 285836 kb
Host smart-c1c39621-1ae1-4dad-bdb0-660b96ab9980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654364572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2654364572
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2054290178
Short name T207
Test name
Test status
Simulation time 11696494748 ps
CPU time 203.24 seconds
Started Mar 26 02:10:18 PM PDT 24
Finished Mar 26 02:13:41 PM PDT 24
Peak memory 257116 kb
Host smart-7e502890-e0d8-4f65-94db-50509d1b2760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20542
90178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2054290178
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1706686692
Short name T686
Test name
Test status
Simulation time 332449838 ps
CPU time 10.76 seconds
Started Mar 26 02:10:19 PM PDT 24
Finished Mar 26 02:10:30 PM PDT 24
Peak memory 254652 kb
Host smart-46b03fae-9384-4581-b8a4-92231e9410f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17066
86692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1706686692
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4071324291
Short name T317
Test name
Test status
Simulation time 40938090941 ps
CPU time 1720.54 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:39:09 PM PDT 24
Peak memory 289196 kb
Host smart-b3fcdcd3-58a8-41a9-bc3e-f360bb4fce0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071324291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4071324291
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3249968843
Short name T222
Test name
Test status
Simulation time 150720166420 ps
CPU time 2637.33 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:54:26 PM PDT 24
Peak memory 288652 kb
Host smart-73a4d590-3870-42e6-a230-3364a2e9f6e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249968843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3249968843
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3430521603
Short name T215
Test name
Test status
Simulation time 56428827153 ps
CPU time 572.15 seconds
Started Mar 26 02:10:30 PM PDT 24
Finished Mar 26 02:20:02 PM PDT 24
Peak memory 248180 kb
Host smart-2049be63-e381-4b2a-b3fa-59a1335c7264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430521603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3430521603
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.215307140
Short name T594
Test name
Test status
Simulation time 194960158 ps
CPU time 19.03 seconds
Started Mar 26 02:10:23 PM PDT 24
Finished Mar 26 02:10:42 PM PDT 24
Peak memory 248784 kb
Host smart-b052dae4-6f4f-4453-95b7-2cf74f9c84fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
7140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.215307140
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4002583260
Short name T651
Test name
Test status
Simulation time 1946822418 ps
CPU time 57.17 seconds
Started Mar 26 02:10:20 PM PDT 24
Finished Mar 26 02:11:17 PM PDT 24
Peak memory 248788 kb
Host smart-9072698d-916f-41de-9f60-091dbac55332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
83260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4002583260
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1458588267
Short name T427
Test name
Test status
Simulation time 217021884 ps
CPU time 4.49 seconds
Started Mar 26 02:10:19 PM PDT 24
Finished Mar 26 02:10:23 PM PDT 24
Peak memory 240664 kb
Host smart-0a1de4fa-31f4-4ad5-b7da-ccd32b88e77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14585
88267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1458588267
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1857927521
Short name T556
Test name
Test status
Simulation time 307565616 ps
CPU time 5.95 seconds
Started Mar 26 02:10:18 PM PDT 24
Finished Mar 26 02:10:24 PM PDT 24
Peak memory 240696 kb
Host smart-43dca92b-b1f2-4c5f-a8b8-a7f7c2ed7765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18579
27521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1857927521
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1707703461
Short name T4
Test name
Test status
Simulation time 139051534209 ps
CPU time 2550.21 seconds
Started Mar 26 02:10:29 PM PDT 24
Finished Mar 26 02:53:00 PM PDT 24
Peak memory 289196 kb
Host smart-685af4fe-f06f-4eca-ad3a-61ef3ebd8cd2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707703461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1707703461
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1540973860
Short name T105
Test name
Test status
Simulation time 367879084935 ps
CPU time 2555.09 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:53:03 PM PDT 24
Peak memory 322292 kb
Host smart-807be5a6-4582-490a-9ace-ec67db6352e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540973860 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1540973860
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3674588525
Short name T684
Test name
Test status
Simulation time 120532696134 ps
CPU time 1918.38 seconds
Started Mar 26 02:10:35 PM PDT 24
Finished Mar 26 02:42:34 PM PDT 24
Peak memory 281680 kb
Host smart-41c8ce6c-af02-4850-bc79-10d6327af964
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674588525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3674588525
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3733532888
Short name T712
Test name
Test status
Simulation time 1629624892 ps
CPU time 72.29 seconds
Started Mar 26 02:10:26 PM PDT 24
Finished Mar 26 02:11:38 PM PDT 24
Peak memory 256580 kb
Host smart-6f6201c1-bc4a-423b-845e-d6f5e2c6ca4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37335
32888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3733532888
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.838570880
Short name T695
Test name
Test status
Simulation time 11466254831 ps
CPU time 68.4 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:11:36 PM PDT 24
Peak memory 249020 kb
Host smart-5632a0b7-f925-4672-bfcd-99d37fbd5ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83857
0880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.838570880
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.699905222
Short name T284
Test name
Test status
Simulation time 858956988070 ps
CPU time 2545.57 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:52:53 PM PDT 24
Peak memory 283392 kb
Host smart-37fbe3d6-713a-4cfb-90a8-22346972c094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699905222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.699905222
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4081120122
Short name T304
Test name
Test status
Simulation time 53560581909 ps
CPU time 3195.86 seconds
Started Mar 26 02:10:39 PM PDT 24
Finished Mar 26 03:03:55 PM PDT 24
Peak memory 289556 kb
Host smart-16eae468-90f4-44d5-9b3a-335a481ae3fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081120122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4081120122
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.956431812
Short name T226
Test name
Test status
Simulation time 58003391403 ps
CPU time 581.04 seconds
Started Mar 26 02:10:30 PM PDT 24
Finished Mar 26 02:20:11 PM PDT 24
Peak memory 255244 kb
Host smart-4ae3cc5e-df72-4ed4-bedb-db0bbe0fd478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956431812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.956431812
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1388294495
Short name T650
Test name
Test status
Simulation time 185161344 ps
CPU time 9.71 seconds
Started Mar 26 02:10:28 PM PDT 24
Finished Mar 26 02:10:38 PM PDT 24
Peak memory 248804 kb
Host smart-9f5617b1-adf5-49f8-ad10-5bdf7d7a38d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13882
94495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1388294495
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3646661796
Short name T440
Test name
Test status
Simulation time 647446192 ps
CPU time 45.46 seconds
Started Mar 26 02:10:35 PM PDT 24
Finished Mar 26 02:11:20 PM PDT 24
Peak memory 255488 kb
Host smart-0ed7b624-3db1-4270-8ee7-7b4af3664e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36466
61796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3646661796
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2762441132
Short name T391
Test name
Test status
Simulation time 826169160 ps
CPU time 22.13 seconds
Started Mar 26 02:10:27 PM PDT 24
Finished Mar 26 02:10:49 PM PDT 24
Peak memory 254968 kb
Host smart-3fe5d4e2-c036-49c4-8cb6-9c00649720fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624
41132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2762441132
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3256690003
Short name T537
Test name
Test status
Simulation time 270812822 ps
CPU time 17.87 seconds
Started Mar 26 02:10:27 PM PDT 24
Finished Mar 26 02:10:45 PM PDT 24
Peak memory 248808 kb
Host smart-09b9aecc-93b1-46c7-9a23-b5a99e762577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
90003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3256690003
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3068409361
Short name T98
Test name
Test status
Simulation time 50995208461 ps
CPU time 2553.42 seconds
Started Mar 26 02:10:38 PM PDT 24
Finished Mar 26 02:53:12 PM PDT 24
Peak memory 289792 kb
Host smart-7daa79cc-cf56-4265-8a80-293a50719930
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068409361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3068409361
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.648598920
Short name T581
Test name
Test status
Simulation time 13414380407 ps
CPU time 103.63 seconds
Started Mar 26 02:10:40 PM PDT 24
Finished Mar 26 02:12:24 PM PDT 24
Peak memory 256448 kb
Host smart-5eed2e3d-3333-48f8-ac4b-0c0163beebaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64859
8920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.648598920
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1237893074
Short name T553
Test name
Test status
Simulation time 789737286 ps
CPU time 44.36 seconds
Started Mar 26 02:10:39 PM PDT 24
Finished Mar 26 02:11:23 PM PDT 24
Peak memory 248588 kb
Host smart-ca815806-3213-4e40-a20a-b6a55a986a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
93074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1237893074
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3973789374
Short name T330
Test name
Test status
Simulation time 158888732909 ps
CPU time 2674.3 seconds
Started Mar 26 02:10:51 PM PDT 24
Finished Mar 26 02:55:25 PM PDT 24
Peak memory 289420 kb
Host smart-0102450b-4010-4d3e-b4fe-669f387034db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973789374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3973789374
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2156570370
Short name T82
Test name
Test status
Simulation time 188336505092 ps
CPU time 2636.72 seconds
Started Mar 26 02:10:49 PM PDT 24
Finished Mar 26 02:54:47 PM PDT 24
Peak memory 289064 kb
Host smart-5455c51a-a2a1-4b14-b0ca-904db77ba7be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156570370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2156570370
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.922861739
Short name T677
Test name
Test status
Simulation time 6585268154 ps
CPU time 272.14 seconds
Started Mar 26 02:10:40 PM PDT 24
Finished Mar 26 02:15:12 PM PDT 24
Peak memory 247056 kb
Host smart-b68e3fdd-170e-4467-84ad-3ce9c8196dbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922861739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.922861739
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2623376997
Short name T301
Test name
Test status
Simulation time 701401594 ps
CPU time 23.56 seconds
Started Mar 26 02:10:39 PM PDT 24
Finished Mar 26 02:11:03 PM PDT 24
Peak memory 255572 kb
Host smart-fab24362-6d40-4921-a098-9bce7c986350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26233
76997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2623376997
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2796294415
Short name T62
Test name
Test status
Simulation time 271407541 ps
CPU time 25.74 seconds
Started Mar 26 02:10:40 PM PDT 24
Finished Mar 26 02:11:05 PM PDT 24
Peak memory 255576 kb
Host smart-87122a74-698e-4ca2-b91b-516daeb41254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27962
94415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2796294415
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1262366304
Short name T453
Test name
Test status
Simulation time 265613859 ps
CPU time 31.21 seconds
Started Mar 26 02:10:38 PM PDT 24
Finished Mar 26 02:11:10 PM PDT 24
Peak memory 248788 kb
Host smart-a9fa3461-372b-4d21-ae83-8db1441909e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
66304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1262366304
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3519960142
Short name T375
Test name
Test status
Simulation time 6876731449 ps
CPU time 29.91 seconds
Started Mar 26 02:10:41 PM PDT 24
Finished Mar 26 02:11:11 PM PDT 24
Peak memory 249120 kb
Host smart-4d51c91d-44de-4abf-a183-674f760bdb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35199
60142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3519960142
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1217717763
Short name T675
Test name
Test status
Simulation time 46349403952 ps
CPU time 1337.28 seconds
Started Mar 26 02:10:51 PM PDT 24
Finished Mar 26 02:33:09 PM PDT 24
Peak memory 289508 kb
Host smart-baa6f8f3-6e3d-431c-acd5-bafa659ce456
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217717763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1217717763
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3706949361
Short name T648
Test name
Test status
Simulation time 47268341226 ps
CPU time 1651.07 seconds
Started Mar 26 02:10:50 PM PDT 24
Finished Mar 26 02:38:22 PM PDT 24
Peak memory 270620 kb
Host smart-03d21d59-eb57-45fb-8a12-c19457f5367d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706949361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3706949361
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1917232545
Short name T355
Test name
Test status
Simulation time 1040841847 ps
CPU time 72.19 seconds
Started Mar 26 02:10:49 PM PDT 24
Finished Mar 26 02:12:01 PM PDT 24
Peak memory 256768 kb
Host smart-1cbd362f-2bff-45a7-92ec-968d64b19e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19172
32545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1917232545
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.889129344
Short name T358
Test name
Test status
Simulation time 386633206 ps
CPU time 14.79 seconds
Started Mar 26 02:10:51 PM PDT 24
Finished Mar 26 02:11:06 PM PDT 24
Peak memory 255800 kb
Host smart-66aafaa3-34da-465a-b91a-cc5baf3246a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88912
9344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.889129344
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4254739707
Short name T691
Test name
Test status
Simulation time 10871320938 ps
CPU time 441.6 seconds
Started Mar 26 02:10:54 PM PDT 24
Finished Mar 26 02:18:16 PM PDT 24
Peak memory 247812 kb
Host smart-c47ada99-add9-4881-ad01-691cba217a1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254739707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4254739707
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1705070435
Short name T34
Test name
Test status
Simulation time 674280589 ps
CPU time 24.1 seconds
Started Mar 26 02:10:49 PM PDT 24
Finished Mar 26 02:11:14 PM PDT 24
Peak memory 248900 kb
Host smart-bdf57251-0ad6-4b3a-b385-6c55f12985aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
70435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1705070435
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1358250928
Short name T682
Test name
Test status
Simulation time 369728731 ps
CPU time 39 seconds
Started Mar 26 02:10:51 PM PDT 24
Finished Mar 26 02:11:30 PM PDT 24
Peak memory 247432 kb
Host smart-ae51d228-36cf-4e96-91d9-6c092a34ec46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13582
50928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1358250928
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.726403540
Short name T85
Test name
Test status
Simulation time 188381072 ps
CPU time 12.54 seconds
Started Mar 26 02:10:50 PM PDT 24
Finished Mar 26 02:11:03 PM PDT 24
Peak memory 248804 kb
Host smart-1bf9d809-df28-4480-9a74-fbec308d400a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72640
3540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.726403540
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2720171791
Short name T367
Test name
Test status
Simulation time 2637196958 ps
CPU time 35.45 seconds
Started Mar 26 02:10:50 PM PDT 24
Finished Mar 26 02:11:26 PM PDT 24
Peak memory 256016 kb
Host smart-b3baed63-e8ca-4c56-b186-0c13f1c681a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
71791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2720171791
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1611796880
Short name T294
Test name
Test status
Simulation time 14573004596 ps
CPU time 218.15 seconds
Started Mar 26 02:10:48 PM PDT 24
Finished Mar 26 02:14:27 PM PDT 24
Peak memory 257064 kb
Host smart-2000b142-3c15-4263-8124-b0eb955afd72
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611796880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1611796880
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1143037774
Short name T195
Test name
Test status
Simulation time 42913737 ps
CPU time 4.12 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:13 PM PDT 24
Peak memory 249128 kb
Host smart-6f2c5393-dadf-450c-9749-bc3effb7d156
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1143037774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1143037774
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2947906700
Short name T262
Test name
Test status
Simulation time 47146458311 ps
CPU time 2707.57 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:52:04 PM PDT 24
Peak memory 281768 kb
Host smart-9ba7791c-5153-4a80-9fa7-e7c874d53e5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947906700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2947906700
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1490328082
Short name T409
Test name
Test status
Simulation time 505784953 ps
CPU time 13.31 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:22 PM PDT 24
Peak memory 248832 kb
Host smart-a3e38747-086a-4745-b991-8170d29fc5c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1490328082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1490328082
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1284507072
Short name T420
Test name
Test status
Simulation time 1953643579 ps
CPU time 76.85 seconds
Started Mar 26 02:06:55 PM PDT 24
Finished Mar 26 02:08:12 PM PDT 24
Peak memory 256544 kb
Host smart-eff80a6f-cf1f-4075-9899-6431214581cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12845
07072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1284507072
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3668658996
Short name T515
Test name
Test status
Simulation time 329235692 ps
CPU time 18.19 seconds
Started Mar 26 02:07:00 PM PDT 24
Finished Mar 26 02:07:18 PM PDT 24
Peak memory 255400 kb
Host smart-76f57b70-da64-4bbe-a3bf-faba6f034c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36686
58996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3668658996
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3595111129
Short name T519
Test name
Test status
Simulation time 62029546222 ps
CPU time 1207.31 seconds
Started Mar 26 02:07:10 PM PDT 24
Finished Mar 26 02:27:18 PM PDT 24
Peak memory 265408 kb
Host smart-9f78e77e-f390-4e7b-b9d1-77fce8ee70d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595111129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3595111129
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1330394427
Short name T95
Test name
Test status
Simulation time 40410538927 ps
CPU time 1327.11 seconds
Started Mar 26 02:07:12 PM PDT 24
Finished Mar 26 02:29:20 PM PDT 24
Peak memory 271920 kb
Host smart-13733153-40f8-4e32-8859-3e764dd9a34d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330394427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1330394427
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1129458552
Short name T267
Test name
Test status
Simulation time 46002959006 ps
CPU time 493.59 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:15:10 PM PDT 24
Peak memory 248356 kb
Host smart-249571d5-5e71-4458-96ba-c53c523d380c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129458552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1129458552
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.374827808
Short name T346
Test name
Test status
Simulation time 10666811039 ps
CPU time 53.27 seconds
Started Mar 26 02:07:00 PM PDT 24
Finished Mar 26 02:07:54 PM PDT 24
Peak memory 256088 kb
Host smart-ee10f63b-30ff-4e37-8d87-3a8aedd9b8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37482
7808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.374827808
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4263752586
Short name T491
Test name
Test status
Simulation time 1988376421 ps
CPU time 40.55 seconds
Started Mar 26 02:06:56 PM PDT 24
Finished Mar 26 02:07:37 PM PDT 24
Peak memory 255420 kb
Host smart-871f21ae-ccdf-4db3-9d07-f8b77846e4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42637
52586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4263752586
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1893322737
Short name T11
Test name
Test status
Simulation time 548113840 ps
CPU time 24.51 seconds
Started Mar 26 02:07:12 PM PDT 24
Finished Mar 26 02:07:37 PM PDT 24
Peak memory 275200 kb
Host smart-62d21e82-d256-4d36-a5f8-a6e57c8e61cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1893322737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1893322737
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2676382333
Short name T638
Test name
Test status
Simulation time 4579210053 ps
CPU time 39.42 seconds
Started Mar 26 02:06:59 PM PDT 24
Finished Mar 26 02:07:38 PM PDT 24
Peak memory 255500 kb
Host smart-e17352dd-3e4d-44ef-a6d3-cc7168d432c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26763
82333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2676382333
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3144968801
Short name T663
Test name
Test status
Simulation time 548432976 ps
CPU time 18.85 seconds
Started Mar 26 02:06:58 PM PDT 24
Finished Mar 26 02:07:17 PM PDT 24
Peak memory 255452 kb
Host smart-2e95c544-a438-4762-af07-84c6911ddbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31449
68801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3144968801
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1252704193
Short name T680
Test name
Test status
Simulation time 546208520453 ps
CPU time 9024.56 seconds
Started Mar 26 02:07:07 PM PDT 24
Finished Mar 26 04:37:33 PM PDT 24
Peak memory 395476 kb
Host smart-8b74aba2-54a6-4966-b686-1b15b8ba772e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252704193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1252704193
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.856077816
Short name T565
Test name
Test status
Simulation time 160391860617 ps
CPU time 2621.42 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:54:42 PM PDT 24
Peak memory 289588 kb
Host smart-3f886f40-8783-460f-b95a-850194f7955e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856077816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.856077816
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1933207531
Short name T361
Test name
Test status
Simulation time 19043652914 ps
CPU time 259.43 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:15:20 PM PDT 24
Peak memory 249892 kb
Host smart-13c9e9fb-50ab-4607-b9bf-2b4b454fb3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19332
07531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1933207531
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.58011313
Short name T446
Test name
Test status
Simulation time 183696877 ps
CPU time 10.35 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:11:11 PM PDT 24
Peak memory 253556 kb
Host smart-6065abde-1a77-4450-ad66-585ab96b2a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58011
313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.58011313
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3838607362
Short name T634
Test name
Test status
Simulation time 153984797955 ps
CPU time 1962.78 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:43:43 PM PDT 24
Peak memory 273456 kb
Host smart-7b7af7e0-9bc2-4aa2-928f-a0d20946d6e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838607362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3838607362
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.832032909
Short name T666
Test name
Test status
Simulation time 73329178489 ps
CPU time 2538.6 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:53:19 PM PDT 24
Peak memory 281684 kb
Host smart-f79a04e4-251c-4621-a0c5-9dc2923c4feb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832032909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.832032909
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2077848119
Short name T289
Test name
Test status
Simulation time 12752896458 ps
CPU time 521.29 seconds
Started Mar 26 02:11:02 PM PDT 24
Finished Mar 26 02:19:44 PM PDT 24
Peak memory 247920 kb
Host smart-b13dd1fa-8a31-4ae0-b674-2b69ef80bb3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077848119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2077848119
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3125289465
Short name T73
Test name
Test status
Simulation time 1201914196 ps
CPU time 83.62 seconds
Started Mar 26 02:10:59 PM PDT 24
Finished Mar 26 02:12:24 PM PDT 24
Peak memory 256948 kb
Host smart-7bb5abe1-044e-455b-82a8-e55379f4fad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31252
89465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3125289465
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4259507513
Short name T434
Test name
Test status
Simulation time 122276245 ps
CPU time 22.2 seconds
Started Mar 26 02:11:01 PM PDT 24
Finished Mar 26 02:11:24 PM PDT 24
Peak memory 255728 kb
Host smart-73234ad8-ecbb-41fa-978e-d141337d55dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42595
07513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4259507513
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.201080250
Short name T354
Test name
Test status
Simulation time 777940325 ps
CPU time 50.38 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:11:51 PM PDT 24
Peak memory 255992 kb
Host smart-53e9564b-bba0-40f9-af49-2070d2572e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
0250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.201080250
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1475989063
Short name T236
Test name
Test status
Simulation time 29437132880 ps
CPU time 1737.15 seconds
Started Mar 26 02:10:59 PM PDT 24
Finished Mar 26 02:39:57 PM PDT 24
Peak memory 289520 kb
Host smart-787b2714-8cbc-4e0e-b93f-46e2afb2e9c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475989063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1475989063
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1932565695
Short name T40
Test name
Test status
Simulation time 94025292195 ps
CPU time 4256.72 seconds
Started Mar 26 02:11:02 PM PDT 24
Finished Mar 26 03:21:59 PM PDT 24
Peak memory 350700 kb
Host smart-e9d10996-674e-4118-b529-27b59869e645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932565695 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1932565695
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3173214523
Short name T293
Test name
Test status
Simulation time 11738797257 ps
CPU time 1163.31 seconds
Started Mar 26 02:11:18 PM PDT 24
Finished Mar 26 02:30:41 PM PDT 24
Peak memory 285516 kb
Host smart-96fdc993-382c-48fb-9103-957a2c1e3459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173214523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3173214523
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.95675488
Short name T493
Test name
Test status
Simulation time 472363295 ps
CPU time 54.94 seconds
Started Mar 26 02:11:12 PM PDT 24
Finished Mar 26 02:12:07 PM PDT 24
Peak memory 256716 kb
Host smart-b17f3a02-fea3-4654-9dad-c1456ba3a615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95675
488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.95675488
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2305076757
Short name T356
Test name
Test status
Simulation time 2520173298 ps
CPU time 40.42 seconds
Started Mar 26 02:11:09 PM PDT 24
Finished Mar 26 02:11:49 PM PDT 24
Peak memory 248884 kb
Host smart-011ced43-da85-4bef-8d68-5db964294857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
76757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2305076757
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3030445072
Short name T326
Test name
Test status
Simulation time 52746621586 ps
CPU time 3051.77 seconds
Started Mar 26 02:11:18 PM PDT 24
Finished Mar 26 03:02:10 PM PDT 24
Peak memory 289836 kb
Host smart-d68175db-99a1-475a-83bf-159422886429
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030445072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3030445072
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2105006125
Short name T299
Test name
Test status
Simulation time 16379140563 ps
CPU time 1558.66 seconds
Started Mar 26 02:11:10 PM PDT 24
Finished Mar 26 02:37:09 PM PDT 24
Peak memory 289592 kb
Host smart-d16e47d8-bdce-45c7-857f-b1204f27eafd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105006125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2105006125
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2247087245
Short name T707
Test name
Test status
Simulation time 1251434680 ps
CPU time 56.04 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:11:57 PM PDT 24
Peak memory 248792 kb
Host smart-19fc90dd-8d5d-4e68-9014-d2451043f06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22470
87245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2247087245
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2730399187
Short name T484
Test name
Test status
Simulation time 707193145 ps
CPU time 52.11 seconds
Started Mar 26 02:11:09 PM PDT 24
Finished Mar 26 02:12:01 PM PDT 24
Peak memory 254612 kb
Host smart-a01b53f1-46aa-4e48-8f12-f579d204e0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303
99187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2730399187
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2681434156
Short name T254
Test name
Test status
Simulation time 706169797 ps
CPU time 32.88 seconds
Started Mar 26 02:11:18 PM PDT 24
Finished Mar 26 02:11:51 PM PDT 24
Peak memory 248556 kb
Host smart-6cf26388-8e4a-46b5-abda-241b7d50c5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26814
34156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2681434156
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2225501175
Short name T397
Test name
Test status
Simulation time 7912555346 ps
CPU time 59.2 seconds
Started Mar 26 02:11:00 PM PDT 24
Finished Mar 26 02:11:59 PM PDT 24
Peak memory 248912 kb
Host smart-25cb4297-737b-4aa0-b512-3402b5c56838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255
01175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2225501175
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2042196252
Short name T90
Test name
Test status
Simulation time 81918088232 ps
CPU time 2694.97 seconds
Started Mar 26 02:11:12 PM PDT 24
Finished Mar 26 02:56:07 PM PDT 24
Peak memory 289552 kb
Host smart-3e25a3f0-95f5-40ab-8e22-ffc2df6e4041
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042196252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2042196252
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3972855342
Short name T692
Test name
Test status
Simulation time 89477332886 ps
CPU time 7709.32 seconds
Started Mar 26 02:11:10 PM PDT 24
Finished Mar 26 04:19:41 PM PDT 24
Peak memory 338376 kb
Host smart-6279f463-b502-4a4d-9738-7affa2cebf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972855342 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3972855342
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1902046276
Short name T443
Test name
Test status
Simulation time 41530545478 ps
CPU time 1337.36 seconds
Started Mar 26 02:11:19 PM PDT 24
Finished Mar 26 02:33:37 PM PDT 24
Peak memory 281760 kb
Host smart-06acad8a-542f-401e-a2d5-a7f216c6312b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902046276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1902046276
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4061223139
Short name T41
Test name
Test status
Simulation time 7321623624 ps
CPU time 259.06 seconds
Started Mar 26 02:11:21 PM PDT 24
Finished Mar 26 02:15:40 PM PDT 24
Peak memory 251032 kb
Host smart-8aad7529-007d-4486-8628-f947f7758ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40612
23139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4061223139
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4034556863
Short name T523
Test name
Test status
Simulation time 98371442 ps
CPU time 7.47 seconds
Started Mar 26 02:11:20 PM PDT 24
Finished Mar 26 02:11:28 PM PDT 24
Peak memory 249876 kb
Host smart-777cb085-d418-4c27-8dda-25e97d5de81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
56863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4034556863
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2635660982
Short name T272
Test name
Test status
Simulation time 16009782262 ps
CPU time 1611.4 seconds
Started Mar 26 02:11:22 PM PDT 24
Finished Mar 26 02:38:14 PM PDT 24
Peak memory 289128 kb
Host smart-e307d5fe-3bbe-4ebf-962f-080c92405568
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635660982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2635660982
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1398609392
Short name T217
Test name
Test status
Simulation time 214899281445 ps
CPU time 3210.04 seconds
Started Mar 26 02:11:22 PM PDT 24
Finished Mar 26 03:04:53 PM PDT 24
Peak memory 289264 kb
Host smart-69befb6e-bb16-4500-b900-6f93eaaf5796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398609392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1398609392
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.133754249
Short name T701
Test name
Test status
Simulation time 11482741780 ps
CPU time 448.79 seconds
Started Mar 26 02:11:20 PM PDT 24
Finished Mar 26 02:18:49 PM PDT 24
Peak memory 247892 kb
Host smart-ce9371c4-b1c7-4e68-94ff-cef653b276eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133754249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.133754249
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.6936631
Short name T27
Test name
Test status
Simulation time 1622095916 ps
CPU time 55.11 seconds
Started Mar 26 02:11:21 PM PDT 24
Finished Mar 26 02:12:16 PM PDT 24
Peak memory 256000 kb
Host smart-0f986e38-3fa4-44ec-a0c7-f861e11e5757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69366
31 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.6936631
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1934317896
Short name T538
Test name
Test status
Simulation time 149275256 ps
CPU time 13.27 seconds
Started Mar 26 02:11:36 PM PDT 24
Finished Mar 26 02:11:49 PM PDT 24
Peak memory 254884 kb
Host smart-2ca574f2-0fc3-45f2-ad7a-db0a446aa4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
17896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1934317896
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.306333851
Short name T511
Test name
Test status
Simulation time 778340573 ps
CPU time 45.95 seconds
Started Mar 26 02:11:10 PM PDT 24
Finished Mar 26 02:11:56 PM PDT 24
Peak memory 256524 kb
Host smart-fa0bc5c1-03c2-43a9-84cd-6084b045e479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30633
3851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.306333851
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.956919493
Short name T478
Test name
Test status
Simulation time 183281829315 ps
CPU time 2793.01 seconds
Started Mar 26 02:11:34 PM PDT 24
Finished Mar 26 02:58:08 PM PDT 24
Peak memory 288812 kb
Host smart-e5d550a2-5e41-46ea-989e-18dce736fa02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956919493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.956919493
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.224997568
Short name T708
Test name
Test status
Simulation time 688849171 ps
CPU time 15.9 seconds
Started Mar 26 02:11:31 PM PDT 24
Finished Mar 26 02:11:48 PM PDT 24
Peak memory 256752 kb
Host smart-547aaf0e-e7e1-4656-852c-e7564bad476e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22499
7568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.224997568
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.649015505
Short name T444
Test name
Test status
Simulation time 225032915 ps
CPU time 16.17 seconds
Started Mar 26 02:11:20 PM PDT 24
Finished Mar 26 02:11:36 PM PDT 24
Peak memory 248888 kb
Host smart-851b2232-3d5a-4a6d-8750-acc90ddcaf31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64901
5505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.649015505
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1381180823
Short name T704
Test name
Test status
Simulation time 484801981431 ps
CPU time 2113.09 seconds
Started Mar 26 02:11:35 PM PDT 24
Finished Mar 26 02:46:49 PM PDT 24
Peak memory 281724 kb
Host smart-ab7bb149-4b05-4c8d-a9ea-7a6d9d8865df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381180823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1381180823
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1177035422
Short name T486
Test name
Test status
Simulation time 32644519126 ps
CPU time 1190.35 seconds
Started Mar 26 02:11:37 PM PDT 24
Finished Mar 26 02:31:28 PM PDT 24
Peak memory 289936 kb
Host smart-b01e5a3e-8c69-44e9-9d8d-ff1b24ae223f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177035422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1177035422
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2592435003
Short name T626
Test name
Test status
Simulation time 11339192520 ps
CPU time 130.61 seconds
Started Mar 26 02:11:35 PM PDT 24
Finished Mar 26 02:13:46 PM PDT 24
Peak memory 248132 kb
Host smart-cd6aab2f-1876-4efa-bc6c-7081f58686f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592435003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2592435003
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.443459246
Short name T387
Test name
Test status
Simulation time 255824732 ps
CPU time 25.85 seconds
Started Mar 26 02:11:20 PM PDT 24
Finished Mar 26 02:11:46 PM PDT 24
Peak memory 256048 kb
Host smart-cce138e9-4b67-46a2-8339-a408a2232397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44345
9246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.443459246
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3910934671
Short name T104
Test name
Test status
Simulation time 591561530 ps
CPU time 21.65 seconds
Started Mar 26 02:11:20 PM PDT 24
Finished Mar 26 02:11:42 PM PDT 24
Peak memory 247492 kb
Host smart-66bafa12-3829-4e14-a899-d794e6c33520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39109
34671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3910934671
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1749914902
Short name T357
Test name
Test status
Simulation time 3578906224 ps
CPU time 43.91 seconds
Started Mar 26 02:11:36 PM PDT 24
Finished Mar 26 02:12:20 PM PDT 24
Peak memory 248940 kb
Host smart-11cdbcb0-8fcb-45c8-bb15-c7b38c639bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17499
14902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1749914902
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3735629986
Short name T597
Test name
Test status
Simulation time 1527949998 ps
CPU time 132.24 seconds
Started Mar 26 02:11:29 PM PDT 24
Finished Mar 26 02:13:42 PM PDT 24
Peak memory 257036 kb
Host smart-c72cdbbe-c0a0-4a18-9682-b5092693ff71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735629986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3735629986
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3224809284
Short name T381
Test name
Test status
Simulation time 41772666458 ps
CPU time 1308.15 seconds
Started Mar 26 02:11:34 PM PDT 24
Finished Mar 26 02:33:22 PM PDT 24
Peak memory 273220 kb
Host smart-2920990f-7dbd-4b43-841e-0e2304ef04f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224809284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3224809284
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1969515065
Short name T639
Test name
Test status
Simulation time 30350218849 ps
CPU time 114.84 seconds
Started Mar 26 02:11:37 PM PDT 24
Finished Mar 26 02:13:32 PM PDT 24
Peak memory 249004 kb
Host smart-4db314c8-b158-4c3c-8a1b-9fcd56344400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19695
15065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1969515065
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3220110328
Short name T438
Test name
Test status
Simulation time 1478443692 ps
CPU time 45.73 seconds
Started Mar 26 02:11:31 PM PDT 24
Finished Mar 26 02:12:17 PM PDT 24
Peak memory 255576 kb
Host smart-962fa8bf-87dc-4009-8fd2-fd07f6bec6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
10328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3220110328
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1013260646
Short name T477
Test name
Test status
Simulation time 84267369387 ps
CPU time 2111.11 seconds
Started Mar 26 02:11:44 PM PDT 24
Finished Mar 26 02:46:56 PM PDT 24
Peak memory 273448 kb
Host smart-cd5c2e76-7d8f-40d2-8345-aef19835a078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013260646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1013260646
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1262011318
Short name T213
Test name
Test status
Simulation time 51387089812 ps
CPU time 1628.11 seconds
Started Mar 26 02:11:54 PM PDT 24
Finished Mar 26 02:39:02 PM PDT 24
Peak memory 282724 kb
Host smart-a9986bbe-9720-4ac0-9877-b6e248b6a33c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262011318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1262011318
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1139496559
Short name T277
Test name
Test status
Simulation time 16804808749 ps
CPU time 124.47 seconds
Started Mar 26 02:11:41 PM PDT 24
Finished Mar 26 02:13:46 PM PDT 24
Peak memory 248124 kb
Host smart-fb3de14c-8f4b-4daf-a44b-2056f61579ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139496559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1139496559
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3076931963
Short name T210
Test name
Test status
Simulation time 28055973 ps
CPU time 2.78 seconds
Started Mar 26 02:11:34 PM PDT 24
Finished Mar 26 02:11:37 PM PDT 24
Peak memory 240664 kb
Host smart-b5559382-fbf4-4098-ae89-09d78df3b5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30769
31963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3076931963
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2771541916
Short name T55
Test name
Test status
Simulation time 1842898067 ps
CPU time 65.4 seconds
Started Mar 26 02:11:37 PM PDT 24
Finished Mar 26 02:12:43 PM PDT 24
Peak memory 248872 kb
Host smart-13619877-a5e8-47c9-9ccc-a7e0a61fc9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
41916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2771541916
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2151593676
Short name T512
Test name
Test status
Simulation time 608024468 ps
CPU time 10.93 seconds
Started Mar 26 02:11:33 PM PDT 24
Finished Mar 26 02:11:44 PM PDT 24
Peak memory 248592 kb
Host smart-dae3112a-5d30-445c-9af0-2a0a3b27d0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515
93676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2151593676
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1036384903
Short name T64
Test name
Test status
Simulation time 460794430 ps
CPU time 15.06 seconds
Started Mar 26 02:11:30 PM PDT 24
Finished Mar 26 02:11:46 PM PDT 24
Peak memory 248804 kb
Host smart-0a4fc5f4-cbbd-4e0e-8a55-23af805acda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10363
84903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1036384903
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3561815754
Short name T93
Test name
Test status
Simulation time 31529766998 ps
CPU time 2279.64 seconds
Started Mar 26 02:11:40 PM PDT 24
Finished Mar 26 02:49:40 PM PDT 24
Peak memory 287688 kb
Host smart-3bc11bc0-2127-44f4-a4c1-8fecc5bddafa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561815754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3561815754
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1905743376
Short name T89
Test name
Test status
Simulation time 87700314572 ps
CPU time 2661.39 seconds
Started Mar 26 02:11:40 PM PDT 24
Finished Mar 26 02:56:02 PM PDT 24
Peak memory 306248 kb
Host smart-eaa68653-a316-405e-b93b-7f9663ad5804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905743376 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1905743376
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2418879864
Short name T101
Test name
Test status
Simulation time 28761606596 ps
CPU time 1808.91 seconds
Started Mar 26 02:11:51 PM PDT 24
Finished Mar 26 02:42:01 PM PDT 24
Peak memory 286324 kb
Host smart-d79dd79a-af28-42d9-9111-29e8b46d1b94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418879864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2418879864
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1916284964
Short name T405
Test name
Test status
Simulation time 1749730509 ps
CPU time 136.73 seconds
Started Mar 26 02:11:49 PM PDT 24
Finished Mar 26 02:14:06 PM PDT 24
Peak memory 256716 kb
Host smart-fe04351e-a594-439e-a4a0-398ed18ab4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19162
84964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1916284964
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.870501514
Short name T384
Test name
Test status
Simulation time 682848224 ps
CPU time 27.82 seconds
Started Mar 26 02:11:52 PM PDT 24
Finished Mar 26 02:12:20 PM PDT 24
Peak memory 255780 kb
Host smart-98868a89-0285-48fa-a947-886f218b6727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87050
1514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.870501514
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.379456201
Short name T327
Test name
Test status
Simulation time 14563782668 ps
CPU time 1066.47 seconds
Started Mar 26 02:11:51 PM PDT 24
Finished Mar 26 02:29:38 PM PDT 24
Peak memory 270516 kb
Host smart-686dc3bc-a974-4864-b433-e09394210a55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379456201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.379456201
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3338581313
Short name T617
Test name
Test status
Simulation time 117927761238 ps
CPU time 2081.8 seconds
Started Mar 26 02:11:52 PM PDT 24
Finished Mar 26 02:46:35 PM PDT 24
Peak memory 285064 kb
Host smart-87d67f33-8452-4eb3-bb03-4c692a1ef2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338581313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3338581313
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3519561673
Short name T525
Test name
Test status
Simulation time 2430547500 ps
CPU time 97.75 seconds
Started Mar 26 02:11:50 PM PDT 24
Finished Mar 26 02:13:28 PM PDT 24
Peak memory 247848 kb
Host smart-1e25f78e-2c28-490a-b4b1-fe9b2ea59ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519561673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3519561673
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.313551110
Short name T495
Test name
Test status
Simulation time 1008334309 ps
CPU time 14.42 seconds
Started Mar 26 02:11:50 PM PDT 24
Finished Mar 26 02:12:04 PM PDT 24
Peak memory 252460 kb
Host smart-c7dd54e0-2a27-4556-9af4-17186045e319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31355
1110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.313551110
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4068863826
Short name T497
Test name
Test status
Simulation time 398583786 ps
CPU time 28.88 seconds
Started Mar 26 02:11:51 PM PDT 24
Finished Mar 26 02:12:20 PM PDT 24
Peak memory 255416 kb
Host smart-61eb5ee7-4c68-4404-802d-685621fed72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40688
63826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4068863826
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1805280958
Short name T584
Test name
Test status
Simulation time 2168510819 ps
CPU time 73.62 seconds
Started Mar 26 02:11:51 PM PDT 24
Finished Mar 26 02:13:05 PM PDT 24
Peak memory 256504 kb
Host smart-ac42279f-9e4d-4100-b52e-70c86d1e44ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18052
80958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1805280958
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2359404085
Short name T385
Test name
Test status
Simulation time 345701781 ps
CPU time 21.8 seconds
Started Mar 26 02:11:52 PM PDT 24
Finished Mar 26 02:12:14 PM PDT 24
Peak memory 255840 kb
Host smart-d7252e30-2b18-44eb-a562-5c96e6a3a6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23594
04085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2359404085
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.4228154344
Short name T77
Test name
Test status
Simulation time 79951118437 ps
CPU time 1635.94 seconds
Started Mar 26 02:12:07 PM PDT 24
Finished Mar 26 02:39:23 PM PDT 24
Peak memory 306244 kb
Host smart-f7f07c89-3244-4659-b703-be100a5d22a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228154344 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.4228154344
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2904002920
Short name T687
Test name
Test status
Simulation time 98753390703 ps
CPU time 1472.2 seconds
Started Mar 26 02:12:06 PM PDT 24
Finished Mar 26 02:36:39 PM PDT 24
Peak memory 272844 kb
Host smart-30710fb3-1c31-4664-ba72-7d99f7679923
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904002920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2904002920
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.188247718
Short name T394
Test name
Test status
Simulation time 890669033 ps
CPU time 56.45 seconds
Started Mar 26 02:12:06 PM PDT 24
Finished Mar 26 02:13:02 PM PDT 24
Peak memory 247604 kb
Host smart-0d6ab203-49e4-4bea-91a1-2f2a06a40c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
7718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.188247718
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1845534547
Short name T580
Test name
Test status
Simulation time 188465231 ps
CPU time 19.72 seconds
Started Mar 26 02:12:05 PM PDT 24
Finished Mar 26 02:12:25 PM PDT 24
Peak memory 255484 kb
Host smart-0711aa5d-f778-4d5b-9b56-baab45fbed59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18455
34547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1845534547
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1020262768
Short name T667
Test name
Test status
Simulation time 16106928511 ps
CPU time 796.75 seconds
Started Mar 26 02:12:06 PM PDT 24
Finished Mar 26 02:25:23 PM PDT 24
Peak memory 269356 kb
Host smart-f3cb727c-36d1-4d1b-9ee4-9abe971f20a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020262768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1020262768
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.172452619
Short name T14
Test name
Test status
Simulation time 55891172748 ps
CPU time 1449.26 seconds
Started Mar 26 02:12:18 PM PDT 24
Finished Mar 26 02:36:27 PM PDT 24
Peak memory 285936 kb
Host smart-371e45a7-a2c7-4faa-b020-6d86504fe612
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172452619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.172452619
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3282276478
Short name T281
Test name
Test status
Simulation time 3164586556 ps
CPU time 114.76 seconds
Started Mar 26 02:12:05 PM PDT 24
Finished Mar 26 02:14:00 PM PDT 24
Peak memory 247808 kb
Host smart-71b1ea45-de80-47b7-93d8-b4baa229fbd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282276478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3282276478
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1023622362
Short name T450
Test name
Test status
Simulation time 214697303 ps
CPU time 11.91 seconds
Started Mar 26 02:12:05 PM PDT 24
Finished Mar 26 02:12:17 PM PDT 24
Peak memory 253828 kb
Host smart-52cb6656-26c9-4b2c-a6a1-37818f806562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10236
22362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1023622362
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2223323419
Short name T102
Test name
Test status
Simulation time 237670876 ps
CPU time 36.7 seconds
Started Mar 26 02:12:05 PM PDT 24
Finished Mar 26 02:12:42 PM PDT 24
Peak memory 247504 kb
Host smart-04ac0a8d-72a9-401e-91e7-03430bcf3cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22233
23419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2223323419
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.19097778
Short name T662
Test name
Test status
Simulation time 50030446 ps
CPU time 3.62 seconds
Started Mar 26 02:12:05 PM PDT 24
Finished Mar 26 02:12:09 PM PDT 24
Peak memory 240584 kb
Host smart-d242d2ec-6c1b-41cf-97f7-ab55a4f9992f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19097
778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.19097778
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4119576466
Short name T571
Test name
Test status
Simulation time 397760281769 ps
CPU time 2654.56 seconds
Started Mar 26 02:12:18 PM PDT 24
Finished Mar 26 02:56:32 PM PDT 24
Peak memory 286508 kb
Host smart-cf504b7e-d836-464d-8f92-1e1b006f2264
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119576466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4119576466
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1391001313
Short name T416
Test name
Test status
Simulation time 281372598 ps
CPU time 31.5 seconds
Started Mar 26 02:12:20 PM PDT 24
Finished Mar 26 02:12:51 PM PDT 24
Peak memory 255968 kb
Host smart-d50260cb-7b7c-45e0-811c-8ecd32038555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13910
01313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1391001313
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3857140051
Short name T627
Test name
Test status
Simulation time 1693439091 ps
CPU time 37.43 seconds
Started Mar 26 02:12:18 PM PDT 24
Finished Mar 26 02:12:56 PM PDT 24
Peak memory 254808 kb
Host smart-2c2f0d80-6807-43df-9807-5e0b8acc0367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38571
40051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3857140051
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2830325981
Short name T660
Test name
Test status
Simulation time 63089630613 ps
CPU time 2709.69 seconds
Started Mar 26 02:12:27 PM PDT 24
Finished Mar 26 02:57:37 PM PDT 24
Peak memory 288896 kb
Host smart-edd1b188-b370-47c8-86d7-4d30c6ffcb8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830325981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2830325981
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1939742442
Short name T467
Test name
Test status
Simulation time 12795441957 ps
CPU time 504.95 seconds
Started Mar 26 02:12:18 PM PDT 24
Finished Mar 26 02:20:43 PM PDT 24
Peak memory 247028 kb
Host smart-30cb8ceb-1d75-4883-b93c-37d9a76bee35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939742442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1939742442
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1200170518
Short name T314
Test name
Test status
Simulation time 486215488 ps
CPU time 34.51 seconds
Started Mar 26 02:12:17 PM PDT 24
Finished Mar 26 02:12:52 PM PDT 24
Peak memory 255376 kb
Host smart-6ad9100e-c055-4c13-a85b-8f4255ebc060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12001
70518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1200170518
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3159739102
Short name T585
Test name
Test status
Simulation time 887805003 ps
CPU time 54.59 seconds
Started Mar 26 02:12:17 PM PDT 24
Finished Mar 26 02:13:12 PM PDT 24
Peak memory 255832 kb
Host smart-bff7aff1-2b2b-48c7-ab45-a3c33366718c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597
39102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3159739102
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.744495197
Short name T544
Test name
Test status
Simulation time 4240014831 ps
CPU time 62.57 seconds
Started Mar 26 02:12:19 PM PDT 24
Finished Mar 26 02:13:22 PM PDT 24
Peak memory 256636 kb
Host smart-66a9a212-d201-4949-a5cf-9300710eab56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74449
5197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.744495197
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1945040246
Short name T625
Test name
Test status
Simulation time 18031170509 ps
CPU time 61.31 seconds
Started Mar 26 02:12:17 PM PDT 24
Finished Mar 26 02:13:18 PM PDT 24
Peak memory 257088 kb
Host smart-7fe42305-02fc-4232-a770-f89a9792b4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19450
40246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1945040246
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.126057508
Short name T456
Test name
Test status
Simulation time 140766585342 ps
CPU time 2616.84 seconds
Started Mar 26 02:12:25 PM PDT 24
Finished Mar 26 02:56:02 PM PDT 24
Peak memory 289300 kb
Host smart-2affdd7d-e7d1-4fc6-9b96-94e275c51d8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126057508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.126057508
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4289402882
Short name T472
Test name
Test status
Simulation time 92579323324 ps
CPU time 2743.77 seconds
Started Mar 26 02:12:24 PM PDT 24
Finished Mar 26 02:58:09 PM PDT 24
Peak memory 281512 kb
Host smart-7e0f33e0-8268-4b8a-a4c5-c0dfcfd512b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289402882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4289402882
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2485738336
Short name T373
Test name
Test status
Simulation time 156623762 ps
CPU time 22.11 seconds
Started Mar 26 02:12:24 PM PDT 24
Finished Mar 26 02:12:47 PM PDT 24
Peak memory 255808 kb
Host smart-e2892fea-5a49-4932-bc4e-e9bdcb697620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
38336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2485738336
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.492077964
Short name T513
Test name
Test status
Simulation time 463888693 ps
CPU time 24.28 seconds
Started Mar 26 02:12:24 PM PDT 24
Finished Mar 26 02:12:49 PM PDT 24
Peak memory 255572 kb
Host smart-f44a7018-7d6d-4c3e-9cbe-d800b0cd0e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49207
7964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.492077964
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3085994016
Short name T698
Test name
Test status
Simulation time 8017203984 ps
CPU time 799.13 seconds
Started Mar 26 02:12:28 PM PDT 24
Finished Mar 26 02:25:48 PM PDT 24
Peak memory 272696 kb
Host smart-d18eb6cc-725f-43dd-8a2c-654c306db2c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085994016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3085994016
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1706837013
Short name T84
Test name
Test status
Simulation time 105637717516 ps
CPU time 1682.79 seconds
Started Mar 26 02:12:25 PM PDT 24
Finished Mar 26 02:40:29 PM PDT 24
Peak memory 273512 kb
Host smart-1ea0d157-e866-49ce-a63e-9a951b8141e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706837013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1706837013
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1557002503
Short name T276
Test name
Test status
Simulation time 10486678958 ps
CPU time 478.63 seconds
Started Mar 26 02:12:26 PM PDT 24
Finished Mar 26 02:20:25 PM PDT 24
Peak memory 247080 kb
Host smart-202c04de-0ab3-4b72-a05b-fb51e2af68da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557002503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1557002503
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2693612079
Short name T545
Test name
Test status
Simulation time 612800431 ps
CPU time 36.74 seconds
Started Mar 26 02:12:25 PM PDT 24
Finished Mar 26 02:13:02 PM PDT 24
Peak memory 248868 kb
Host smart-4e480adb-ab35-4e0a-887e-82745e4a0c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
12079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2693612079
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.306908998
Short name T656
Test name
Test status
Simulation time 254957570 ps
CPU time 9.43 seconds
Started Mar 26 02:12:24 PM PDT 24
Finished Mar 26 02:12:34 PM PDT 24
Peak memory 249060 kb
Host smart-d972d932-53ff-4221-a937-7b2f0c1e8dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30690
8998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.306908998
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2295103369
Short name T442
Test name
Test status
Simulation time 878224980 ps
CPU time 60.48 seconds
Started Mar 26 02:12:29 PM PDT 24
Finished Mar 26 02:13:30 PM PDT 24
Peak memory 248868 kb
Host smart-da638ec1-8cd9-4368-afca-ec00411614f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22951
03369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2295103369
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3369246908
Short name T349
Test name
Test status
Simulation time 1512675948 ps
CPU time 24.35 seconds
Started Mar 26 02:12:26 PM PDT 24
Finished Mar 26 02:12:50 PM PDT 24
Peak memory 248788 kb
Host smart-ca51e889-74aa-4fac-9507-f8d0a6f1c6e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33692
46908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3369246908
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2590668025
Short name T248
Test name
Test status
Simulation time 19025694499 ps
CPU time 1082.3 seconds
Started Mar 26 02:12:38 PM PDT 24
Finished Mar 26 02:30:41 PM PDT 24
Peak memory 265396 kb
Host smart-5a5d471b-4be5-4579-8915-a835621919fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590668025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2590668025
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.599343068
Short name T676
Test name
Test status
Simulation time 6216914971 ps
CPU time 751.45 seconds
Started Mar 26 02:12:38 PM PDT 24
Finished Mar 26 02:25:10 PM PDT 24
Peak memory 272544 kb
Host smart-c3fde75e-ee77-4fca-b544-870676da7aae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599343068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.599343068
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1995215546
Short name T447
Test name
Test status
Simulation time 112594209 ps
CPU time 7.87 seconds
Started Mar 26 02:12:41 PM PDT 24
Finished Mar 26 02:12:49 PM PDT 24
Peak memory 250948 kb
Host smart-2903b23f-0d00-42f8-ab7e-0200126d1a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19952
15546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1995215546
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1076547007
Short name T423
Test name
Test status
Simulation time 3246723458 ps
CPU time 59.14 seconds
Started Mar 26 02:12:38 PM PDT 24
Finished Mar 26 02:13:37 PM PDT 24
Peak memory 255648 kb
Host smart-3f5bcc0b-6f22-4cd0-b00e-5c69e5330e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10765
47007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1076547007
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4286301122
Short name T697
Test name
Test status
Simulation time 90473767227 ps
CPU time 2665.01 seconds
Started Mar 26 02:12:38 PM PDT 24
Finished Mar 26 02:57:04 PM PDT 24
Peak memory 289056 kb
Host smart-c2f40ca7-b937-46dd-8fe3-62ff231b0a02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286301122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4286301122
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3262167989
Short name T552
Test name
Test status
Simulation time 108040934889 ps
CPU time 1677.61 seconds
Started Mar 26 02:12:48 PM PDT 24
Finished Mar 26 02:40:46 PM PDT 24
Peak memory 269640 kb
Host smart-4a089ae2-a9b8-4020-a82f-4ad5193fe1d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262167989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3262167989
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.11310681
Short name T534
Test name
Test status
Simulation time 108311598174 ps
CPU time 602.72 seconds
Started Mar 26 02:12:43 PM PDT 24
Finished Mar 26 02:22:46 PM PDT 24
Peak memory 255712 kb
Host smart-47b32a98-0ac8-4ca9-8eb7-7e3020604dba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11310681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.11310681
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2550795752
Short name T575
Test name
Test status
Simulation time 533632098 ps
CPU time 22.96 seconds
Started Mar 26 02:12:38 PM PDT 24
Finished Mar 26 02:13:01 PM PDT 24
Peak memory 255996 kb
Host smart-8f89d559-4372-4ace-a32a-fc7fb976b796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25507
95752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2550795752
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2356754925
Short name T549
Test name
Test status
Simulation time 533339708 ps
CPU time 35.57 seconds
Started Mar 26 02:12:36 PM PDT 24
Finished Mar 26 02:13:12 PM PDT 24
Peak memory 249152 kb
Host smart-811eab4f-b0e0-479b-b3c8-c114194c2d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23567
54925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2356754925
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4091803020
Short name T612
Test name
Test status
Simulation time 132569698 ps
CPU time 18.84 seconds
Started Mar 26 02:12:37 PM PDT 24
Finished Mar 26 02:12:56 PM PDT 24
Peak memory 248424 kb
Host smart-42ca2088-730c-4865-a0d2-b5970078db23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40918
03020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4091803020
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.822856106
Short name T608
Test name
Test status
Simulation time 777628409 ps
CPU time 13.46 seconds
Started Mar 26 02:12:37 PM PDT 24
Finished Mar 26 02:12:51 PM PDT 24
Peak memory 248836 kb
Host smart-1ae4f53d-c66f-44e3-b394-86f303bc7493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82285
6106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.822856106
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3805401033
Short name T29
Test name
Test status
Simulation time 30557899917 ps
CPU time 1799.9 seconds
Started Mar 26 02:12:48 PM PDT 24
Finished Mar 26 02:42:48 PM PDT 24
Peak memory 283460 kb
Host smart-aa55e5e5-9219-4ca2-bec8-edcd96282677
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805401033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3805401033
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.37373860
Short name T241
Test name
Test status
Simulation time 69621974572 ps
CPU time 1076.08 seconds
Started Mar 26 02:12:50 PM PDT 24
Finished Mar 26 02:30:46 PM PDT 24
Peak memory 281824 kb
Host smart-b488dff0-66cb-44bc-add1-4dd3d8bdc932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373860 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.37373860
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3595166487
Short name T205
Test name
Test status
Simulation time 59031757 ps
CPU time 2.67 seconds
Started Mar 26 02:07:13 PM PDT 24
Finished Mar 26 02:07:16 PM PDT 24
Peak memory 249060 kb
Host smart-a8c2af12-0ffa-42b2-82fd-b703d107abf6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3595166487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3595166487
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3479201567
Short name T465
Test name
Test status
Simulation time 8049821167 ps
CPU time 833.07 seconds
Started Mar 26 02:07:11 PM PDT 24
Finished Mar 26 02:21:05 PM PDT 24
Peak memory 273452 kb
Host smart-968a05b0-8438-4dcd-b25c-8536df8a6ed0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479201567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3479201567
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1580579051
Short name T402
Test name
Test status
Simulation time 675077194 ps
CPU time 31.38 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:40 PM PDT 24
Peak memory 248764 kb
Host smart-82341b5a-0a83-4969-88f2-b62649ebab62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1580579051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1580579051
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3249487733
Short name T658
Test name
Test status
Simulation time 274405502 ps
CPU time 27.04 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:36 PM PDT 24
Peak memory 248872 kb
Host smart-d0a91766-12cb-49af-947e-646b3e49fa15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32494
87733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3249487733
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1131993932
Short name T702
Test name
Test status
Simulation time 1230875036 ps
CPU time 41.97 seconds
Started Mar 26 02:07:12 PM PDT 24
Finished Mar 26 02:07:55 PM PDT 24
Peak memory 248880 kb
Host smart-3a71ec0b-93c9-4dbd-b24f-3ec311bac2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319
93932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1131993932
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2141716672
Short name T329
Test name
Test status
Simulation time 99079599713 ps
CPU time 1688.28 seconds
Started Mar 26 02:07:10 PM PDT 24
Finished Mar 26 02:35:18 PM PDT 24
Peak memory 288864 kb
Host smart-c6698c8a-b612-4856-9429-d678a85212f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141716672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2141716672
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.853987333
Short name T579
Test name
Test status
Simulation time 13199754915 ps
CPU time 764.51 seconds
Started Mar 26 02:07:12 PM PDT 24
Finished Mar 26 02:19:57 PM PDT 24
Peak memory 265480 kb
Host smart-46c8f15a-5ff0-4b21-90e2-925fb5ae8610
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853987333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.853987333
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2729872477
Short name T268
Test name
Test status
Simulation time 114417059078 ps
CPU time 509.82 seconds
Started Mar 26 02:07:12 PM PDT 24
Finished Mar 26 02:15:42 PM PDT 24
Peak memory 247812 kb
Host smart-4912c243-c0dc-449f-9bec-9311858fbf57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729872477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2729872477
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3132864877
Short name T496
Test name
Test status
Simulation time 2734419827 ps
CPU time 42.74 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 02:07:52 PM PDT 24
Peak memory 255932 kb
Host smart-461614e1-7f30-444b-88e6-3b27fbab6965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31328
64877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3132864877
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2580812375
Short name T464
Test name
Test status
Simulation time 1901096084 ps
CPU time 57.86 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 02:08:07 PM PDT 24
Peak memory 256712 kb
Host smart-9ba5878f-ea25-425d-bb17-7e34cccc662d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25808
12375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2580812375
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1944011009
Short name T548
Test name
Test status
Simulation time 174140636 ps
CPU time 18.23 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:27 PM PDT 24
Peak memory 248832 kb
Host smart-46b6797d-176f-43da-89b9-a3a6266e0c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19440
11009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1944011009
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3887127694
Short name T599
Test name
Test status
Simulation time 1008434712 ps
CPU time 18.65 seconds
Started Mar 26 02:07:07 PM PDT 24
Finished Mar 26 02:07:26 PM PDT 24
Peak memory 254848 kb
Host smart-4cd2cbef-608d-46f6-8469-2774dd05e10b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38871
27694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3887127694
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1928247862
Short name T524
Test name
Test status
Simulation time 300005158 ps
CPU time 31.5 seconds
Started Mar 26 02:07:11 PM PDT 24
Finished Mar 26 02:07:42 PM PDT 24
Peak memory 257068 kb
Host smart-66160f70-b4a2-4aa0-83b4-2afc9773eb16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928247862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1928247862
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.375541427
Short name T197
Test name
Test status
Simulation time 87871378 ps
CPU time 3.43 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:12 PM PDT 24
Peak memory 249000 kb
Host smart-210ed808-6b45-43ce-bc73-2ff812f0b46e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=375541427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.375541427
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2751808186
Short name T50
Test name
Test status
Simulation time 15272819426 ps
CPU time 669.12 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 02:18:18 PM PDT 24
Peak memory 265420 kb
Host smart-d62822d0-1f94-4d22-94e1-0530d4c2da88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751808186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2751808186
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3802183519
Short name T369
Test name
Test status
Simulation time 472680662 ps
CPU time 9.53 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:18 PM PDT 24
Peak memory 240568 kb
Host smart-88fd1cff-8cd9-41d0-a700-1ab5422660cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3802183519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3802183519
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4149784898
Short name T690
Test name
Test status
Simulation time 13769039332 ps
CPU time 194.68 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 02:10:23 PM PDT 24
Peak memory 249900 kb
Host smart-2f582b38-01d9-4780-a06b-748086c573ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41497
84898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4149784898
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.4093678743
Short name T546
Test name
Test status
Simulation time 36037015 ps
CPU time 3.16 seconds
Started Mar 26 02:07:07 PM PDT 24
Finished Mar 26 02:07:11 PM PDT 24
Peak memory 240700 kb
Host smart-e7ce1d28-d59d-4e78-a7e8-ed4e73c96b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40936
78743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4093678743
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2370980732
Short name T315
Test name
Test status
Simulation time 27957121681 ps
CPU time 1551.04 seconds
Started Mar 26 02:07:10 PM PDT 24
Finished Mar 26 02:33:01 PM PDT 24
Peak memory 273336 kb
Host smart-bcf2ffb5-7c82-4165-865e-91a45a51b026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370980732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2370980732
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1946092993
Short name T417
Test name
Test status
Simulation time 90276304099 ps
CPU time 2731.63 seconds
Started Mar 26 02:07:07 PM PDT 24
Finished Mar 26 02:52:39 PM PDT 24
Peak memory 281776 kb
Host smart-91a6dd81-893a-45b7-88e3-c0aa043b7a8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946092993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1946092993
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.118909461
Short name T271
Test name
Test status
Simulation time 4806824045 ps
CPU time 199.86 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 02:10:29 PM PDT 24
Peak memory 248020 kb
Host smart-4d81f850-b2c1-4aef-9813-4e97245ddfdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118909461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.118909461
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3742095274
Short name T475
Test name
Test status
Simulation time 359565995 ps
CPU time 32.03 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:41 PM PDT 24
Peak memory 249040 kb
Host smart-a3269db2-7cd5-4553-96c6-bbd6ca73e4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37420
95274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3742095274
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2348710451
Short name T20
Test name
Test status
Simulation time 12882812955 ps
CPU time 60.1 seconds
Started Mar 26 02:07:11 PM PDT 24
Finished Mar 26 02:08:11 PM PDT 24
Peak memory 255676 kb
Host smart-82f24d18-921f-494c-8e83-77c2536c0373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
10451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2348710451
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.102252217
Short name T238
Test name
Test status
Simulation time 345364387 ps
CPU time 24.81 seconds
Started Mar 26 02:07:14 PM PDT 24
Finished Mar 26 02:07:39 PM PDT 24
Peak memory 254768 kb
Host smart-70a40c75-0ebc-47a5-8217-ee144cc054db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10225
2217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.102252217
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3708658534
Short name T429
Test name
Test status
Simulation time 465294264 ps
CPU time 39.42 seconds
Started Mar 26 02:07:07 PM PDT 24
Finished Mar 26 02:07:47 PM PDT 24
Peak memory 248844 kb
Host smart-d65d09d1-72e7-4856-83b8-cce2085de2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37086
58534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3708658534
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.26712527
Short name T201
Test name
Test status
Simulation time 158558938 ps
CPU time 3.27 seconds
Started Mar 26 02:07:30 PM PDT 24
Finished Mar 26 02:07:34 PM PDT 24
Peak memory 249060 kb
Host smart-cef9510b-6f12-45e8-836b-327618d89136
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=26712527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.26712527
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.947007364
Short name T562
Test name
Test status
Simulation time 95565576351 ps
CPU time 1818.41 seconds
Started Mar 26 02:07:33 PM PDT 24
Finished Mar 26 02:37:52 PM PDT 24
Peak memory 273604 kb
Host smart-2c9e4076-d384-4ac6-a29b-cddaca234d6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947007364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.947007364
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2894090319
Short name T672
Test name
Test status
Simulation time 238359239 ps
CPU time 14.52 seconds
Started Mar 26 02:07:30 PM PDT 24
Finished Mar 26 02:07:45 PM PDT 24
Peak memory 240596 kb
Host smart-8242322b-e930-4a57-95c4-a84cef429f53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2894090319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2894090319
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2907038135
Short name T551
Test name
Test status
Simulation time 349218449 ps
CPU time 22.76 seconds
Started Mar 26 02:07:10 PM PDT 24
Finished Mar 26 02:07:33 PM PDT 24
Peak memory 255088 kb
Host smart-7ea21b6e-f788-4085-b0e7-92f9c2e7f8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29070
38135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2907038135
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.544317098
Short name T362
Test name
Test status
Simulation time 1034934634 ps
CPU time 29.28 seconds
Started Mar 26 02:07:10 PM PDT 24
Finished Mar 26 02:07:40 PM PDT 24
Peak memory 255248 kb
Host smart-f92b565f-4887-4e61-ad4a-f84f5366cdab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54431
7098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.544317098
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2024618651
Short name T622
Test name
Test status
Simulation time 124886765561 ps
CPU time 1218.56 seconds
Started Mar 26 02:07:25 PM PDT 24
Finished Mar 26 02:27:44 PM PDT 24
Peak memory 273452 kb
Host smart-9e20796f-475c-4e53-9e04-989eaf409774
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024618651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2024618651
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1048748198
Short name T288
Test name
Test status
Simulation time 3430983248 ps
CPU time 139.27 seconds
Started Mar 26 02:07:28 PM PDT 24
Finished Mar 26 02:09:48 PM PDT 24
Peak memory 248180 kb
Host smart-f781e605-a189-436a-90de-409945354432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048748198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1048748198
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.227805584
Short name T348
Test name
Test status
Simulation time 6231682565 ps
CPU time 77.56 seconds
Started Mar 26 02:07:11 PM PDT 24
Finished Mar 26 02:08:29 PM PDT 24
Peak memory 257072 kb
Host smart-62c27131-9062-4f68-b468-389e104cef16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22780
5584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.227805584
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1514690160
Short name T404
Test name
Test status
Simulation time 2726245756 ps
CPU time 38.85 seconds
Started Mar 26 02:07:13 PM PDT 24
Finished Mar 26 02:07:52 PM PDT 24
Peak memory 248100 kb
Host smart-90f2a2a9-956e-4408-a5a5-4255c8b19c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
90160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1514690160
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1216701940
Short name T250
Test name
Test status
Simulation time 713198430 ps
CPU time 52.2 seconds
Started Mar 26 02:07:09 PM PDT 24
Finished Mar 26 02:08:01 PM PDT 24
Peak memory 256604 kb
Host smart-4713983f-43af-42c3-b295-d7c12a66e07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12167
01940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1216701940
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1461266443
Short name T616
Test name
Test status
Simulation time 222186972 ps
CPU time 8.27 seconds
Started Mar 26 02:07:08 PM PDT 24
Finished Mar 26 02:07:17 PM PDT 24
Peak memory 250932 kb
Host smart-95590e04-3140-46ba-86b8-12c0bab6b7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14612
66443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1461266443
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2924962449
Short name T245
Test name
Test status
Simulation time 127582424407 ps
CPU time 3814.8 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 03:11:01 PM PDT 24
Peak memory 306060 kb
Host smart-4ada186b-e2dd-4f35-bb18-847a93698aa3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924962449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2924962449
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2920511327
Short name T193
Test name
Test status
Simulation time 243501688 ps
CPU time 4.92 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 02:07:31 PM PDT 24
Peak memory 248744 kb
Host smart-c5beb4ce-0806-48ee-8a74-68ebcfe944f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2920511327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2920511327
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1246070288
Short name T498
Test name
Test status
Simulation time 54078769293 ps
CPU time 1658.57 seconds
Started Mar 26 02:07:27 PM PDT 24
Finished Mar 26 02:35:05 PM PDT 24
Peak memory 267560 kb
Host smart-6356836c-0e7f-4f02-a203-e8cab662c8a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246070288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1246070288
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.184273543
Short name T471
Test name
Test status
Simulation time 4956480706 ps
CPU time 56.91 seconds
Started Mar 26 02:07:33 PM PDT 24
Finished Mar 26 02:08:30 PM PDT 24
Peak memory 240812 kb
Host smart-5f1d61ff-0037-4807-9ce1-beb9bf9acfcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=184273543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.184273543
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4141257758
Short name T703
Test name
Test status
Simulation time 8397428336 ps
CPU time 147.59 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 02:09:54 PM PDT 24
Peak memory 251288 kb
Host smart-9ed76099-6c35-4e09-825d-38ae8b1f5834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41412
57758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4141257758
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3447837894
Short name T380
Test name
Test status
Simulation time 2324498904 ps
CPU time 38.66 seconds
Started Mar 26 02:07:27 PM PDT 24
Finished Mar 26 02:08:06 PM PDT 24
Peak memory 255516 kb
Host smart-cdd2de99-a450-41b5-be26-d69644c95a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34478
37894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3447837894
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.912059663
Short name T647
Test name
Test status
Simulation time 13748860449 ps
CPU time 1265 seconds
Started Mar 26 02:07:25 PM PDT 24
Finished Mar 26 02:28:30 PM PDT 24
Peak memory 289220 kb
Host smart-2d371d16-b37e-47ae-89d3-5a485440a0f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912059663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.912059663
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2675097938
Short name T564
Test name
Test status
Simulation time 259849581835 ps
CPU time 2577.14 seconds
Started Mar 26 02:07:25 PM PDT 24
Finished Mar 26 02:50:24 PM PDT 24
Peak memory 285044 kb
Host smart-247226ec-4614-44ed-a1c9-b4fbc35b2c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675097938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2675097938
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3831642900
Short name T8
Test name
Test status
Simulation time 12177612400 ps
CPU time 556.06 seconds
Started Mar 26 02:07:30 PM PDT 24
Finished Mar 26 02:16:47 PM PDT 24
Peak memory 246868 kb
Host smart-29bd6876-0731-44df-9429-8e262e071a59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831642900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3831642900
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2445619250
Short name T535
Test name
Test status
Simulation time 1290987512 ps
CPU time 25.92 seconds
Started Mar 26 02:07:31 PM PDT 24
Finished Mar 26 02:07:57 PM PDT 24
Peak memory 255916 kb
Host smart-b481520e-7ce8-40cd-9fb1-70a18256829f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24456
19250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2445619250
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3386118041
Short name T403
Test name
Test status
Simulation time 1381227320 ps
CPU time 33.51 seconds
Started Mar 26 02:07:30 PM PDT 24
Finished Mar 26 02:08:04 PM PDT 24
Peak memory 247568 kb
Host smart-0863236f-9325-44e5-843c-fb269bae626f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33861
18041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3386118041
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2382029705
Short name T66
Test name
Test status
Simulation time 407464514 ps
CPU time 21.68 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 02:07:48 PM PDT 24
Peak memory 247416 kb
Host smart-590dcb6f-da4e-4e7a-a3aa-2f07215e076e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
29705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2382029705
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2994771254
Short name T458
Test name
Test status
Simulation time 1290190351 ps
CPU time 41.1 seconds
Started Mar 26 02:07:24 PM PDT 24
Finished Mar 26 02:08:05 PM PDT 24
Peak memory 256000 kb
Host smart-12c79eae-f8a9-4a4d-b597-75538041ab1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29947
71254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2994771254
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.706241296
Short name T292
Test name
Test status
Simulation time 29805829370 ps
CPU time 1436.62 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 02:31:23 PM PDT 24
Peak memory 289520 kb
Host smart-b31de0bb-7d8b-4f80-a089-84c6ee9cbafe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706241296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.706241296
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3934850918
Short name T526
Test name
Test status
Simulation time 204482366416 ps
CPU time 4465.55 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 03:21:52 PM PDT 24
Peak memory 337572 kb
Host smart-f2c3689e-0fd6-408f-929a-b638faef9510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934850918 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3934850918
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1378679816
Short name T192
Test name
Test status
Simulation time 64607379 ps
CPU time 3.28 seconds
Started Mar 26 02:07:29 PM PDT 24
Finished Mar 26 02:07:34 PM PDT 24
Peak memory 249100 kb
Host smart-6f4a3057-a081-4157-9d4b-429cf9da07f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1378679816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1378679816
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1707326187
Short name T536
Test name
Test status
Simulation time 136085741646 ps
CPU time 2038.21 seconds
Started Mar 26 02:07:31 PM PDT 24
Finished Mar 26 02:41:30 PM PDT 24
Peak memory 281748 kb
Host smart-06e921e5-14f5-482e-8628-0e54e1a5e4d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707326187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1707326187
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.850593690
Short name T600
Test name
Test status
Simulation time 633094875 ps
CPU time 10.02 seconds
Started Mar 26 02:07:32 PM PDT 24
Finished Mar 26 02:07:43 PM PDT 24
Peak memory 248868 kb
Host smart-bc2d14df-bb91-479d-be02-c1e094d21d19
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=850593690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.850593690
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1072274266
Short name T372
Test name
Test status
Simulation time 480639623 ps
CPU time 10.16 seconds
Started Mar 26 02:07:32 PM PDT 24
Finished Mar 26 02:07:43 PM PDT 24
Peak memory 254216 kb
Host smart-bebdee63-76a0-4001-9a74-ae2dfd000947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722
74266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1072274266
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2776605872
Short name T436
Test name
Test status
Simulation time 1013040410 ps
CPU time 21.4 seconds
Started Mar 26 02:07:31 PM PDT 24
Finished Mar 26 02:07:53 PM PDT 24
Peak memory 254088 kb
Host smart-423d8938-c7bf-4d4c-9be5-f78613bf9680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
05872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2776605872
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4241116378
Short name T316
Test name
Test status
Simulation time 33479287879 ps
CPU time 1856.08 seconds
Started Mar 26 02:07:28 PM PDT 24
Finished Mar 26 02:38:24 PM PDT 24
Peak memory 272860 kb
Host smart-cf4518ac-e901-4bcc-99c0-c875348c9d8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241116378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4241116378
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1369647503
Short name T678
Test name
Test status
Simulation time 38854768883 ps
CPU time 2208.63 seconds
Started Mar 26 02:07:30 PM PDT 24
Finished Mar 26 02:44:20 PM PDT 24
Peak memory 281740 kb
Host smart-0f82c5ab-9500-4c12-be8f-58126ad9a0f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369647503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1369647503
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.35587803
Short name T572
Test name
Test status
Simulation time 15395922670 ps
CPU time 200.03 seconds
Started Mar 26 02:07:25 PM PDT 24
Finished Mar 26 02:10:45 PM PDT 24
Peak memory 247132 kb
Host smart-ccf6bbb3-97eb-4db5-940c-09f3f2def136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35587803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.35587803
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.676764056
Short name T38
Test name
Test status
Simulation time 93268845 ps
CPU time 6.84 seconds
Started Mar 26 02:07:29 PM PDT 24
Finished Mar 26 02:07:38 PM PDT 24
Peak memory 249024 kb
Host smart-f8564946-3c77-4f1d-a247-d8e4055f7de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67676
4056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.676764056
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2360887695
Short name T353
Test name
Test status
Simulation time 463128065 ps
CPU time 36.78 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 02:08:03 PM PDT 24
Peak memory 254944 kb
Host smart-eb2f0b24-ddc5-4bbb-b828-5206d1ef6965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23608
87695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2360887695
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1623272230
Short name T309
Test name
Test status
Simulation time 1582901618 ps
CPU time 25.67 seconds
Started Mar 26 02:07:32 PM PDT 24
Finished Mar 26 02:07:58 PM PDT 24
Peak memory 255548 kb
Host smart-b26ee409-5005-4f54-87e4-84a66517f0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
72230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1623272230
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2476343806
Short name T371
Test name
Test status
Simulation time 752516597 ps
CPU time 40.98 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 02:08:07 PM PDT 24
Peak memory 249012 kb
Host smart-5e4e4ff9-9b39-4e18-adfb-6d7bad9bf7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24763
43806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2476343806
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.448746478
Short name T670
Test name
Test status
Simulation time 382877487 ps
CPU time 41.12 seconds
Started Mar 26 02:07:32 PM PDT 24
Finished Mar 26 02:08:13 PM PDT 24
Peak memory 257064 kb
Host smart-eed31e2b-38bd-4e17-b7c5-ed5db56e2587
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448746478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.448746478
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1985803300
Short name T183
Test name
Test status
Simulation time 510106676204 ps
CPU time 5231.11 seconds
Started Mar 26 02:07:26 PM PDT 24
Finished Mar 26 03:34:38 PM PDT 24
Peak memory 339144 kb
Host smart-1e386416-f1eb-4854-810c-bc7a84431a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985803300 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1985803300
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%