Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	81557	1			T4	248		T5	570		T6	2
class_i[0x1]	47221	1			T5	291		T6	1		T46	15
class_i[0x2]	46202	1			T4	14		T12	4050		T5	2
class_i[0x3]	69000	1			T6	2		T46	9		T62	12

---

Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	62336	1			T4	237		T12	1013		T5	143
alert[0x1]	60640	1			T4	1		T12	1018		T5	294
alert[0x2]	62742	1			T12	1004		T5	276		T6	2
alert[0x3]	58262	1			T4	24		T12	1015		T5	150

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

243719

1

T4

262

T12

4050

T5

863

esc_ping_fail

261

1

T6

7

T7

3

T8

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62267	1			T4	237		T12	1013		T5	143
esc_integrity_fail	alert[0x1]	60577	1			T4	1		T12	1018		T5	294
esc_integrity_fail	alert[0x2]	62678	1			T12	1004		T5	276		T46	49
esc_integrity_fail	alert[0x3]	58197	1			T4	24		T12	1015		T5	150
esc_ping_fail	alert[0x0]	69	1			T6	2		T7	1		T8	1
esc_ping_fail	alert[0x1]	63	1			T6	1		T7	1		T308	4
esc_ping_fail	alert[0x2]	64	1			T6	2		T7	1		T308	2
esc_ping_fail	alert[0x3]	65	1			T6	2		T8	1		T307	3

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	81503	1			T4	248		T5	570		T46	186
esc_integrity_fail	class_i[0x1]	47169	1			T5	291		T46	15		T64	528
esc_integrity_fail	class_i[0x2]	46106	1			T4	14		T12	4050		T5	2
esc_integrity_fail	class_i[0x3]	68941	1			T46	9		T62	12		T29	639
esc_ping_fail	class_i[0x0]	54	1			T6	2		T7	2		T313	1
esc_ping_fail	class_i[0x1]	52	1			T6	1		T309	1		T231	2
esc_ping_fail	class_i[0x2]	96	1			T6	2		T7	1		T308	7
esc_ping_fail	class_i[0x3]	59	1			T6	2		T8	2		T322	1