Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	633039078	0	0	621
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	633039078	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	633039078	632880984	0	0
tb.dut.CheckAccuCntDw	0	0	621	621	0	0
tb.dut.CheckEscCntDw	0	0	621	621	0	0
tb.dut.CheckNAlerts	0	0	621	621	0	0
tb.dut.CheckNClasses	0	0	621	621	0	0
tb.dut.CheckNEscSev	0	0	621	621	0	0
tb.dut.CrashdumpKnownO_A	0	0	633039078	632880984	0	0
tb.dut.EdnKnownO_A	0	0	633039078	632880984	0	0
tb.dut.EscPKnownO_A	0	0	633039078	632880984	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	633039078	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	633039078	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	633039078	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	633039078	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	633039078	70	0	0
tb.dut.IrqAKnownO_A	0	0	633039078	632880984	0	0
tb.dut.IrqBKnownO_A	0	0	633039078	632880984	0	0
tb.dut.IrqCKnownO_A	0	0	633039078	632880984	0	0
tb.dut.IrqDKnownO_A	0	0	633039078	632880984	0	0
tb.dut.TlAReadyKnownO_A	0	0	633039078	632880984	0	0
tb.dut.TlDValidKnownO_A	0	0	633039078	632880984	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	662825026	2150587	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	662825026	25491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	662825026	26801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	662825026	25646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	662825026	26884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	662825026	25734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	662825026	25591	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	662825026	26766	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	662825026	26536	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	662825026	25992	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	662825026	27214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	662825026	25474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	662825026	26156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	662825026	25271	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	662825026	26403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	662825026	25456	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	662825026	25657	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	662825026	26785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	662825026	25795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	662825026	25980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	662825026	25826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	662825026	25986	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	662825026	25619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	662825026	25862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	662825026	26270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	662825026	25899	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	662825026	26087	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	662825026	26282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	662825026	27053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	662825026	25458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	662825026	25447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	662825026	25564	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	662825026	25523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	662825026	26024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	662825026	25443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	662825026	25437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	662825026	26054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	662825026	26209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	662825026	26103	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	662825026	26015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	662825026	24896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	662825026	25512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	662825026	26215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	662825026	25828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	662825026	26310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	662825026	26256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	662825026	26012	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	662825026	25849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	662825026	26733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	662825026	25392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	662825026	26328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	662825026	25693	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	662825026	25951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	662825026	26227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	662825026	26251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	662825026	25490	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	662825026	26727	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	662825026	26279	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	662825026	25654	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	662825026	25460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	662825026	25563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	662825026	25540	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	662825026	25814	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	662825026	25915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	662825026	25815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	662825026	25863	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	662825026	25844	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	662825026	26223	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	662825026	26332	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	662825026	25527	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	662825026	49968	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	662825026	25850	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	662825026	25810	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	662825026	26372	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	662825026	25508	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	662825026	25836	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	662825026	25819	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	662825026	26234	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	662825026	25322	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	633039078	8008	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	633039078	234327	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	633039078	326808553	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	633039078	219	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	633039078	773	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	633039078	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	633039078	388	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	632902808	231757572	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	633039078	883	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	633039078	863	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	633039078	847	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	633039078	834	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	633039078	786	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	633039078	90683	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	633039078	652	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	633039078	87	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	633039078	1273	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	633039078	1063	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	633039078	632880984	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	633039078	2504	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	633039078	156013	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	633039078	374394707	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	633039078	224	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	633039078	483	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	633039078	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	633039078	224	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	632902808	276372593	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	633039078	575	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	633039078	568	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	633039078	564	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	633039078	553	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	633039078	1072	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	633039078	114082	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	633039078	973	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	633039078	75	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	633039078	1221	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	633039078	1011	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	633039078	632880984	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	633039078	2744	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	633039078	187139	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	633039078	372682463	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	633039078	295	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	633039078	467	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	633039078	13	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	633039078	194	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	632902808	299744619	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	633039078	524	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	633039078	512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	633039078	504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	633039078	499	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	633039078	922	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	633039078	114839	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	633039078	852	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	633039078	54	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	633039078	1268	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	633039078	1058	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	633039078	632880984	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	633039078	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	633039078	3102	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	633039078	189187	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	633039078	360497025	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	633039078	236	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	633039078	458	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	633039078	21	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	633039078	185	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	632902808	251388286	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	633039078	533	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	633039078	524	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	633039078	514	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	633039078	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	633039078	1340	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	633039078	161319	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	633039078	1256	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	633039078	61	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	633039078	1248	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	633039078	1038	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	633039078	632880984	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	662825026	118207745	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	662825026	662187013	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	662825026	662187013	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	662825026	172761469	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	662825026	662187013	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	662825026	662187013	0	0
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