Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	87	1			T5	1		T64	1		T29	1
class_index[0x1]	75	1			T12	1		T18	1		T23	1
class_index[0x2]	54	1			T20	1		T34	2		T79	2
class_index[0x3]	61	1			T18	1		T20	1		T64	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	128	1			T20	2		T23	1		T64	1
intr_timeout_cnt[1]	50	1			T12	1		T18	2		T79	1
intr_timeout_cnt[2]	24	1			T64	1		T83	1		T51	1
intr_timeout_cnt[3]	22	1			T5	1		T29	4		T37	1
intr_timeout_cnt[4]	12	1			T101	1		T278	1		T93	2
intr_timeout_cnt[5]	12	1			T79	1		T120	1		T279	1
intr_timeout_cnt[6]	8	1			T31	1		T57	1		T278	1
intr_timeout_cnt[7]	6	1			T26	1		T27	1		T280	2
intr_timeout_cnt[8]	7	1			T112	1		T260	1		T265	1
intr_timeout_cnt[9]	8	1			T26	1		T93	1		T265	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x3]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	44	1			T37	1		T77	5		T78	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T72	1		T58	1		T92	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T64	1		T110	1		T281	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T5	1		T29	1		T37	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T101	1		T278	1		T276	2
class_index[0x0]	intr_timeout_cnt[5]	3	1			T120	1		T282	1		T283	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T57	1		T284	1		T285	1
class_index[0x0]	intr_timeout_cnt[7]	4	1			T26	1		T280	2		T286	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T282	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T287	1		T288	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	35	1			T23	1		T85	1		T113	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T12	1		T18	1		T81	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T83	1		T52	1		T26	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T29	1		T278	1		T289	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T93	1		T119	1		T239	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T279	1		T290	1		T291	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T31	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T27	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T265	1		T286	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T285	1		T286	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T20	1		T34	2		T109	1
class_index[0x2]	intr_timeout_cnt[1]	7	1			T79	1		T110	1		T292	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T51	1		T289	1		T293	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T82	1		T51	1		T93	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T119	1		T270	1		T294	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T79	1		T295	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T296	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T297	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T112	1		T260	1		T288	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T286	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	29	1			T20	1		T64	1		T77	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T18	1		T71	1		T110	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T93	1		T298	1		T299	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T29	2		T300	1		T294	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T93	1		T282	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T296	2		T283	1		T301	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T278	1		T302	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T26	1		T93	1		T265	1