Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340391	1			T1	1677		T2	31		T3	1527
all_values[1]	340391	1			T1	1677		T2	31		T3	1527
all_values[2]	340391	1			T1	1677		T2	31		T3	1527
all_values[3]	340391	1			T1	1677		T2	31		T3	1527

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677393

1

T1

3341

T2

58

T3

3021

auto[1]

684171

1

T1

3367

T2

66

T3

3087

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814188

1

T1

4430

T2

64

T3

3064

auto[1]

547376

1

T1

2278

T2

60

T3

3044

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96852	1			T1	518		T2	6		T3	388
all_values[0]	auto[0]	auto[1]	72659	1			T1	324		T2	6		T3	385
all_values[0]	auto[1]	auto[0]	97977	1			T1	531		T2	10		T3	378
all_values[0]	auto[1]	auto[1]	72903	1			T1	304		T2	9		T3	376
all_values[1]	auto[0]	auto[0]	102457	1			T1	522		T2	12		T3	388
all_values[1]	auto[0]	auto[1]	66957	1			T1	312		T2	11		T3	384
all_values[1]	auto[1]	auto[0]	103930	1			T1	533		T2	4		T3	379
all_values[1]	auto[1]	auto[1]	67047	1			T1	310		T2	4		T3	376
all_values[2]	auto[0]	auto[0]	102474	1			T1	513		T2	7		T3	370
all_values[2]	auto[0]	auto[1]	67591	1			T1	307		T2	6		T3	370
all_values[2]	auto[1]	auto[0]	102894	1			T1	539		T2	9		T3	394
all_values[2]	auto[1]	auto[1]	67432	1			T1	318		T2	9		T3	393
all_values[3]	auto[0]	auto[0]	102508	1			T1	653		T2	5		T3	369
all_values[3]	auto[0]	auto[1]	65895	1			T1	192		T2	5		T3	367
all_values[3]	auto[1]	auto[0]	105096	1			T1	621		T2	11		T3	398
all_values[3]	auto[1]	auto[1]	66892	1			T1	211		T2	10		T3	393