Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340391	1			T1	1677		T2	31		T3	1527
all_pins[1]	340391	1			T1	1677		T2	31		T3	1527
all_pins[2]	340391	1			T1	1677		T2	31		T3	1527
all_pins[3]	340391	1			T1	1677		T2	31		T3	1527

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1087290	1			T1	5565		T2	92		T3	4570
values[0x1]	274274	1			T1	1143		T2	32		T3	1538
transitions[0x0=>0x1]	182578	1			T1	816		T2	21		T3	965
transitions[0x1=>0x0]	182833	1			T1	817		T2	22		T3	966

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	267488	1			T1	1373		T2	22		T3	1151
all_pins[0]	values[0x1]	72903	1			T1	304		T2	9		T3	376
all_pins[0]	transitions[0x0=>0x1]	72248	1			T1	303		T2	8		T3	375
all_pins[0]	transitions[0x1=>0x0]	66492	1			T1	211		T2	10		T3	393
all_pins[1]	values[0x0]	273344	1			T1	1367		T2	27		T3	1151
all_pins[1]	values[0x1]	67047	1			T1	310		T2	4		T3	376
all_pins[1]	transitions[0x0=>0x1]	36473	1			T1	186		T2	3		T3	181
all_pins[1]	transitions[0x1=>0x0]	42329	1			T1	180		T2	8		T3	181
all_pins[2]	values[0x0]	272959	1			T1	1359		T2	22		T3	1134
all_pins[2]	values[0x1]	67432	1			T1	318		T2	9		T3	393
all_pins[2]	transitions[0x0=>0x1]	37577	1			T1	200		T2	6		T3	220
all_pins[2]	transitions[0x1=>0x0]	37192	1			T1	192		T2	1		T3	203
all_pins[3]	values[0x0]	273499	1			T1	1466		T2	21		T3	1134
all_pins[3]	values[0x1]	66892	1			T1	211		T2	10		T3	393
all_pins[3]	transitions[0x0=>0x1]	36280	1			T1	127		T2	4		T3	189
all_pins[3]	transitions[0x1=>0x0]	36820	1			T1	234		T2	3		T3	189