Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T170	4		T171	7		T172	7
all_values[1]	269	1			T170	4		T171	7		T172	7
all_values[2]	269	1			T170	4		T171	7		T172	7
all_values[3]	269	1			T170	4		T171	7		T172	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

602

1

T170

9

T171

10

T172

12

auto[1]

474

1

T170

7

T171

18

T172

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

444

1

T170

5

T171

19

T172

19

auto[1]

632

1

T170

11

T171

9

T172

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

654

1

T170

11

T171

22

T172

20

auto[1]

422

1

T170

5

T171

6

T172

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

78

1

T170

1

T171

2

T172

2

all_values[0]

auto[0]

auto[0]

auto[1]

24

1

T352

3

T353

1

T354

1

all_values[0]

auto[0]

auto[1]

auto[0]

52

1

T170

2

T171

3

T172

4

all_values[0]

auto[0]

auto[1]

auto[1]

17

1

T355

1

T356

1

T357

1

all_values[0]

auto[1]

auto[0]

auto[1]

60

1

T171

2

T358

1

T355

1

all_values[0]

auto[1]

auto[1]

auto[1]

38

1

T170

1

T172

1

T358

1

all_values[1]

auto[0]

auto[0]

auto[0]

55

1

T172

3

T355

1

T356

1

all_values[1]

auto[0]

auto[0]

auto[1]

21

1

T358

1

T355

1

T354

2

all_values[1]

auto[0]

auto[1]

auto[0]

50

1

T171

5

T172

2

T356

3

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T170

2

T171

1

T172

1

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T170

1

T171

1

T358

2

all_values[1]

auto[1]

auto[1]

auto[1]

48

1

T170

1

T172

1

T352

3

all_values[2]

auto[0]

auto[0]

auto[0]

76

1

T171

1

T172

3

T358

3

all_values[2]

auto[0]

auto[0]

auto[1]

28

1

T170

3

T171

1

T355

1

all_values[2]

auto[0]

auto[1]

auto[0]

40

1

T171

3

T172

1

T355

1

all_values[2]

auto[0]

auto[1]

auto[1]

32

1

T356

1

T352

1

T354

2

all_values[2]

auto[1]

auto[0]

auto[1]

49

1

T170

1

T171

1

T172

1

all_values[2]

auto[1]

auto[1]

auto[1]

44

1

T171

1

T172

2

T356

3

all_values[3]

auto[0]

auto[0]

auto[0]

45

1

T170

1

T171

1

T172

3

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T170

1

T171

1

T356

1

all_values[3]

auto[0]

auto[1]

auto[0]

48

1

T170

1

T171

4

T172

1

all_values[3]

auto[0]

auto[1]

auto[1]

31

1

T358

1

T355

1

T352

2

all_values[3]

auto[1]

auto[0]

auto[1]

72

1

T170

1

T355

1

T356

2

all_values[3]

auto[1]

auto[1]

auto[1]

45

1

T171

1

T172

3

T358

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal